# Intelligent Power Module (IPM), 3-Phase, IGBT, 600 V, 3 A, 1 kV, NDIP, SLLIMM

![Product image](https://novapart.co/image/farnell:2807349/)

**URL**: https://novapart.co/products/STGIPN3H60T-H/intelligent-power-module-ipm-3-phase-igbt-600-v-a
**SKU**: STGIPN3H60T-H
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || Intelligent Power Modules
**Price**: €4.3900
**Stock**: 10+
**Lead Time**: 127 days (indicative)

## Description

IPM Power Device:IGBT; Voltage Rating (Vces / Vdss):600V; Current Rating (Ic / Id):3A; Isolation Voltage:1kV; IPM Case Style:NDIP; IPM Series:SLLIMM; Product Range:SLLIMM Nano Series;

## Specifications

| Parameter | Value |
|---|---|
| Svhc | No SVHC (25-Jun-2025) |
| Ipm Series | SLLIMM |
| Product Range | SLLIMM Nano Series |
| Ipm Case Style | NDIP |
| Ipm Power Device | IGBT |
| Isolation Voltage | 1kV |
| Current Rating (Ic / Id) | 3A |
| Voltage Rating (Vces / Vdss) | 600V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2807349/)

## **STGIPN3H60T-H** 

SLLIMM™-nano small low-loss intelligent molded module IPM, 3 A, 600 V, 3-phase IGBT inverter bridge 

Datasheet - production data 

## **Applications** 

- 3-phase inverters for motor drives 

- Dish washers, refrigerator compressors, heating systems, air-conditioning fans, draining and recirculation pumps 

## **Description** 

## **Features** 

- IPM 3 A, 600 V, 3-phase IGBT inverter bridge including control ICs for gate driving and freewheeling diodes 

- Optimized for low electromagnetic interference 

- VCE(sat) negative temperature coefficient 

This SLLIMM (small low-loss intelligent molded module) nano provides a compact, high performance AC motor drive in a simple, rugged design. It is composed of six MOSFETs and three half-bridge HVICs for gate driving, providing low electromagnetic interference (EMI) characteristics with optimized switching speed. The package is optimized for thermal performance and compactness in built-in motor applications, or other low power applications where assembly space is limited. This IPM includes an operational amplifier, completely uncommitted, and a comparator that can be used to design a fast and efficient protection circuit. SLLIMM™ is a trademark of STMicroelectronics. 

- 3.3 V, 5 V, 15 V CMOS/TTL input comparators with hysteresis and pulldown/pull-up resistors 

- Undervoltage lockout 

- Internal bootstrap diode 

- Interlocking function 

- Smart shutdown function 

- Comparator for fault protection against overtemperature and overcurrent 

- Op-amp for advanced current sensing 

- Optimized pinout for board layout 

- NTC for temperature control (UL 1434 CA 2 and 4) 

**Table 1: Device summary** 

|**Order code**|**Marking**|**Package**|**Packing**|
|---|---|---|---|
|STGIPN3H60T-H|GIPN3H60T-H|NDIP-26L|Tube|



This is information on a product in full production. 

_www.st.com_ 

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|**Contents**<br>**STGIPN3H60T-H**|**Contents**<br>**STGIPN3H60T-H**|
|---|---|
|**Contents**||
|**1**|**Internal schematic diagram and pin configuration ....................... 3**|
|**2**|**Electrical ratings ............................................................................. 6**|
||2.1<br>Absolute maximum ratings ................................................................ 6|
||2.2<br>Thermal data ..................................................................................... 7|
|**3**|**Electrical characteristics ................................................................ 8**|
||3.1<br>Inverter part ....................................................................................... 8|
||3.2<br>Control part ..................................................................................... 10|
||3.2.1<br>NTC thermistor ................................................................................. 12|
||3.3<br>Waveform definitions ....................................................................... 15|
|**4**|**Smart shutdown function ............................................................. 16**|
|**5**|**Application circuit example .......................................................... 18**|
||5.1<br>Guidelines ....................................................................................... 19|
|**6**|**Package information ..................................................................... 21**|
||6.1<br>NDIP-26L type C package information ............................................ 22|
||6.2<br>NDIP-26L packing information ........................................................ 24|
|**7**|**Revision history ............................................................................ 25**|



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**Internal schematic** diagram and pin configuration 

## **1 Internal schematic diagram and pin configuration** 

**Figure 1: Internal schematic diagram** 

**==> picture [464 x 460] intentionally omitted <==**

**----- Start of picture text -----**<br>
GND (1) N W (26)<br>T/ SD / OD (2) NTC<br>GND W, OUT W (25)<br>Vcc W (3) HVG<br>OUT Vboo t W (24)<br>HIN W (4) VCC<br>HIN LVG<br>SD/OD<br>LINW (5) LIN Vboot<br>OP+ (6)<br>N V (23)<br>OPOUT (7) GND OP+<br>OPOUT<br>OP- (8) OP- HVG V, OUT V (22)<br>OUT<br>VCC<br>Vcc V (9) HIN LVG<br>SD/OD<br>LIN Vboot<br>HIN V (10)<br>Vboo t V (21)<br>LIN V (11)<br>GND N U (20)<br>CIN (12) CIN<br>HVG<br>Vcc U (13)<br>OUT U, OUT U (19)<br>VCC<br>HIN U (14) HIN LVG<br>SD/OD<br>LIN Vboot P (18)<br>T / SD / OD (15)<br>LIN U (16) Vboo t U (17)<br>**----- End of picture text -----**<br>


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**Internal schematic** diagram and pin configuration 

**Table 2: Pin description** 

|**Pin**|**Symbol**|**Description**|
|---|---|---|
|1|GND|Ground|
|2|T/ SD<br>/ OD|NTC thermistor terminal / shutdown logic input (active low) / open-drain<br>(comparator output)|
|3|VCCW|Low voltagepower supplyWphase|
|4|HIN W|High-side logic input for Wphase|
|5|LIN W|Low-side logic input for Wphase|
|6|OP+|Op-ampnon-invertinginput|
|7|OPOUT|Op-ampoutput|
|8|OP-|Op-ampinvertinginput|
|9|VCCV|Low voltagepower supplyVphase|
|10|HIN V|High-side logic input for Vphase|
|11|LIN V|Low-side logic input for Vphase|
|12|CIN|Comparator input|
|13|VCCU|Low voltagepower supplyfor Uphase|
|14|HIN U|High-side logic input for Uphase|
|15|T/ SD<br>/ OD|NTC thermistor terminal / shutdown logic input (active low) / open-drain<br>(comparator output)|
|16|LIN U|Low-side logic input for Uphase|
|17|VBOOTU|Bootstrapvoltage for Uphase|
|18|P|Positive DC input|
|19|U, OUTU|Uphase output|
|20|NU|Negative DC input for Uphase|
|21|VBOOTV|Bootstrapvoltage for Vphase|
|22|V, OUTV|Vphase output|
|23|NV|Negative DC input for Vphase|
|24|VBOOTW|Bootstrapvoltage for Wphase|
|25|W, OUTW|Wphase output|
|26|NW|Negative DC input for Wphase|



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## **Internal schematic** diagram and pin configuration 

**Figure 2: Pin layout (top view)** 

**==> picture [406 x 239] intentionally omitted <==**

**----- Start of picture text -----**<br>
PIN26 (*) (*) PIN17<br>PIN #1 ID<br>PIN1 PIN16<br>(*) Dummy pin internally connected to P (positive DC input). AM09368V1<br>**----- End of picture text -----**<br>


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**Electrical ratings** 

## **2 Electrical ratings** 

## **2.1 Absolute maximum ratings** 

**Table 3: Inverter part** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VCES|Each IGBT collector emitter voltage (VIN_(1)_= 0)|600|V|
|± IC_(2)_|Each IGBT continuous collector current at TC= 25 °C|3|A|
|± ICP_(3)_|Each IGBTpulsed collector current|18|A|
|PTOT|Each IGBT total dissipation at TC= 25 °C|8|W|



## **Notes:** 

(1)Applied among HINi, LINi and GND for i = U, V, W. 

(2)Calculated according to the iterative formula: 

(3)Pulse width limited by max. junction temperature. 

**Table 4: Control part** 

|**Symbol**|**Parameter**|**Min.**|**Max.**|**Unit**|
|---|---|---|---|---|
|VOUT|Output voltage applied among OUTU, OUTV, OUTW-<br>GND|Vboot- 21|Vboot+ 0.3|V|
|VCC|Low voltagepower supply|- 0.3|21|V|
|VCIN|Comparator input voltage|- 0.3|VCC+ 0.3|V|
|Vop+|Op-ampnon-invertinginput|- 0.3|VCC+ 0.3|V|
|Vop-|Op-ampinvertinginput|- 0.3|VCC+ 0.3|V|
|Vboot|Bootstrapvoltage|- 0.3|620|V|
|VIN|Logic input voltage applied amongHIN, LIN and GND|- 0.3|15|V|
|𝑉𝑇/𝑆𝐷<br>̅̅̅̅/𝑂𝐷|Open-drain voltage|- 0.3|15|V|
|∆VOUT/dT|Allowed output slew rate||50|V/ns|



**Table 5: Total system** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VISO|Isolation withstand voltage applied among each pin and<br>heatsinkplate (AC voltage, t = 60 s)|1000|V|
|Tj|Power chipoperating junction temperature range|-40 to 150|°C|
|TC|Module operation case temperature range|-40 to 125|°C|



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**Electrical ratings** 

## **2.2 Thermal data** 

||**Table 6: Thermal data**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|RthJA|Thermal resistance junction-ambient|50|°C/W|



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**Electrical characteristics** 

## **3 Electrical characteristics** 

## **3.1** 

## **Inverter part** 

TJ = 25 °C unless otherwise specified. 

**Table 7: Static** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VCE(sat)|Collector-emitter saturation<br>voltage|VCC= Vboot= 15 V,<br>VIN_(1)_= 0 to 5 V, IC= 1 A|-|2.15|2.6|V|
|||VCC= Vboot= 15 V,<br>VIN_(1)_= 0 to 5 V, IC= 1 A,<br>TJ= 125 °C|-|1.65|||
|ICES|Collector cut-off current<br>(VIN_(1)_= 0 “logic state”)|VCE= 550 V,<br>VCC= VBoot= 15 V|-||250|µA|
|VF|Diode forward voltage|VIN_(1)_= 0 “logic state”,<br>IC= 1 A|-||1.7|V|



## **Notes:** 

(1)Applied among HINi, LINi and GND for i = U, V, W. 

**Table 8: Inductive load switching time and energy** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ton_(1)_|Turn-on time|VDD= 300 V,<br>VCC= Vboot= 15 V,<br>VIN_(2)_= 0 to 5 V,<br>IC= 1 A<br>(see_Figure 4: "Switching_<br>_time definition"_)|-|275|-|ns|
|tc(on)_(1)_|Crossover time (on)||-|90|-||
|toff_(1)_|Turn-off time||-|890|-||
|tc(off)_(1)_|Crossover time (off)||-|125|-||
|trr|Reverse recoverytime||-|50|-||
|Eon|Turn-on switchingenergy||-|18|-|µJ|
|Eoff|Turn-off switchingenergy||-|13|-||



## **Notes:** 

(1)tON and tOFF include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are the switching time of MOSFET itself under the internally given gate driving conditions. 

(2)Applied among HINi, LINi and GND for i = U, V, W. 

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**Figure 3: Switching time test circuit** 

**Figure 4: Switching time definition** 

_Figure 4: "Switching time definition"_ refers to HIN, LIN inputs (active high). 

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## **Electrical characteristics** 

## **3.2 Control part** 

**Table 9: Low voltage power supply (VCC = 15 V unless otherwise specified)** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VCC_hys|VCCUV hysteresis||1.2|1.5|1.8|V|
|VCC_thON|VCCUV turn-ON threshold||11.5|12|12.5|V|
|VCC_thOFF|VCCUV turn-OFF threshold||10|10.5|11|V|
|Iqccu|Undervoltage quiescent supply<br>current|VCC= 10 V, T/ SD<br>/OD = 5 V; LIN = 0,<br>HIN= 0, CIN= 0 V|||150|µA|
|Iqcc|Quiescent current|Vcc= 15 V, T/ SD<br>/OD = 5 V; LIN = 0;<br>HIN= 0, CIN= 0 V|||1|mA|
|Vref|Internal comparator (CIN)<br>reference voltage||0.5|0.54|0.58|V|



**Table 10: Bootstrapped voltage (VCC = 15 V unless otherwise specified)** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VBS_hys|VBSUV hysteresis||1.2|1.5|1.8|V|
|VBS_thON|VBSUV turn-ON threshold||11.1|11.5|12.1|V|
|VBS_thOFF|VBSUV turn-OFF threshold||9.8|10|10.6|V|
|IQBSU|Undervoltage VBSquiescent<br>current|VBS< 9 V, T/ SD<br>/OD = 5 V, LIN = 0<br>HIN=5 V, CIN= 0 V||70|110|µA|
|IQBS|VBSquiescent current|VBS=15 V, T/ SD<br>/OD = 5 V, LIN = 0<br>HIN=5 V, CIN= 0 V||150|210|µA|
|RDS(on)|Bootstrapdriver on-resistance|LVG ON||120||Ω|



**Table 11: Logic inputs (VCC = 15 V unless otherwise specified)** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Vil|Low logic level voltage||||0.8|V|
|Vih|High logic level voltage||2.25|||V|
|IHINh|HIN logic “1” input bias current|HIN = 15 V|20|40|100|µA|
|IHINI|HIN logic “0” input bias current|HIN = 0 V|||1|µA|
|ILINh|LIN logic “1” input bias current|LIN = 15 V|20|40|100|µA|
|ILINI|LIN logic “0” input bias current|LIN = 0 V|||1|µA|
|ISDh|SD<br>logic “0” input bias<br>current|SD<br>= 15 V|220|295|370|µA|
|ISDI|SD<br>logic “1” input bias<br>current|SD<br>= 0 V|||3|µA|
|Dt|Dead time|see_Figure 9: "Dead time and_<br>_interlocking waveform definitions"_||180||ns|



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**Electrical characteristics** 

**Table 12: Op-amp characteristics (VCC = 15 V unless otherwise specified)** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Vio|Input offset voltage|Vic= 0 V, Vo= 7.5 V|||6|mV|
|Iio|Input offset current|Vic= 0 V, Vo= 7.5 V||4|40|nA|
|Iib|Input bias current_(1)_|||100|200|nA|
|Vicm|Input common mode voltage range||0|||V|
|VOL|Low level output voltage|RL= 10 kΩ to VCC||75|150|mV|
|VOH|High level output voltage|RL= 10 kΩ to GND|14|14.7||V|
|Io|Output short-circuit current|Source, Vid= + 1 V; Vo= 0 V|16|30||mA|
|||Sink, Vid= -1 V; Vo= VCC|50|80||mA|
|SR|Slew rate|Vi= 1 - 4 V; CL= 100pF; unity gain|2.5|3.8||V/µs|
|GBWP|Gain bandwidthproduct|Vo= 7.5 V|8|12||MHz|
|Avd|Large signal voltagegain|RL= 2 kΩ|70|85||dB|
|SVR|Supplyvoltage rejection ratio|vs. VCC|60|75||dB|
|CMRR|Common mode rejection ratio||55|70||dB|



## **Notes:** 

(1)The direction of input current is out of the IC. 

**Table 13: Sense comparator characteristics (VCC = 15 V unless otherwise specified)** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Iib|Input bias current|VCIN= 1 V|||3|µA|
|Vod|Open-drain low level output voltage|Iod= 3 mA|||0.5|V|
|RON_OD|Open-drain low level output resistance|Iod= 3 mA||166||Ω|
|RPD_SD|SD<br>pull-down resistor_(1)_|||125||kΩ|
|td_comp|Comparator delay|T/ SD<br>/OD pulled to 5 V through<br>100 kΩ resistor||90|130|ns|
|SR|Slew rate|CL= 180pF; Rpu= 5 kΩ||60||V/μs|
|tsd|Shutdown to high / low-side driver<br>propagation delay|VOUT= 0, Vboot= VCC,<br>VIN= 0 to 3.3 V|50|125|200|ns|
|tisd|Comparator triggering to high / low-<br>side driver turn-off propagation delay|Measured applying a voltage step<br>from 0 V to 3.3 V to pin CIN|50|200|250||



## **Notes:** 

(1)Equivalent value derived from the resistances of three drivers in parallel 

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## **Electrical characteristics** 

|**Electrical characteristics**||||**STGIPN3H60T-H**|**STGIPN3H60T-H**|
|---|---|---|---|---|---|
||**Table 14: Truth table**|||||
|**Condition**|**Logic input (VI) **|||**Output**||
||**T/ SD**<br>**/OD**|**LIN**|**HIN**|**LVG**|**HVG**|
|Shutdown enable half-bridge tri-state|L|X_(1)_|X_(1)_|L|L|
|Interlockinghalf-bridge tri-state|H|H|H|L|L|
|0 “logic state” half-bridge tri-state|H|L|L|L|L|
|1 “logic state” low-side direct driving|H|H|L|H|L|
|1 “logic state” high-side direct driving|H|L|H|L|H|



## **Notes:** 

(1)X: don’t care. 

## **3.2.1 NTC thermistor** 

## **Figure 5: Internal structure of** ̅̅̅̅̅𝐒𝐃 **and NTC** 

**==> picture [406 x 182] intentionally omitted <==**

**----- Start of picture text -----**<br>
Vbias<br>R SD<br>VT/SD/OD LIN Vboot<br>SD/OD<br>C SD NTC HIN HVG<br>VCC<br>OUT<br>RPD_SD<br>LVG<br>GND CIN<br>**----- End of picture text -----**<br>


RPD_SD: equivalent value as result of resistances of three drivers in parallel. 

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**Electrical characteristics** 

**Figure 6: Equivalent resistance (NTC//RPD_SD)** 

**Figure 7: Equivalent resistance (NTC//RPD_SD zoom)** 

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**Electrical characteristics** 

**Figure 8: Voltage of T/** 𝐒𝐃̅̅̅̅ **/OD pin according to NTC temperature** 

**==> picture [407 x 295] intentionally omitted <==**

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**Electrical characteristics** 

## **3.3 Waveform definitions** 

**Figure 9: Dead time and interlocking waveform definitions** 

**==> picture [406 x 349] intentionally omitted <==**

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**Smart shutdown** function 

**STGIPN3H60T-H** 

## **4 Smart shutdown function** 

The device integrates a comparator for fault sensing purposes. The comparator has an internal voltage reference VREF connected to the inverting input, while the non-inverting input on pin (CIN) can be connected to an external shunt resistor for simple overcurrent protection. 

When the comparator triggers, the device goes to the shutdown state and both of its outputs are set to low level, causing the half-bridge to enter tri-state. 

In common overcurrent protection architectures, the comparator output is usually connected to the shutdown input through an RC network so to provide a monostable circuit which implements a protection time following to a fault condition. 

Our smart shutdown architecture immediately turns off the output gate driver in case of overcurrent through a preferential path for the fault signal, which directly switches off the outputs. The time delay between the fault and output shutdown no longer depends on the RC values of the external network connected to the shutdown pin. At the same time, the 

DMOS connected to the open-drain output (pin T/ SD /OD) is turned on by the internal logic, which holds it on until the shutdown voltage is lower than the minimum value of logic input threshold (Vil). 

Besides, the smart shutdown function allows the real disable time to be increased while the constant time of the external RC network remains as it is. 

An NTC thermistor for temperature monitoring is internally connected in parallel to the 

SD pin. To avoid undesired shutdown, keep the voltage 𝑉𝑇/𝑆𝐷̅̅̅̅/𝑂𝐷 higher than the high ̅̅̅̅ level logic threshold by setting the pull-up resistor 𝑅𝑆𝐷 to 1 kΩ or 2.2 kΩ for the 3.3 V or 5 V MCU power supplies, respectively. 

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**Smart shutdown** function 

**Figure 10: Smart shutdown timing waveforms** 

**==> picture [253 x 281] intentionally omitted <==**

**----- Start of picture text -----**<br>
comp Vref<br>CP+<br>HIN/LIN<br>PROTECTION<br>HVG/LVG<br>SD/OD<br>open-drain gate<br>(internal)<br>disable time<br>Fast shutdown:<br>the driver outputs are set to the SD state as soon as the comparator<br>triggers even if the SD signal hasn’t reached the lowest input threshold<br>**----- End of picture text -----**<br>


**==> picture [396 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
An approximation of the disable time is given by:<br>Vbias SHUTDOWN CIRCUIT<br>R SD<br>VT/SD/OD T/SD/ OD<br>SMART SD<br>C SD<br>LOGIC<br>NTC RPD_SD RON_OD<br>**----- End of picture text -----**<br>


**==> picture [67 x 6] intentionally omitted <==**

**----- Start of picture text -----**<br>
GIPG080920140931FSR<br>**----- End of picture text -----**<br>


Please refer to _Table 13: "Sense comparator characteristics (VCC = 15 V unless otherwise specified)"_ for internal propagation delay time details. 

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**Application circuit** example 

## **5 Application circuit example** 

**Figure 11: Application circuit example** 

**==> picture [464 x 552] intentionally omitted <==**

**----- Start of picture text -----**<br>
MICROCONTROLLER<br>GAD250720161156FSR<br>C4<br>D<br>PW R_GN<br>Rshunt<br>DZ2 DZ2<br>C3 C3<br>Cboot U Cboot V Cboot W<br>Vboot V (21) V, OUT V (22) W, OUT W (25) N W (26) RS<br>HVG LVG HVG LVG OP+ HVG OUT LVG<br>LIN SD/OD HIN GND SD/OD HIN OP- GND SD/OD HIN VCC GND<br>LIN U (16) HIN U (14) Vcc U (13) Vcc V (9) OP- (8) OPOUT (7) Vcc W (3) GND (1)<br>C SF D<br>C1 C1 C1 C1 C1 SGN_GN DZ1<br>R SF R5<br>R4<br>R1 R1 R1 R1<br>RS<br>R2 R3 R SD<br>R1<br>LIN U HIN U HIN V ADC LIN W<br>SD Te m p .<br>VDC<br>+ -<br>Cvdc<br>DZ2<br>C3<br>Vboot U (17) P (18) U, OUT U (19) N U (20) N V (23) Vboot W (24)<br>NTC<br>CIN (12) LIN V (11) HIN V (10) OP+ (6) LINW (5) HIN W (4)<br>T / SD / OD (15) T / SD / OD (2)<br>C OP<br>C1<br>ADC<br>R1 R1 C 2<br>C SD Ccvc<br>5V / 3.3V 5V / 3.3V C<br>+ VC -<br>RS<br>LIN V HIN W Monitoring<br>M<br>Vboot OUT CIN Vboot OUT Vboot<br>VCC LIN VCC OPOUT LIN<br>**----- End of picture text -----**<br>


Application designers are free to use a different scheme according to the specifications of the device. 

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**Application circuit** example 

## **5.1 Guidelines** 

- Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull-down resistor is builtin for each input. To avoid the input signal oscillation, the wiring of each input should be as short as possible and the use of RC filters (R1, C1) on each input signal is suggested. The filters should be with a time constant of about 100 ns and placed as close as possible to the IPM input pins. 

- The use of a bypass capacitor CVCC (aluminum or tantalum) can help to reduce the transient circuit demand on the power supply. Besides, to reduce high frequency switching noise distributed on the power lines, a decoupling capacitor C2 (100 to 220 nF, with low ESR and low ESL) should be placed as close as possible to Vcc pin and in parallel whit the bypass capacitor. 

- The use of an RC filter (RSF, CSF) is recommended to avoid protection circuit malfunction. The time constant (RSF x CSF) should be set to 1 µs and the filter must be placed as close as possible to the CIN pin. 

- The SD is an input/output pin (open-drain type if it is used as output). A built-in 

thermistor NTC is internally connected between the SD pin and GND. The voltage VSD-GND decreases as the temperature increases, due to the pull-up resistor RSD. In order to keep the voltage always higher than the high level logic threshold, the pull-up resistor is suggested to be set to 1 kΩ or 2.2 kΩ for 3.3 V or 5 V MCU power supply, 

respectively. The CSD capacitor of the filter on SD should be fixed no higher than 3.3 

nF to ensure the SD activation time τ1 ≤ 500 ns; the filter should be placed as close 

as possible to the SD pin. 

- The decoupling capacitor C3 (from 100 to 220 nF, ceramic with low ESR and low ESL), in parallel with each Cboot, filters the high frequency disturbance. Both Cboot and C3 (if present) should be placed as close as possible to the U, V, W and Vboot pins. Bootstrap negative electrodes should be connected to U, V, W terminals directly and separated from the main output wires. 

- To prevent the overvoltage on Vcc pin, a Zener diode (Dz1) can be used. Similarly on the Vboot pin, a Zener diode (Dz2) can be placed in parallel with each Cboot. 

- The use of the decoupling capacitor C4 (100 to 220 nF, with low ESR and low ESL) in parallel with the electrolytic capacitor Cvdc avoids surge destruction. Both capacitors C4 and Cvdc should be placed as close as possible to the IPM (C4 has priority over Cvdc). 

- By integrating an application specific type HVIC inside the module, direct coupling to the MCU terminals without an optocoupler is possible. 

- Low inductance shunt resistors should be used for phase leg current sensing. 

- In order to avoid malfunctions, the wiring among N pins, the shunt resistor and PWR_GND should be as short as possible. 

   - These guidelines ensure the specifications of the device for the application design. For further details, please refer to the relevant application note AN4043. 

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**Application circuit** example 

**Table 15: Recommended operating conditions** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VPN|Supply voltage|Applied among P-Nu, Nv,<br>Nw||300|500|V|
|VCC|Control supplyvoltage|Applied to VCC-GND|13.5|15|18|V|
|VBS|High-side bias voltage|Applied to VBOOTi-OUTi<br>for i = U, V, W|13||18|V|
|tdead|Blanking time to prevent arm-<br>short|For each input signal|1.5|||µs|
|fPWM|PWM input signal|-40 °C < Tc< 100 °C<br>-40 °C < Tj< 125 °C|||25|kHz|
|TC|Case operation temperature||||100|°C|



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**Package information** 

## **6 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

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**Package information** 

## **6.1 NDIP-26L type C package information** 

**Figure 12: NDIP-26L type C package outline** 

**==> picture [463 x 522] intentionally omitted <==**

**----- Start of picture text -----**<br>
8278949_7<br>**----- End of picture text -----**<br>


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**Package information** 

**Table 16: NDIP-26L type C mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|||4.40|
|A1|0.80|1.00|1.20|
|A2|3.00|3.10|3.20|
|A3|1.70|1.80|1.90|
|A4|5.70|5.90|6.10|
|b|0.53||0.72|
|b1|0.52|0.60|0.68|
|b2|0.83||1.02|
|b3|0.82|0.90|0.98|
|c|0.46||0.59|
|c1|0.45|0.50|0.55|
|D|29.05|29.15|29.25|
|D1|0.50|0.77|1.00|
|D2|0.35|0.53|0.70|
|D3|||29.55|
|E|12.35|12.45|12.55|
|e|1.70|1.80|1.90|
|e1|2.40|2.50|2.60|
|eB1|16.10|16.40|16.70|
|eB2|21.18|21.48|21.78|
|L|1.24|1.39|1.54|



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**Package information** 

## **6.2 NDIP-26L packing information** 

**Figure 13: NDIP-26L tube (dimensions are in mm)** 

**==> picture [433 x 30] intentionally omitted <==**

**----- Start of picture text -----**<br>
Notes:<br>1- Material: extrused/transparent PVC 0.80°°' mm thickness 10E6~10E11/SQ PVC<br>2- General tolerance unless otherwise specified: +0.25 mm<br>8313150_3<br>**----- End of picture text -----**<br>


**Table 17: Shipping details** 

|**Parameter**|**Value**|
|---|---|
|Basequantity|17pieces|
|Bulkquantity|476pieces|



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**Revision history** 

## **7 Revision history** 

**Table 18: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|19-Dec-2013|1|Initial release.|
|23-Apr-2014|2|Updated_Figure 1: Internal schematic diagram_and_Section 3:_<br>_Electrical characteristics._<br>Minor text changes.|
|05-May-2014|3|Updated features in coverpage.|
|04-Nov-2014|4|Updated:<br>–_Figure 1: Internal schematic diagram_<br>–_Table 10: Logic inputs (VCC = 15 V unless otherwise specified)_<br>–_Table 12: Sense comparator characteristics (VCC = 15 V unless_<br>_otherwise specified)_<br>–_Section 3.1.1: NTC thermistor_<br>–_Section 4: Smart shutdown function description_<br>–_Figure 10: Smart shutdown timing waveforms_<br>_– Figure 11: Typical application circuit_<br>–_Section 5.1: Recommendations_<br>– minor text changes|
|07-Nov-2014|5|Minor text and formattingedits throughout document.|
|08-Jun-2015|6|Updated_Section 6: Package information._<br>Minor text changes.|
|16-Mar-2017|7|Updated_Section 6.1: "NDIP-26L type C package information"_and<br>_Section 6.2: "NDIP-26L packing information"_<br>Minor text changes|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2017 STMicroelectronics – All rights reserved 

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