# IGBT Module, IPM Three Phase Inverter, 15 A, 600 V, 44 W, 125 °C, SDIP

![Product image](https://novapart.co/image/farnell:1889349/)

**URL**: https://novapart.co/products/STGIPL14K60/igbt-module-ipm-three-phase-inverter-15-a-600-v-44
**SKU**: STGIPL14K60
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || IGBTs || IGBT Modules
**Price**: €7.3500
**Stock**: 10+

## Description

Transistor Polarity:N Channel; DC Collector Current:15A; Collector Emitter Saturation Voltage Vce(on):600V; Power Dissipation Pd:44W; Collector Emitter Voltage V(br)ceo:-; Transistor

## Specifications

| Parameter | Value |
|---|---|
| No. Of Pins | 38Pins |
| Product Range | - |
| Igbt Technology | - |
| Igbt Termination | Solder |
| Power Dissipation | 44W |
| Igbt Configuration | IPM Three Phase Inverter |
| Transistor Mounting | Through Hole |
| Transistor Polarity | N Channel |
| Dc Collector Current | 15A |
| Power Dissipation Pd | 44W |
| Transistor Case Style | SDIP |
| Operating Temperature Max | 125°C |
| Junction Temperature Tj Max | 125°C |
| Continuous Collector Current | 15A |
| Collector Emitter Voltage Max | - |
| Collector Emitter Voltage V(Br)Ceo | - |
| Collector Emitter Saturation Voltage | 600V |
| Collector Emitter Saturation Voltage Vce(On) | 600V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:1889349/)

## **STGIPL14K60, STGIPL14K60-S** 

## SLLIMM™ (small low-loss intelligent molded module) IPM, 3-phase inverter, 15 A, 600 V short-circuit rugged IGBT 

**Datasheet** - **production data** 

- 5 kΩ NTC for temperature control 

- UL Recognized: UL1557 file E81734 

## **Applications** 

- 3-phase inverters for motor drives 

- Home appliances, such as washing machines, refrigerators, air conditioners and sewing machines 

## **Description** 

**==> picture [83 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
SDIP-38L option A<br>**----- End of picture text -----**<br>


**==> picture [35 x 5] intentionally omitted <==**

**----- Start of picture text -----**<br>
AM01193v1<br>**----- End of picture text -----**<br>


## **Features** 

- IPM 15 A, 600 V 3-phase IGBT inverter bridge including control ICs for gate driving and freewheeling diodes 

- Short-circuit rugged IGBTs 

These intelligent power modules provides a compact, high performance AC motor drive in a simple, rugged design. Combining ST proprietary control ICs with the most advanced short-circuitrugged IGBT system technology, this device is ideal for 3-phase inverters in applications such as home appliances and air conditioners. SLLIMM™ is a trademark of STMicroelectronics. 

- VCE(sat) negative temperature coefficient 

- 3.3 V, 5 V, 15 V CMOS/TTL inputs comparators with hysteresis and pull down/pull up resistors 

- Undervoltage lockout 

- Internal bootstrap diode 

- Interlocking function 

- Smart shut down function 

- Comparators for fault protection against overtemperature and overcurrent 

- Op amps for advanced current sensing 

- DBC substrate leading to low thermal resistance 

- Isolation rating of 2500 Vrms/min 

**Table 1. Device summary** 

|**Order code**|**Marking**|**Package**|**Packaging**|
|---|---|---|---|
|STGIPL14K60|GIPL14K60|SDIP-38L option A|Tube|
|STGIPL14K60-S|GIPL14K60-S|SDIP-38L option B|Tube|



_www.st.com_ 

October 2013 

1/26 

DocID15589 Rev 11 

This is information on a product in full production. 

**STGIPL14K60, STGIPL14K60-S** 

**Contents** 

|**Contents**|**Contents**|
|---|---|
|**1**|**Internal block diagram and pin configuration  . . . . . . . . . . . . . . . . . . . . 3**|
|**2**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6**|
||2.1<br>Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
||2.2<br>Thermal data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
|**3**|**Electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8**|
||3.1<br>Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10|
||3.1.1<br>NTC thermistor  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12|
||3.2<br>Waveforms definitions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|**4**|**Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15**|
|**5**|**Applications information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17**|
||5.1<br>Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|**6**|**Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19**|
|**7**|**Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23**|
|**8**|**Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25**|



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**Internal block diagram and pin configuration** 

## **1 Internal block diagram and pin configuration** 

## **Figure 1. Internal block diagram** 

**==> picture [453 x 508] intentionally omitted <==**

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**Internal block diagram and pin configuration** 

**Table 2. Pin description** 

|||**Table 2. Pin description**|
|---|---|---|
|**Pin**|**Symbol**|**Description**|
|1|OUTU|High side reference output for U phase|
|2|Vboot U|Bootstrap voltage for U phase|
|3|LIN<br>U|Low side logic input for U phase|
|4|HINU|High side logic input for U phase|
|5|OP-U|Op amp inverting input for U phase|
|6|OPOUT U|Op amp output for U phase|
|7|OP+U|Op amp non inverting input for U phase|
|8|CINU|Comparator input for U phase|
|9|OUTV|High side reference output for V phase|
|10|Vboot V|Bootstrap voltage for V phase|
|11|LIN<br>V|Low side logic input for V phase|
|12|HINV|High side logic input for V phase|
|13|OP-V|Op amp inverting input for V phase|
|14|OPOUT V|Op amp output for V phase|
|15|OP+V|Op amp non inverting input for V phase|
|16|CINV|Comparator input for V phase|
|17|OUTW|High side reference output for W phase|
|18|Vboot W|Bootstrap voltage for W phase|
|19|LIN<br>W|Low side logic input for W phase|
|20|HINW|High side logic input for W phase|
|21|OP-W|Op amp inverting input for W phase|
|22|OPOUT W|Op amp output for W phase|
|23|OP+W|Op amp non inverting input for W phase|
|24|CINW|Comparator input for W phase|
|25|VCC|Low voltage power supply|
|26|SD<br>/ OD|Shut down logic input (active low) / open drain (comparator output)|
|27|GND|Ground|
|28|T2|NTC thermistor terminal 2|
|29|T1|NTC thermistor terminal 1|
|30|NW|Negative DC input for W phase|
|31|W|W phase output|
|32|P|Positive DC input|
|33|NV|Negative DC input for V phase|
|34|V|V phase output|



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**Internal block diagram and pin configuration** 

**Table 2. Pin description (continued)** 

|**Pin**|**Symbol**|**Description**|
|---|---|---|
|35|P|Positive DC input|
|36|NU|Negative DC input for U phase|
|37|U|U phase output|
|38|P|Positive DC input|



## **Figure 2. Pin layout (bottom view)** 

**==> picture [286 x 179] intentionally omitted <==**

**----- Start of picture text -----**<br>
Marking area<br>**----- End of picture text -----**<br>


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**Electrical ratings** 

## **2 Electrical ratings** 

## **2.1 Absolute maximum ratings** 

**Table 3. Inverter part** 

||**Table 3. Inverterpart**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|VPN|Supply voltage applied between P-NU, NV, NW|450|V|
|VPN(surge)|Supply voltage (surge) applied between P-NU,<br>NV, NW|500|V|
|VCES|Each IGBT collector emitter voltage (VIN<br>(1)= 0)|600|V|
|± IC<br>(2)|Each IGBT continuous collector current<br>at TC= 25°C|15|A|
|± ICP<br>(3)|Each IGBT pulsed collector current|30|A|
|PTOT|Each IGBT total dissipation at TC= 25°C|44|W|
|tscw|Short circuit withstand time, VCE= 0.5 V(BR)CES<br>Tj= 125 °C, VCC= Vboot= 15 V, VIN (1)= 0÷5 V|5|µs|
|<br>||||



1. Applied between HINi, LINi and GND for i = U, V, W 

2. Calculated according to the iterative formula: 

T – T IC(TC) = -------------------------------------------------------------------------------------------------------Rthj – c × VCE(satj(max)(max) )([T] Cj(max),[I] C([T] C)) 

3. Pulse width limited by max junction temperature 

**Table 4. Control part** 

||**Table 4. Controlpart**||||
|---|---|---|---|---|
|**Symbol**|**Parameter**|**Min.**|**Max.**|**Unit**|
|VOUT|Output voltage applied between<br>OUTU, OUTV, OUTW- GND|Vboot- 21|Vboot+ 0.3|V|
|VCC|Low voltage power supply|- 0.3|21|V|
|VCIN|Comparator input voltage|- 0.3|VCC+ 0.3|V|
|Vop+|OPAMP non-inverting input|- 0.3|VCC+ 0.3|V|
|Vop-|OPAMP inverting input|- 0.3|VCC+ 0.3|V|
|Vboot|Bootstrap voltage|- 0.3|620|V|
|VIN|Logic input voltage applied between HIN, LIN<br>and<br>GND|- 0.3|15|V|
|~~V~~SD<br>/OD|Open drain voltage|- 0.3|15|V|
|dVOUT/dt|Allowed output slew rate||50|V/ns|



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**Electrical ratings** 

**Table 5. Total system** 

||**Table 5. Total system**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|VISO|Isolation withstand voltage applied between each<br>pin and heatsink plate (AC voltage, t = 60sec.)|2500|V|
|Tj|Power chips operating junction temperature|-40 to 150|°C|
|TC|Module case operation temperature|-40 to 125|°C|



## **2.2 Thermal data** 

## **Table 6. Thermal data** 

||**Table 6. Thermal data**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|Rth(j-c)|Thermal resistance junction-case single IGBT|2.8|°C/W|
||Thermal resistance junction-case single diode|5|°C/W|



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**Electrical characteristics** 

## **3 Electrical characteristics** 

Tj = 25 °C unless otherwise specified. 

**Table 7. Inverter part** 

|||**Table 7. Inverterpart**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test condition**|**Value**|||**Unit**|
||||**Min.**|**Typ.**|**Max.**||
|VCE(sat)|Collector-emitter<br>saturation voltage|VCC= VBoot= 15 V, VIN<br>(1)= 0 ÷ 5 V,<br>IC= 7 A|-|2.1|2.5|V|
|||VCC= VBoot= 15 V, VIN<br>(1)= 0 ÷ 5 V,<br>IC= 7 A, Tj= 125 °C|-|1.8|||
|ICES|Collector-cut off current<br>(VIN<br>(1)=0 “logic state”)|VCE= 550 V<br>VCC= Vboot= 15 V|-||150|µA|
|VF|Diode forward voltage|VIN<br>(1)= 0 “logic state”, IC= 7 A|-||2.1|V|
|**Inductive load switching time and**||**energy**|||||
|ton|Turn-on time|VDD= 300 V,<br>VCC= Vboot= 15 V,<br>VIN<br>(1)= 0 ÷ 5 V,<br>IC= 7 A<br>(see_Figure 3_)|-|270||ns|
|tc(on)|Crossover time (on)||-|130|||
|toff|Turn-off time||-|320|||
|tc(off)|Crossover time (off)||-|110|||
|trr|Reverse recovery time||-|130|||
|Eon|Turn-on switching losses||-|150||µJ|
|Eoff|Turn-off switching losses||-|90|||



1. Applied between HINi LINi and GND for i = U, V, W (LIN inputs are active-low). 

_Note:_ 

_ton and toff include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are the switching time of IGBT itself under the internally given gate driving condition._ 

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**Electrical characteristics** 

## **Figure 3. Switching time test circuit** 

**==> picture [405 x 234] intentionally omitted <==**

**----- Start of picture text -----**<br>
INPUT<br>BOOT<br>/Lin VBOOT>VCC BUS<br>+5V<br>/SD HVG<br>RSD<br>Hin L<br>OUT<br>VCC<br>Vcc<br>IC<br>DT LVG<br>VCE<br>GND CP+<br>0<br>1<br>AM06019v2<br>**----- End of picture text -----**<br>


**Figure 4. Switching time definition** 

**==> picture [397 x 283] intentionally omitted <==**

**----- Start of picture text -----**<br>
100% IC   100% IC<br>t rr<br>VCE IC IC VCE<br>VIN VIN<br>t ON t OFF<br>t C(ON) t C(OFF)<br>VIN(ON) 10% IC 90% IC 10% VCE VIN(OFF) 10% VCE 10% IC<br>(a) turn-on (b) turn-off AM09223V1<br>**----- End of picture text -----**<br>


Figure 4 "Switching time definition" refers to HIN inputs (active high). For LIN inputs (active low), VIN polarity must be inverted for turn-on and turn-off. 

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**Electrical characteristics** 

## **3.1 Control part** 

**Table 8. Low voltage power supply (VCC = 15 V unless otherwise specified)** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Vcc_hys|VccUV hysteresis||1.2|1.5|1.8|V|
|Vcc_thON|VccUV turn ON threshold||11.5|12|12.5|V|
|Vcc_thOFF|VccUV turn OFF threshold||10|10.5|11|V|
|Iqccu|Undervoltage quiescent<br>supply current|VCC= 10 V<br>SD/OD<br>= 5 V; LIN<br>= 5 V;<br>HIN= 0, CIN= 0|||450|µA|
|Iqcc|Quiescent current|VCC= 15 V<br>SD/OD<br>= 5 V; LIN<br>= 5 V<br>HIN= 0, CIN= 0|||3.5|mA|
|Vref|Internal comparator (CIN)<br>reference voltage||0.5|0.54|0.58|V|



**Table 9. Bootstrapped voltage (VCC = 15 V unless otherwise specified)** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VBS_hys|VBS UV hysteresis||1.2|1.5|1.8|V|
|VBS_thON|VBS UV turn ON threshold||11.1|11.5|12.1|V|
|VBS_thOFF|VBS UV turn OFF threshold||9.8|10|10.6|V|
|IQBSU|Undervoltage VBSquiescent<br>current|VBS< 9 V<br>SD/OD<br>= 5 V; LIN<br>and<br>HIN = 5 V; CIN= 0||70|110|µA|
|IQBS|VBSquiescent current|VBS= 15 V<br>SD/OD<br>= 5 V; LIN<br>and<br>HIN = 5 V; CIN= 0||200|300|µA|
|RDS(on)|Bootstrap driver on resistance|LVG ON||120||W|



**Table 10. Logic inputs (VCC = 15 V unless otherwise specified)** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Vil|Low logic level voltage||0.8||1.1|V|
|Vih|High logic level voltage||1.9||2.25|V|
|IHINh|HIN logic “1” input bias current|HIN = 15 V|110|175|260|µA|
|IHINl|HIN logic “0” input bias current|HIN = 0 V|||1|µA|
|ILINl|LIN<br>logic “1” input bias current|LIN<br>= 0 V|3|6|20|µA|
|ILINh|LIN<br>logic “0” input bias current|LIN<br>= 15 V|||1|µA|
|ISDh|SD<br>logic “0” input bias current|SD<br>= 15 V|30|120|300|µA|



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**Electrical characteristics** 

**Table 10. Logic inputs (VCC = 15 V unless otherwise specified) (continued)** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISDl|SD<br>logic “1” input bias current|SD<br>= 0 V|||3|µA|
|Dt|Dead time|see_Figure 9_||600||ns|
|**Table 11. OPAMP characteristics(VCC = 15 V unless otherwise specified)**|||||||
|**Symbol**|**Parameter**|**Test condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|Vio|Input offset voltage|Vic= 0 V, Vo= 7.5 V|||6|mV|
|Iio|Input offset current|Vic= 0 V, Vo= 7.5 V||4|40|nA|
|Iib|Input bias current(1)|||100|200|nA|
|ςicm|Input common mode voltage<br>range||0|||V|
|ςOL|Low level output voltage|RL= 10 kΩto VCC||75|150|mV|
|ςOH|High level output voltage|RL= 10 kΩto GND|14|14.7||V|
|Io|Output short circuit current|Σουρχε,<br>ςιδ=+1; ςο= 0 ς|16|30||mA|
|||Sink,<br>ςιδ=-1; ςο= ςΧΧ|50|80||mA|
|SR|Slew rate|Vi= 1÷4 V; CL= 100 pF;<br>unity gain|2.5|3.8||V/μs|
|GBWP|Gain bandwidth product|Vo= 7.5 V|8|12||MHz|
|Avd|Large signal voltage gain|RL= 2 kΩ|70|85||dB|
|SVR|Supply voltage rejection ratio|vs. VCC|60|75||dB|
|CMRR|Common mode rejection ratio||55|70||dB|



1. The direction of input current is out of the IC. 

**Table 12. Sense comparator characteristics (VCC = 15 V unless otherwise specified)** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Iib(i)|Input bias current|VCIN(i)=1 V, i= U, V o W|-||3|µA|
|Vol|Open-drain low-level output<br>voltage|Iod= 3 mA|-||0.5|V|
|td_comp|Comparator delay|SD<br>/OD pulled to 5 V through<br>100 kΩresistor|-|90|130|ns|
|SR|Slew rate|CL= 180 pF; Rpu= 5 kΩ|-|60||V/µsec|
|tsd|Shut down to high / low side<br>driver propagation delay|VOUT = 0, Vboot = VCC,<br>VIN = 0 to 3.3 V|50|125|200|ns|
|tisd|Comparator triggering to high /<br>low side driver turn-off<br>propagation delay|Measured applying a voltage<br>step from 0 V to 3.3 V to pin<br>CINi|50|200|250||



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**Electrical characteristics** 

**Table 13. Truth table** 

||**Table 13. Truth table**|**Table 13. Truth table**|**Table 13. Truth table**|||
|---|---|---|---|---|---|
|**Condition**|**Logic input (VI)**|||**Output**||
||**SD**<br>**/OD**|**LIN**|**HIN**|**LVG**|**HVG**|
|Shutdown enable<br>half-bridge 3-state|L|X|X|L|L|
|Interlocking<br>half-bridge 3-state|H|L|H|L|L|
|0 ‘’logic state”<br>half-bridge 3-state|H|H|L|L|L|
|1 “logic state”<br>low side direct driving|H|L|L|H|L|
|1 “logic state”<br>high side direct driving|H|H|H|L|H|



_Note: X: don’t care_ 

_._ 

**Figure 5. Maximum IC(RMS) current vs. switching Figure 6. Maximum** I **C(RMS) current vs. fsine(1) frequency[(1)]** 

**==> picture [462 x 176] intentionally omitted <==**

**----- Start of picture text -----**<br>
20 AM07839v1 12 AM07840v1<br>18 11<br>V PN = 300 V, Modulation index = 0.8,<br>PF = 0.6, Tj = 150 °C, TC = 10 °C<br>16 10<br>TC = 80 °C<br>14 9<br>TC = 100 °C<br>12 8 f SW = 12 kHz<br>10 VP PN F = 0.6, T= 300 V, Modulation index j = 150 °C, fSINE = 60 Hz= 0.8,  7 ffSWSW = 16 kHz= 20 kHz<br>8 6<br>4 6 8 10 12 14 16 18 20 1 10 100<br>fSW [kHz] fSINE [Hz]<br> [A]<br> [A]<br>Ic(RMS)<br>Ic(RMS)<br>**----- End of picture text -----**<br>


1. Simulated curves refer to typical IGBT parameters and maximum Rthj-c. 

## **3.1.1 NTC thermistor** 

**Table 14. NTC thermistor** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**<br>|**Max.**|**Unit.**|
|---|---|---|---|---|---|---|
|R25|Resistance|T = 25°C||5||kΩ|
|R125|Resistance|T = 125°C||300||Ω|
|B|B-constant|T = 25°C to 85°C||3340||K|
|T|Operating temperature||-40||125|°C|



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**Electrical characteristics** 

## **Equation 1: resistance variation vs. temperature** 

**==> picture [125 x 31] intentionally omitted <==**

**----- Start of picture text -----**<br>
B  [1] – --------1 - <br> T [---] 298 <br>R(T) = R25 ⋅ e<br>**----- End of picture text -----**<br>


## Where T are temperatures in Kelvin. 

## **Figure 7. NTC resistance vs. temperature** 

## **Figure 8. NTC resistance vs. temperature zoom** 

**==> picture [462 x 176] intentionally omitted <==**

**----- Start of picture text -----**<br>
NTC (kΩ) AM03795v2 NTC (kΩ) AM03795_2v3<br>1.8<br>100<br>1.6<br>Max<br>80 1.4<br>Min<br>1.2<br>60 1.0<br>0.8 Typ<br>40<br>0.6<br>20 0.4<br>0.2<br>0 0<br>-40 -20 0 20 40 60 80 100 T (°C) 50 60 70 80 90 100 110 120 T (°C)<br>**----- End of picture text -----**<br>


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**Electrical characteristics** 

## **3.2 Waveforms definitions** 

## **Figure 9. Dead time and interlocking waveforms definitions** 

**==> picture [397 x 361] intentionally omitted <==**

**----- Start of picture text -----**<br>
LIN<br>CONTROL SIGNAL EDGES HIN<br>OVERLAPPED:<br>INTERLOCKING + DEAD TIME LVG<br>DTLH DTHL<br>HVG<br>gate driver outputs OFF gate driver outputs OFF<br>(HALF-BRIDGE TRI-STATE) (HALF-BRIDGE TRI-STATE)<br>LIN<br>CONTROL SIGNALS EDGES HIN<br>SYNCHRONOUS (*):<br>DEAD TIME<br>LVG<br>DTLH DTHL<br>HVG<br>gate driver outputs OFF gate driver outputs OFF<br>(HALF-BRIDGE TRI-STATE) (HALF-BRIDGE TRI-STATE)<br>LIN<br>CONTROL SIGNALS EDGES HIN<br>NOT OVERLAPPED,<br>BUT INSIDE THE DEAD TIME: LVG<br>DEAD TIME<br>DTLH DTHL<br>HVG<br>gate driver outputs OFF gate driver outputs OFF<br>(HALF-BRIDGE TRI-STATE) (HALF-BRIDGE TRI-STATE)<br>LIN<br>CONTROL SIGNALS EDGES<br>NOT OVERLAPPED,  HIN<br>OUTSIDE THE DEAD TIME:<br>DIRECT DRIVING<br>LVG<br>DTLH DTHL<br>HVG<br>gate driver outputs OFF gate driver outputs OFF<br>(HALF-BRIDGE TRI-STATE) (HALF-BRIDGE TRI-STATE)<br>INTERLOCKING INTERLOCKING<br>**----- End of picture text -----**<br>


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**Smart shutdown function** 

## **4 Smart shutdown function** 

The devices integrate a comparator for fault sensing purposes. The comparator has an internal voltage reference VREF connected to the inverting input, while the non-inverting input, available on pin (CIN), can be connected to an external shunt resistor in order to implement a simple over-current protection function. When the comparator triggers, the device is set in shutdown state and both its outputs are set to low-level leading the halfbridge in tri-state. In the common overcurrent protection architectures the comparator output is usually connected to the shutdown input through a RC network, in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. Our smart shutdown architecture allows to immediately turn-off the output gate driver in case of overcurrent, the fault signal has a preferential path which directly switches off the outputs. The time delay between the fault and the outputs turn-off is no more dependent on the RC values of the external network connected to the shutdown pin. At the same time the DMOS connected to the open-drain output (pin SD/OD) is turned on by the internal logic which holds it on until the shutdown voltage is lower than the logic input lower threshold (Vil). Finally, the smart shutdown function provides the possibility to increase the real disable time without increasing the constant time of the external RC network. 

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**Smart shutdown function** 

**==> picture [405 x 487] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 10. Smart shutdown timing waveforms<br>comp Vref<br>CP+<br>HIN/LIN<br>PROTECTION<br>HVG/LVG<br>SD/OD<br>open drain gate<br>(internal)<br>disable time<br>Fast shut down:<br>the driver outputs are set in SD state immediately after the comparator<br>triggering even if the SD signal  has not yet reach the lower input threshold<br>An approximation of the disable time is given by:<br>SHUT DOWN CIRCUIT<br>VBIAS<br>RSD  where:<br>SD/OD<br>FROM/TO SMART<br>CONTROLLER SD<br>CSD RON_OD LOGIC<br>RPD_SD<br>AM12947v1<br>**----- End of picture text -----**<br>


Please refer to _Table 12_ for internal propagation delay time details. 

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**Applications information** 

## **5 Applications information** 

## **Figure 11. Typical application circuit** 

**==> picture [419 x 568] intentionally omitted <==**

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**Applications information** 

## **5.1 Recommendations** 

- Input signal HIN is active high logic. A 85kΩ (typ.) pull down resistor is built-in for each high side input. If an external RC filter is used, for noise immunity, pay attention to the variation of the input signal level. 

- Input signal LIN is active low logic. A 720 kΩ (typ.) pull-up resistor, connected to an internal 5 V regulator through a diode, is built-in for each low side input. 

- To prevent the input signals oscillation, the wiring of each input should be as short as possible. 

- By integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler is possible. 

- Each capacitor should be located as nearby the pins of IPM as possible. 

- Low inductance shunt resistors should be used for phase leg current sensing. 

- Electrolytic bus capacitors should be mounted as close to the module bus terminals as possible. Additional high frequency ceramic capacitor mounted close to the module pins will further improve performance. 

- The SD/OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see _Section 4: Smart shutdown function_ for detailed info). 

**Table 15. Recommended operating conditions** 

|**Symbol**|**Parameter**|**Conditions**|**Value**|**Value**|**Value**|**Unit**|
|---|---|---|---|---|---|---|
||||**Min.**|**Typ.**|**Max.**||
|VPN|Supply Voltage|Applied between P-Nu, Nv, Nw||300|400|V|
|VCC|Control supply voltage|Applied between VCC-GND|13.5|15|18|V|
|VBS|High side bias voltage|Applied between VBOOTi-OUTifor<br>i = U, V, W|13||18|V|
|tdead|Blanking time to<br>prevent Arm-short|For each input signal|1|||µs|
|fPWM|PWM input signal|-40°C < Tc< 100°C<br>-40°C < Tj< 125°C|||20|kHz|
|TC|Case operation<br>temperature||||100|°C|



_Note: For further details refer to AN3338._ 

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**Package information** 

## **6 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _www.st.com_ . ECOPACK[®] is an ST trademark. 

Please refer to dedicated technical note TN0107 for mounting instructions. 

**Table 16. SDIP-38L option A mechanical data** 

|**Dimensions**|**mm.**|**mm.**|**mm.**|
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|49.10|49.60|50.10|
|A1|1.10|1.30|1.50|
|A2|1.40|1.60|1.80|
|A3|44.10|44.60|45.10|
|B|24.00|24.50|25.00|
|B1|11.25|11.85|12.45|
|B2|27.10|27.60|28.10|
|B3|28.60|29.10|29.60|
|C|5.00|5.40|6.00|
|C1|6.50|7.00|7.50|
|C2|10.35|10.85|11.35|
|e|1.10|1.30|1.50|
|e1|3.20|3.40|3.60|
|e2|5.80|6.00|6.20|
|e3|4.60|4.80|5.00|
|e4|5.60|5.80|6.00|
|e5|6.30|6.50|6.70|
|e6|4.50|4.70|4.90|
|D||38.10||
|D1||5.75||
|E||11.80||
|E1||2.15||
|F|0.85|1.00|1.15|
|F1|0.35|0.50|0.65|
|R|1.55|1.75|1.95|
|T|0.45|0.55|0.65|
|V|0°||6°|



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**Package information** 

**==> picture [240 x 11] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 12. SDIP-38L option A drawing dimensions<br>**----- End of picture text -----**<br>


**==> picture [390 x 402] intentionally omitted <==**

**----- Start of picture text -----**<br>
8142868_G<br>**----- End of picture text -----**<br>


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**Package information** 

**Table 17. SDIP-38L option B mechanical data** 

|**Dimensions**|**mm.**|**mm.**|**mm.**|
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|49.10|49.60|50.10|
|A1|1.10|1.30|1.50|
|A2|1.40|1.60|1.80|
|A3|44.10|44.60|45.10|
|B|24.00|24.50|25.00|
|B1|11.25|11.85|12.45|
|B2|27.10|27.60|28.10|
|B3|29.65|30.15|30.65|
|C|5.00|5.40|6.00|
|C2|8.15|8.35|8.55|
|e|1.10|1.30|1.50|
|e1|3.20|3.40|3.60|
|e2|5.80|6.00|6.20|
|e3|4.60|4.80|5.00|
|e4|5.60|5.80|6.00|
|e5|6.30|6.50|6.70|
|e6|4.50|4.70|4.90|
|D||38.10||
|D1||5.75||
|E||11.80||
|E1||2.15||
|F|0.85|1.00|1.15|
|F1|0.35|0.50|0.65|
|R|1.55|1.75|1.95|
|T|0.45|0.55|0.65|
|V|0°||6°|



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**Package information** 

**==> picture [240 x 11] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 13. SDIP-38L option B drawing dimensions<br>**----- End of picture text -----**<br>


**==> picture [393 x 510] intentionally omitted <==**

**----- Start of picture text -----**<br>
8434993_A<br>**----- End of picture text -----**<br>


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**Packaging mechanical data** 

## **7 Packaging mechanical data** 

**==> picture [314 x 11] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 14. SDIP-38L shipping tube type A (dimensions are in mm.)<br>**----- End of picture text -----**<br>


**==> picture [353 x 541] intentionally omitted <==**

**----- Start of picture text -----**<br>
8147106_E<br>**----- End of picture text -----**<br>


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**Packaging mechanical data** 

**Figure 15. SDIP-38L shipping tube type B (dimensions are in mm.)** 

**==> picture [297 x 541] intentionally omitted <==**

**----- Start of picture text -----**<br>
8147106_E<br>**----- End of picture text -----**<br>


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**Revision history** 

## **8 Revision history** 

**Table 18. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|16-Apr-2009|1|Initial release|
|29-Mar-2010|2|Inserted_Figure 5_,_Figure 6_and_Section 4: Smart shutdown function_.<br>Updated_Section 3.1: Control part_and package mechanical data,<br>_Section 6_.<br>Minor text changes to improve readability.|
|14-Jun-2010|3|Document status promoted from preliminary data to datasheet.<br>Updated_Table 7: Inverter part_,_Figure 5: Maximum IC(RMS) current_<br>_vs. switching frequency_and_Figure 6: Maximum IC(RMS) current_<br>_vs. fsine(1)_.|
|21-Sep-2010|4|Updated:_Table 3_,_5_,_8_,_9_,_10_and_12_.<br>Modified:_Figure 5_and_Figure 6_.|
|09-Mar-2011|5|Updated title with SLLIMM™ in cover page, added SDIP-38L tube<br>dimensions_Figure 14_.|
|04-Nov-2011|6|Updated title with SLLIMM™ (small low-loss intelligent molded<br>module) IPM, 3-phase inverter - 15 A, 600 V short-circuit rugged<br>IGBT in cover page and SDIP-38L mechanical data_Table 16 on_<br>_page 19_,_Figure 12_.|
|28-Aug-2012|7|Modified: Min. and Max. value_Table 4 on page 6_.<br>Updated:_Figure 14_.<br>Added:_Figure 15_.|
|04-Mar-2013|8|Added:_Figure 7_and_Figure 8_|
|13-Mar-2013|9|Modified:_Figure 8 on page 13_|
|17-Jun-2013|10|Updated:_Figure 9: Dead time and interlocking waveforms_<br>_definitions_.|
|17-Oct-2013|11|Added device STGIPL14K60-S and modified_Table 1: Device_<br>_summary_accordingly.<br>Updated_Section 6: Package information_and_Section 7: Packaging_<br>_mechanical data_.<br>Minor text changes.|



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## Links

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