# Power MOSFET, N Channel, 1.05 kV, 4 A, 1.4 ohm, TO-220FP, Through Hole

![Product image](https://novapart.co/image/farnell:2807268/)

**URL**: https://novapart.co/products/STF7N105K5/power-mosfet-n-channel-105-kv-4-a-14-ohm-to-220fp
**SKU**: STF7N105K5
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.1700
**Stock**: 200+
**Lead Time**: 113 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:4A; Drain Source Voltage Vds:1.05kV; On Resistance Rds(on):1.4ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4V; Po

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | MDmesh K5 |
| Qualification | - |
| Power Dissipation | 25W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-220FP |
| Drain Source Voltage Vds | 1.05kV |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 4A |
| Drain Source On State Resistance | 1.4ohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2807268/)

## **STF7N105K5** 

## N-channel 1050 V, 1.4 Ω typ., 4 A MDmesh™ K5 Power MOSFET in TO-220FP package 

Datasheet - production data 

## **Features** 

|**Order code**|**V DS**|**RDS(on) max.**|**ID**|**PTOT**|
|---|---|---|---|---|
|STF7N105K5|1050 V|2.0 Ω|4 A|25 W|



- Industry’s lowest RDS(on) x area 

- Industry’s best FoM (figure of merit) 

- Ultra-low gate charge 

- 100% avalanche tested 

- Zener-protected 

**==> picture [42 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
TO-220FP<br>**----- End of picture text -----**<br>


**Figure 1: Internal schematic diagram** 

## **Applications** 

- Switching applications 

D(2) **Description** This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic G(1) reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. S(3) AM15572v1_no_tab 

**Table 1: Device summary** 

|**Order code**|**Marking**|**Package**|**Packaging**|
|---|---|---|---|
|STF7N105K5|7N105K5|TO-220FP|Tube|



_www.st.com_ 

June 2016 

DocID026184 Rev 2 

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This is information on a product in full production. 

|**Contents**<br>**STF7N105K5**|**Contents**<br>**STF7N105K5**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 9**|
|**4**|**Package information ..................................................................... 10**|
||4.1<br>TO-220FP package information ...................................................... 11|
|**5**|**Revision history ............................................................................ 13**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VGS|Gate- source voltage|± 30|V|
|ID|Drain current (continuous) at TC= 25 °C|4_(1)_|A|
|ID|Drain current (continuous) at TC= 100 °C|3_(1)_|A|
|IDM_(2)_|Drain current (pulsed)|16|A|
|PTOT|Total dissipation at TC= 25 °C|25|W|
|IAR|Max. current duringrepetitive or singlepulse avalanche|1.5|A|
|EAS|Single pulse avalanche energy<br>(starting TJ= 25 °C, ID=IAR, VDD= 50 V)|132|mJ|
|VISO|Insulation withstand voltage (RMS) from all three leads to external<br>heat sink (t = 1 s; TC= 25 °C)|2500|V|
|dv/dt_(3)_|Peak diode recoveryvoltage slope|4.5|V/ns|
|dv/dt_(4)_|MOSFET dv/dt ruggedness|50|V/ns|
|Tj|Operating junction temperature range|- 55 to 150|°C|
|Tstg|Storage temperature range|||



## **Notes:** 

- (1)Limited by package. 

(2)Pulse width limited by safe operating area. 

(3)ISD ≤ 4 A, di/dt ≤ 100 A/µs, VDS(peak) ≤ V(BR)DSS ; VSD ≤ 840 V 

- (4)VDS ≤ 840 V 

**Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case max|5|°C/W|
|Rthj-amb|Thermal resistancejunction-amb max|62.5|°C/W|



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**Electrical characteristics** 

## **2 Electrical characteristics** 

(TCASE = 25 °C unless otherwise specified). 

**Table 4: On/off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|VGS= 0 V, ID= 1 mA|1050|||V|
|IDSS|Zero gate voltage drain<br>current|VGS= 0 V, VDS= 1050 V|||1|µA|
|||VGS= 0 V, VDS= 1050 V,<br>TC=125 °C_(1)_|||50|µA|
|IGSS|Gate bodyleakage current|VDS= 0, VGS= ± 20 V|||±10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 100µA|3|4|5|V|
|RDS(on)|Static drain-source on-<br>resistance|VGS= 10 V, ID= 2 A||1.4|2|Ω|



## **Notes:** 

(1)Defined by design, not subject to production test. 

**Table 5: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS=100 V, f=1 MHz, VGS=0 V|-|380|-|pF|
|Coss|Output capacitance||-|40|-|pF|
|Crss|Reverse transfer<br>capacitance||-|0.65|-|pF|
|Co(tr)_(1)_|Equivalent capacitance<br>time related|VGS= 0 V, VDS= 0 to 840 V|-|47|-|pF|
|Co(er)_(2)_|Equivalent capacitance<br>energy related||-|17|-|pF|
|RG|Intrinsicgate resistance|f = 1MHz open drain|-|7|-|Ω|
|Qg|Totalgate charge|VDD= 840 V, ID= 4 A<br>VGS=10 V<br>_Figure 16: "Test circuit for gate_<br>_charge behavior"_|-|11|-|nC|
|Qgs|Gate-source charge||-|2.8|-|nC|
|Qgd|Gate-drain charge||-|5.6|-|nC|



## **Notes:** 

(1)Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 

(2)Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 

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**Electrical characteristics** 

**Table 6: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDD= 525 V, ID= 2 A, RG=4.7 Ω,<br>VGS=10 V<br>(see_Figure 15: "Test circuit for_<br>_resistive load switching times"_and<br>_Figure 20: "Switching time_<br>_waveform"_)|-|17.5|-|ns|
|tr|Rise time||-|7|-|ns|
|td(off)|Turn-off delaytime||-|43|-|ns|
|tf|Fall time||-|25|-|ns|



## **Table 7: Source drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||4|A|
|ISDM|Source-drain current<br>(pulsed)||||16|A|
|VSD_(1)_|Forward on voltage|ISD= 4 A, VGS=0|-||1.6|V|
|trr|Reverse recoverytime|ISD= 4 A, VDD= 60 V<br>di/dt = 100 A/µs,<br>_Figure 17: "Test circuit for_<br>_inductive load switching and_<br>_diode recovery times"_|-|370||ns|
|Qrr|Reverse recoverycharge||-|3||µC|
|IRRM|Reverse recovery current||-|16.5||A|
|trr|Reverse recoverytime|ISD= 4 A,VDD= 60 V<br>di/dt=100 A/µs, Tj=150 °C<br>_Figure 17: "Test circuit for_<br>_inductive load switching and_<br>_diode recovery times"_|-|600||ns|
|Qrr|Reverse recoverycharge||-|4.4||µC|
|IRRM|Reverse recovery current||-|14.5||A|



## **Notes:** 

(1)Pulsed: pulse duration = 300µs, duty cycle 1.5% 

**Table 8: Gate-source Zener diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)GSO|Gate-source breakdown voltage|IGS= ± 1mA, ID=0|30|-|-|V|



The built-in back-to-back Zener diodes have been specifically designed to enhance the ESD capability of the device. The Zener voltage is appropriate for efficient and costeffective intervention to protect the device integrity. These integrated Zener diodes thus eliminate the need for external components. 

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**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2: Safe operating area** 

**==> picture [128 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 3: Thermal impedance<br>**----- End of picture text -----**<br>


**Figure 4: Output characteristics** 

**Figure 5: Transfer characteristics** 

**Figure 6: Gate charge vs gate-source voltage** 

**==> picture [186 x 28] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 7: Static drain-source on-resistance<br>GIPG310320141422SA<br>RDsion, Ω<br>**----- End of picture text -----**<br>


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**Electrical characteristics** 

**Figure 8: Capacitance variations** 

**Figure 10: Normalized gate threshold voltage vs temperature** 

**Figure 9: Source-drain diode forward characteristics** 

**Figure 11: Normalized on-resistance vs temperature** 

**==> picture [147 x 23] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.2 D= µ<br>re<br>**----- End of picture text -----**<br>


**Figure 12: Normalized V(BR)DSS vs temperature** GIPG210320141421S A 

**Figure 13: Maximum avalanche energy vs starting Tj** 

**==> picture [179 x 152] intentionally omitted <==**

**----- Start of picture text -----**<br>
EAS<br>(mJ) ID=1.5 A<br>120<br>VDD=50 V<br>100<br>80<br>60<br>40<br>20<br>0<br>0 20 40 60 80 100 120 140 TJ(°C)<br>**----- End of picture text -----**<br>


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**Electrical characteristics** 

**Figure 14: Output capacitance stored energy** 

**==> picture [9 x 6] intentionally omitted <==**

**----- Start of picture text -----**<br>
( µ J)<br>**----- End of picture text -----**<br>


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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 580] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 15: Test circuit for resistive load  Figure 16: Test circuit for gate charge<br>switching times  behavior<br>Figure 17: Test circuit for inductive load<br>switching and diode recovery times  Figure 18: Unclamped inductive load test<br>circuit<br>Figure 20: Switching time waveform<br>Figure 19: Unclamped inductive waveform<br>**----- End of picture text -----**<br>


**==> picture [24 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
9/14<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

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**Package information** 

## **4.1 TO-220FP package information** 

**Figure 21: TO-220FP package outline** 

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**Package information** 

**Table 9: TO-220FP package mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|4.4||4.6|
|B|2.5||2.7|
|D|2.5||2.75|
|E|0.45||0.7|
|F|0.75||1|
|F1|1.15||1.70|
|F2|1.15||1.70|
|G|4.95||5.2|
|G1|2.4||2.7|
|H|10||10.4|
|L2||16||
|L3|28.6||30.6|
|L4|9.8||10.6|
|L5|2.9||3.6|
|L6|15.9||16.4|
|L7|9||9.3|
|Dia|3||3.2|



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**Revision history** 

## **5 Revision history** 

**Table 10: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|07-Apr-2014|1|First release.|
|07-Jun-2016|2|Updated_Figure 6: "Gate charge vs gate-source voltage"_and_Table 5:_<br>_"Dynamic"_.<br>Minor text changes.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2016 STMicroelectronics – All rights reserved 

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