# Power MOSFET, N Channel, 800 V, 2 A, 2.75 ohm, TO-220FP, Through Hole

![Product image](https://novapart.co/image/farnell:3367039/)

**URL**: https://novapart.co/products/STF3LN80K5/power-mosfet-n-channel-800-v-2-a-275-ohm-to-220fp
**SKU**: STF3LN80K5
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.5400
**Stock**: 200+
**Lead Time**: 113 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | MDmesh K5 |
| Qualification | - |
| Power Dissipation | 20W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-220FP |
| Drain Source Voltage Vds | 800V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 2A |
| Drain Source On State Resistance | 2.75ohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3367039/)

## **STF3LN80K5** 

N-channel 800 V, 2.75 Ω typ., 2 A MDmesh™ K5 Power MOSFET in a TO-220FP package 

Datasheet - production data 

## **Features** 

|**Order code**|**VDS**|**RDS(on) max**|**ID**|
|---|---|---|---|
|STF3LN80K5|800 V|3.25 Ω|2 A|



- Industry’s lowest RDS(on) x area 

- Industry’s best FoM (figure of merit) 

- Ultra-low gate charge 

- 100% avalanche tested 

- Zener-protected 

**==> picture [42 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
TO-220FP<br>**----- End of picture text -----**<br>


**Figure 1: Internal schematic diagram** 

## **Applications** 

- Switching applications 

D(2) **Description** This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic G(1) reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. S(3) AM15572v1_no_tab **Table 1: Device summary Order code Marking Package Packing** STF3LN80K5 3LN80K5 TO-220FP Tube 

This is information on a product in full production. 

_www.st.com_ 

July 2016 

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|**Contents**<br>**STF3LN80K5**|**Contents**<br>**STF3LN80K5**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>2.1 Electrical characteristics (curves) ................................................ 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>TO-220FP package information ...................................................... 10|
|**5**|**Revision history ............................................................................ 12**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VGS|Gate-source voltage|± 30|V|
|ID_(1)_|Drain current (continuous) at TC= 25 °C|2|A|
|ID_(1)_|Drain current (continuous) at TC= 100 °C|1.25|A|
|ID_(2)_|Drain current (pulsed)|8|A|
|PTOT|Total dissipation at TC= 25 °C|20|W|
|VISO|Insulation withstand voltage (RMS) from all three leads to external<br>heat sink (t = 1 s; TC= 25 °C)|2500|V|
|dv/dt_(3)_|Peak diode recovery voltage slope|4.5|V/ns|
|dv/dt_(4)_|MOSFET dv/dt ruggedness|50||
|Tstg|Storage temperature range|- 55 to 150|°C|
|Tj|Operating junction temperature range|||



## **Notes:** 

- (1)Limited by maximum junction temperature. 

- (2)Pulse width limited by safe operating area. 

(3)ISD ≤ 2 A, di/dt ≤ 100 A/µs; VDSpeak < V(BR)DSS, VDD = 640 V 

- (4)VDS ≤ 640 V. 

**Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case|6.25|°C/W|
|Rthj-amb|Thermal resistancejunction-ambient|62.5|°C/W|



## **Table 4: Avalanche characteristics** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|IAR|Avalanche current, repetitive or not repetitive (pulse width limited byTjmax)|0.7|A|
|EAS|Singlepulse avalanche energy(startingTj= 25°C, ID= IAR; VDD= 50 V)|155|mJ|



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**Electrical characteristics** 

## **2 Electrical characteristics** 

(TC = 25 °C unless otherwise specified) 

**Table 5: On /off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|ID= 1 mA, VGS= 0 V|800|||V|
|IDSS|Zero gate voltage<br>drain current|VDS= 800 V, VGS= 0 V|||1|µA|
|||VDS= 800 V, VGS= 0 V,<br>TC= 125 °C_(1)_|||50|µA|
|IGSS|Gate body leakage<br>current|VGS= ± 20 V, VGS= 0 V|||±10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 100µA|3|4|5|V|
|RDS(on)|Static drain-source<br>on-resistance|VGS= 10 V, ID= 1 A||2.75|3.25|Ω|



## **Notes:** 

(1)Defined by design, not subject to production test. 

**Table 6: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 100 V, f = 1 MHz,<br>VGS= 0 V|-|102|-|pF|
|Coss|Output capacitance||-|11|-|pF|
|Crss|Reverse transfer<br>capacitance||-|0.1|-|pF|
|Cotr_(1)_|Equivalent capacitance<br>time related|VDS= 0 to 640 V, VGS= 0 V|-|20|-|pF|
|Coer_(2)_|Equivalent capacitance<br>energy related||-|7|-|pF|
|RG|Intrinsicgate resistance|f = 1 MHz, ID= 0 A|-|12|-|Ω|
|Qg|Totalgate charge|VDD= 640 V, ID= 2 A,<br>VGS= 10 V ( see_Figure 15:_<br>_"Test circuit for gate charge_<br>_behavior"_)|-|2.63|-|nC|
|Qgs|Gate-source charge||-|0.91|-|nC|
|Qgd|Gate-drain charge||-|1.53|-|nC|



## **Notes:** 

(1)Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 

(2)Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 

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**Electrical characteristics** 

**Table 7: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDD= 400 V, ID= 1 A, RG= 4.7 Ω,<br>VGS= 10 V ( see_Figure 14: "Test_<br>_circuit for resistive load switching_<br>_times"_and_Figure 19: "Switching_<br>_time waveform"_)|-|6.2|-|ns|
|tr|Rise time||-|7|-|ns|
|td(off)|Turn-off delaytime||-|30|-|ns|
|tf|Fall time||-|26|-|ns|



**Table 8: Source drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||2|A|
|ISDM_(1)_|Source-drain current<br>(pulsed)||-||8|A|
|VSD_(2)_|Forward on voltage|ISD= 2 A, VGS= 0 V|-||1.5|V|
|trr|Reverse recoverytime|ISD= 2 A, di/dt = 100 A/µs,<br>VDD= 60 V ( see_Figure 16: "Test_<br>_circuit for inductive load switching_<br>_and diode recovery times"_)|-|210||ns|
|Qrr|Reverse recovery<br>charge||-|0.8||µC|
|IRRM|Reverse recovery<br>current||-|7.6||A|
|trr|Reverse recoverytime|ISD= 2 A, di/dt = 100 A/µs,<br>VDD= 60 V, Tj= 150 °C, (see<br>_Figure 16: "Test circuit for_<br>_inductive load switching and diode_<br>_recovery times"_)|-|345||ns|
|Qrr|Reverse recovery<br>charge||-|1.2||µC|
|IRRM|Reverse recovery<br>current||-|7.2||A|



## **Notes:** 

(1)Pulse width limited by safe operating area. 

(2)Pulsed: pulse duration = 300 µs, duty cycle 1.5%. 

**Table 9: Gate-source Zener diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)GSO|Gate-source breakdown voltage|IGS= ± 1 mA, ID= 0 A|30|-|-|V|



The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. 

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**Electrical characteristics** 

## **2.1 2.1 Electrical characteristics (curves)** 

**==> picture [386 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 2: Safe operating area  Figure 3: Thermal impedance<br>**----- End of picture text -----**<br>


**Figure 4: Output characteristics Figure 5: Transfer characteristics** 

**==> picture [158 x 142] intentionally omitted <==**

**==> picture [159 x 142] intentionally omitted <==**

**Figure 6: Gate charge vs gate-source voltage** 

**==> picture [161 x 143] intentionally omitted <==**

**Figure 7: Static drain-source on-resistance** 

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**Electrical characteristics** 

**==> picture [389 x 179] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 9: Source-drain diode forward<br>Figure 8: Capacitance variations<br>characteristics<br>**----- End of picture text -----**<br>


**==> picture [409 x 179] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 10: Normalized gate threshold voltage  Figure 11: Normalized on-resistance vs<br>vs temperature  temperature<br>**----- End of picture text -----**<br>


**==> picture [395 x 190] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 13: Maximum avalanche energy vs<br>Figure 12: Normalized V(BR)DSS vs<br>starting TJ<br>temperature<br>**----- End of picture text -----**<br>


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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 580] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 14: Test circuit for resistive load<br>Figure 15: Test circuit for gate charge<br>switching times<br>behavior<br>VDD<br>RL<br>VGS IG= CONST 100 Ω D.U.T.<br>pulse width + 2.7 kΩ<br>2200 VG<br>μF<br>47 kΩ<br>1 kΩ<br>AM01469v10<br>Figure 16: Test circuit for inductive load<br>switching and diode recovery times  Figure 17: Unclamped inductive load test<br>circuit<br>Figure 19: Switching time waveform<br>Figure 18: Unclamped inductive waveform<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

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**Package information** 

## **4.1 TO-220FP package information** 

**Figure 20: TO-220FP package outline** 

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**Package information** 

**Table 10: TO-220FP package mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|4.4||4.6|
|B|2.5||2.7|
|D|2.5||2.75|
|E|0.45||0.7|
|F|0.75||1|
|F1|1.15||1.70|
|F2|1.15||1.70|
|G|4.95||5.2|
|G1|2.4||2.7|
|H|10||10.4|
|L2||16||
|L3|28.6||30.6|
|L4|9.8||10.6|
|L5|2.9||3.6|
|L6|15.9||16.4|
|L7|9||9.3|
|Dia|3||3.2|



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**Revision history** 

## **5 Revision history** 

**Table 11: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|13-May-2015|1|Initial release|
|01-Jul-2016|2|Updated title and features in cover page.<br>Updated_Table 2: "Absolute maximum ratings"_and_Section 2:_<br>_"Electrical characteristics"_.<br>Added_Section 2.1: "2.1 Electrical characteristics (curves)"_.<br>Minor text changes.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2016 STMicroelectronics – All rights reserved 

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