# Power MOSFET, N Channel, 600 V, 18 A, 0.175 ohm, TO-220FP, Through Hole

![Product image](https://novapart.co/image/farnell:2807256/)

**URL**: https://novapart.co/products/STF25N60M2-EP/power-mosfet-n-channel-600-v-18-a-0175-ohm-to
**SKU**: STF25N60M2-EP
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.2500
**Stock**: 200+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:18A; Drain Source Voltage Vds:600V; On Resistance Rds(on):0.175ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:3V; Po

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | MDmesh M2 |
| Qualification | - |
| Power Dissipation | 30W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-220FP |
| Drain Source Voltage Vds | 600V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 18A |
| Drain Source On State Resistance | 0.175ohm |
| Gate Source Threshold Voltage Max | 3V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2807256/)

## **STF25N60M2-EP** 

N-channel 600 V, 0.175 Ω typ., 18 A MDmesh™ M2 EP Power MOSFET in a TO-220FP package 

Datasheet - production data 

## **Features** 

**Order code VTDSJmax @ Rmax. DS(on) ID** STF25N60M2-EP 650 V 0.188 Ω 18 A ~~a~~ 

- Extremely low gate charge 

- Excellent output capacitance (COSS) profile 

- Very low turn-off switching losses 

- 100% avalanche tested 

- Zener-protected 

## **TO-220FP** 

**Figure 1: Internal schematic diagram** 

**==> picture [87 x 163] intentionally omitted <==**

**----- Start of picture text -----**<br>
D(2)<br>G(1)<br>S(3)<br>**----- End of picture text -----**<br>


AM15572v1_no_tab 

## **Applications** 

- Switching applications 

- Tailored for Very High Frequency Converters (f > 150 kHz) 

## **Description** 

This device is an N-channel Power MOSFET developed using MDmesh™ M2 EP enhanced performance technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance, optimized switching characteristics with very low turn-off switching losses, rendering it suitable for the most demanding very high frequency converters. 

**Table 1: Device summary Order code Marking Package Packaging** STF25N60M2-EP 25N60M2EP TO-220FP Tube ~~a~~ 

This is information on a product in full production. 

_www.st.com_ 

August 2016 

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|**Contents**<br>**STF25N60M2-EP**|**Contents**<br>**STF25N60M2-EP**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 9**|
|**4**|**Package mechanical data ............................................................. 10**|
||4.1<br>TO-220FP package information ...................................................... 11|
|**5**|**Revision history ............................................................................ 13**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VGS|Gate-source voltage|±25|V|
|VGS|Transientgate-source voltage (tp≤ 10 ns)|±35|V|
|ID|Drain current (continuous) at TC= 25 °C|18_(1)_|A|
|ID|Drain current (continuous) at TC= 100 °C|11.3_(1)_|A|
|IDM_(2)_|Drain current (pulsed)|72_(1)_|A|
|PTOT|Total dissipation at TC= 25 °C|30|W|
|dv/dt_(3)_|Peak diode recoveryvoltage slope|15|V/ns|
|dv/dt_(4)_|MOSFET dv/dt ruggedness|50|V/ns|
|VISO|Insulation withstand voltage (RMS) from all three leads to external<br>heat sink (t = 1 s, TC= 25 °C)|2500|V|
|Tstg|Storage temperature range|- 55 to 150|°C|
|Tj|Operating junction temperature|||



## **Notes:** 

(1)Limited Limited by maximum junction temperature. 

(2)Pulse width limited by safe operating area. 

(3)ISD ≤ 18 A, di/dt ≤ 400 A/µs; VDS peak < V(BR)DSS, VDD = 400 V. 

(4)VDS ≤ 480 V 

**Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case max|4.2|°C/W|
|Rthj-amb|Thermal resistance junction-ambient max|62.5|°C/W|



**Table 4: Avalanche characteristics** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|IAR|Avalanche current, repetetive or not repetetive<br>(pulse width limited by Tjmax)|3.5|A|
|EAS|Single pulse avalanche energy (starting Tj= 25 °C, ID= IAR;<br>VDD= 50 V)|200|mJ|



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**Electrical characteristics** 

## **2 Electrical characteristics** 

TC = 25 °C unless otherwise specified 

**Table 5: On/off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|VGS= 0 V, ID= 1 mA|600|||V|
|IDSS|Zero gate voltage drain<br>current|VGS= 0 V, VDS= 600 V|||1|µA|
|||VGS= 0 V, VDS= 600 V,<br>TC= 125 °C_(1)_|||100|µA|
|IGSS|Gate-body leakage<br>current|VDS= 0 V, VGS= ±25 V|||±10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250µA|2|3|4|V|
|RDS(on)|Static drain-source<br>on-resistance|VGS= 10 V, ID= 9 A||0.175|0.188|Ω|



## **Notes:** 

(1)Defined by design, not subject to production test. 

**Table 6: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 100 V, f = 1 MHz,<br>VGS= 0 V|-|1090|-|pF|
|Coss|Output capacitance||-|56|-|pF|
|Crss|Reverse transfer<br>capacitance||-|1.6|-|pF|
|Coss eq._(1)_|Equivalent output<br>capacitance|VDS= 0 to 480 V, VGS= 0 V|-|255|-|pF|
|RG|Intrinsicgate resistance|f = 1 MHz, ID= 0 A|-|7|-|Ω|
|Qg|Totalgate charge|VDD= 480 V, ID= 18 A,<br>VGS= 10 V<br>(see_Figure 16: "Test circuit for_<br>_gate charge behavior"_)|-|29|-|nC|
|Qgs|Gate-source charge||-|6|-|nC|
|Qgd|Gate-drain charge||-|12|-|nC|



## **Notes:** 

(1)Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 

**Table 7: Switching Energy** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|E(off)|Turn-off energy<br>(from 90% VGSto 0% ID)|VDD= 400 V, ID= 2 A<br>RG= 4.7 Ω, VGS= 10 V|-|7|-|µJ|
|||VDD= 400 V, ID= 4 A<br>RG= 4.7 Ω, VGS= 10 V|-|8|-|µJ|



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**Electrical characteristics** 

**Table 8: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on<br>delaytime|VDD= 300 V, ID= 9 A RG= 4.7 Ω, VGS= 10 V<br>(see_Figure 15: "Test circuit for resistive load_<br>_switching times"_and_Figure 20: "Switching_<br>_time waveform"_)|-|15|-|ns|
|tr|Rise time||-|10|-|ns|
|td(off)|Turn-off-<br>delaytime||-|61|-|ns|
|tf|Fall time||-|16|-|ns|



**Table 9: Source drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain<br>current||-||18|A|
|ISDM_(1)_|Source-drain<br>current (pulsed)||-||72|A|
|VSD_(2)_|Forward on voltage|VGS= 0 V, ISD= 18 A|-||1.6|V|
|trr|Reverse recovery<br>time|ISD= 18 A, di/dt = 100 A/µs,<br>VDD= 100 V<br>(see_Figure 17: "Test circuit for_<br>_inductive load switching and diode_<br>_recovery times"_)|-|360||ns|
|Qrr|Reverse recovery<br>charge||-|5||µC|
|IRRM|Reverse recovery<br>current||-|28||A|
|trr|Reverse recovery<br>time|ISD= 18 A, di/dt = 100 A/µs,<br>VDD= 100 V, Tj= 150 °C<br>(see_Figure 17: "Test circuit for_<br>_inductive load switching and diode_<br>_recovery times"_)|-|445||ns|
|Qrr|Reverse recovery<br>charge||-|6.5||µC|
|IRRM|Reverse recovery<br>current||-|29||A|



## **Notes:** 

(1)Pulse width is limited by safe operating area 

(2)Pulsed: pulse duration = 300 µs, duty cycle 1.5% 

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**Electrical characteristics** 

## **2.2 Electrical characteristics (curves)** 

**==> picture [158 x 154] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 2: Safe operating area<br>ID (A) GIPG021220141118ALS<br>10µs<br>10<br>100µs<br>1ms<br>10ms<br>1<br>0.1 TTSingle pulsejC=150°C=25°C<br>0.1 1 10 100 VDS(V)<br>DS(on)<br>Operation in this area<br>is limited by max R<br>**----- End of picture text -----**<br>


**==> picture [129 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 3: Thermal impedance<br>**----- End of picture text -----**<br>


**==> picture [144 x 142] intentionally omitted <==**

**==> picture [390 x 166] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 4: Output characteristics  Figure 5: Transfer characteristics<br>ID(A) GIPG011220141438ALS ID(A) GIPG281120141611ALS<br>40 40 VDS = 16 V<br>35 V GS  = 6,7,8,9,10 V 35<br>30 30<br>25 V GS = 5 V 25<br>20 20<br>15 15<br>10 10<br>5 VGS = 4 V 5<br>0 0<br>0 4 8 12 16 VDS(V) 0 2 4 6 8 VGS(V)<br>**----- End of picture text -----**<br>


**Figure 6: Gate charge vs gate-source voltage** 

**==> picture [157 x 142] intentionally omitted <==**

**Figure 7: Static drain-source on-resistance** 

**==> picture [153 x 142] intentionally omitted <==**

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**Electrical characteristics** 

**Figure 8: Capacitance variations** 

**Figure 9: Output capacitance stored energy** 

**==> picture [159 x 145] intentionally omitted <==**

**----- Start of picture text -----**<br>
EOSS GIPG181120141603ALS<br>(μJ)<br>8<br>6<br>4<br>2<br>0<br>0 100 200 300 400 500 600 VDS(V)<br>**----- End of picture text -----**<br>


**==> picture [398 x 166] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 10: Turn-off switching loss vs drain  Figure 11: Normalized gate threshold voltage<br>current  vs temperature<br>EOSS GIPG261120141106ALS VGS(th) GIPG181120141615ALS<br>(μJ) (norm)<br>1.1<br>12<br>ID = 250 µA<br>1.0<br>10<br>0.9<br>8<br>0.8<br>6<br>0.7<br>4 0.6<br>0 1 2 3 4 5 6 ID(A) -75 -25 25 75 125 TJ(°C)<br>**----- End of picture text -----**<br>


**==> picture [171 x 166] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 12: Normalized on-resistance vs<br>temperature<br>R GIPG181120141628ALS<br>DS(on)<br>(norm)<br>2.2<br>1.8<br>VGS = 10 V<br>1.4<br>1.0<br>0.6<br>0.2<br>-75 -25 25 75 125 TJ(°C)<br>**----- End of picture text -----**<br>


**Figure 13: Source-drain diode forward characteristics** 

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**Electrical characteristics** 

**==> picture [198 x 182] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 14: Normalized V(BR)DSS vs temperature<br>V<br>(BR)DSS GIPG191120141457ALS<br>(norm)<br>1.08<br>1.04<br>1.00 ID = 1mA<br>0.96<br>0.92<br>0.88<br>-75 -25 25 75 125 TJ(°C)<br>**----- End of picture text -----**<br>


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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 375] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 15: Test circuit for resistive load  Figure 16: Test circuit for gate charge<br>switching times  behavior<br>Figure 17: Test circuit for inductive load  Figure 18: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>**----- End of picture text -----**<br>


**==> picture [403 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 19: Unclamped inductive waveform  Figure 20: Switching time waveform<br>**----- End of picture text -----**<br>


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**Package mechanical** data 

## **4 Package mechanical data** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

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**Package mechanical** data 

## **4.1 TO-220FP package information** 

**==> picture [161 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 21: TO-220FP package outline<br>**----- End of picture text -----**<br>


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**Package mechanical** data 

**Table 10: TO-220FP package mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|4.4||4.6|
|B|2.5||2.7|
|D|2.5||2.75|
|E|0.45||0.7|
|F|0.75||1|
|F1|1.15||1.70|
|F2|1.15||1.70|
|G|4.95||5.2|
|G1|2.4||2.7|
|H|10||10.4|
|L2||16||
|L3|28.6||30.6|
|L4|9.8||10.6|
|L5|2.9||3.6|
|L6|15.9||16.4|
|L7|9||9.3|
|Dia|3||3.2|



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**Revision history** 

## **5 Revision history** 

**Table 11: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|02-Dec-2014|1|First release.|
|12-Jan-2015|2|Updated product status from “preliminary data” to “production data”.|
|14-Jan-2015|3|Correctedproduct status information on coverpage.|
|25-Aug-2016|4|Modified:_Table 2: "Absolute maximum ratings"_<br>Minor text changes|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2016 STMicroelectronics – All rights reserved 

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