# Power MOSFET, N Channel, 600 V, 18 A, 0.175 ohm, TO-220FP, Through Hole

![Product image](https://novapart.co/image/farnell:2807255/)

**URL**: https://novapart.co/products/STF24N60DM2/power-mosfet-n-channel-600-v-18-a-0175-ohm-to
**SKU**: STF24N60DM2
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.9480
**Stock**: 500+
**Lead Time**: 2 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:18A; Drain Source Voltage Vds:600V; On Resistance Rds(on):0.175ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4V; Po

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | MDmesh DM2 |
| Qualification | - |
| Power Dissipation | 30W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-220FP |
| Drain Source Voltage Vds | 600V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 18A |
| Drain Source On State Resistance | 0.175ohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2807255/)

## **STF24N60DM2** 

## N-channel 600 V, 0.175 Ω typ., 18 A MDmesh™ DM2 Power MOSFET in a TO-220FP package 

Datasheet - production data 

## **Features** 

|**Order code**|**VDS @ TJmax**|**RDS(on) max.**|**ID**|
|---|---|---|---|
|STF24N60DM2|650 V|0.200 Ω|18 A|



- Fast-recovery body diode 

- Extremely low gate charge and input capacitance 

- Low on-resistance 

- 100% avalanche tested 

**==> picture [42 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
TO-220FP<br>**----- End of picture text -----**<br>


- Extremely high dv/dt ruggedness 

- Zener-protected 

**Figure 1: Internal schematic diagram** 

## **Applications** 

- Switching applications 

## **Description** 

This high voltage N-channel Power MOSFET is part of the MDmesh™ DM2 fast recovery diode series. It offers very low recovery charge (Qrr) and time (trr) combined with low RDS(on), rendering it suitable for the most demanding high efficiency converters and ideal for bridge topologies and ZVS phase-shift converters. 

**Table 1: Device summary** 

|**Order code**|**Marking**|**Package**|**Packing**|
|---|---|---|---|
|STF24N60DM2|24N60DM2|TO-220FP|Tube|



This is information on a product in full production. 

_www.st.com_ 

September 2016 

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|**Contents**<br>**STF24N60DM2**|**Contents**<br>**STF24N60DM2**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>TO-220FP package information ...................................................... 10|
|**5**|**Revision history ............................................................................ 12**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VGS|Gate-source voltage|± 25|V|
|ID_(1)_|Drain current (continuous) at TC= 25 °C|18|A|
||Drain current (continuous) at TC= 100 °C|11||
|IDM_(2)(1)_|Drain current (pulsed)|72|A|
|PTOT|Total dissipation at TC= 25 °C|30|W|
|dv/dt_(3)_|Peak diode recoveryvoltage slope|40|V/ns|
|dv/dt_(4)_|MOSFET dv/dt ruggedness|50||
|VISO|Insulation withstand voltage (RMS) from all three leads to external<br>heat sink (t = 1 s; TC= 25 °C)|2500|V|
|Tstg|Storage temperature range|–55 to 150|°C|
|Tj|Max. operating junction temperature range|||



## **Notes:** 

- (1) Limited by package. 

(2) Pulse width is limited by safe operating area. 

(3) ISD ≤ 18 A, di/dt ≤ 400 A/µS, VDS(peak) < V(BR)DSS, VDD = 400 V. 

(4) VDS ≤ 480 V. 

## **Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case max.|4.2|°C/W|
|Rthj-amb|Thermal resistancejunction-ambient max.|62.5||



## **Table 4: Avalanche characteristics** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|IAR|Avalanche current, repetitive or not repetitive<br>(pulse width limited byTJmax)|3.5|A|
|EAS|Single pulse avalanche energy<br>(starting TJ=25 °C, ID= IAR; VDD= 50 V)|180|mJ|



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**Electrical characteristics** 

## **2 Electrical characteristics** 

(Tcase= 25 °C unless otherwise specified) 

**Table 5: On /off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|VGS= 0 V, ID= 1 mA|600|||V|
|IDSS|Zero gate voltage drain<br>current|VGS= 0 V, VDS= 600 V|||1.5|µA|
|||VGS= 0 V, VDS= 600 V,<br>TC= 125 °C_(1)_|||100|µA|
|IGSS|Gate-body leakage<br>current|VDS= 0 V, VGS= ±25 V|||±10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 µA|3|4|5|V|
|RDS(on)|Static drain-source on-<br>resistance|VGS= 10 V, ID= 9 A||0.175|0.200|Ω|



## **Notes:** 

(1)Defined by design, not subject to production test. 

**Table 6: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 100 V, f = 1 MHz,<br>VGS= 0 V|-|1055|-|pF|
|Coss|Output capacitance||-|56|-|pF|
|Crss|Reverse transfer<br>capacitance||-|2.4|-|pF|
|Coss eq._(1)_|Equivalent output<br>capacitance|VDS= 0 to 480 V, VGS= 0 V|-|259|-|pF|
|RG|Intrinsicgate resistance|f = 1 MHz, ID= 0 A|-|7|-|Ω|
|Qg|Totalgate charge|VDD= 480 V, ID= 18 A,<br>VGS= 10 V<br>(see_Figure 15: "Test circuit for_<br>_gate charge behavior"_)|-|29|-|nC|
|Qgs|Gate-source charge||-|6|-|nC|
|Qgd|Gate-drain charge||-|12|-|nC|



## **Notes:** 

(1)Coss eq. is defined as a constant equivalent capacitance giving the same charging time as COSS when VDS increases from 0 to 80% VDSS. 

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**Electrical characteristics** 

## **Table 7: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDD= 300 V, ID= 9 A<br>RG= 4.7 Ω, VGS= 10 V<br>(see_Figure 14: "Test circuit for_<br>_resistive load switching times"_<br>and_Figure 19: "Switching time_<br>_waveform"_)|-|15|-|ns|
|tr|Rise time||-|8.7|-|ns|
|td(off)|Turn-off-delaytime||-|60|-|ns|
|tf|Fall time||-|15|-|ns|



**Table 8: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||18|A|
|ISDM_(1)_|Source-drain current<br>(pulsed)||-||72|A|
|VSD_(2)_|Forward on voltage|VGS= 0 V, ISD= 18 A|-||1.6|V|
|trr|Reverse recoverytime|ISD= 18 A, di/dt = 100 A/µs,<br>VDD= 60 V (see_Figure 16: "Test_<br>_circuit for inductive load_<br>_switching and diode recovery_<br>_times"_)|-|155||ns|
|Qrr|Reverse recovery<br>charge||-|956||nC|
|IRRM|Reverse recovery<br>current||-|12.5||A|
|trr|Reverse recoverytime|ISD= 18 A, di/dt = 100 A/µs,<br>VDD= 60 V, Tj= 150 °C (see<br>_Figure 16: "Test circuit for_<br>_inductive load switching and_<br>_diode recovery times"_)|-|200||ns|
|Qrr|Reverse recovery<br>charge||-|1450||nC|
|IRRM|Reverse recovery<br>current||-|13||A|



## **Notes:** 

(1) Pulse width is limited by safe operating area. 

(2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. 

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## **Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2: Safe operating area** 

**==> picture [190 x 157] intentionally omitted <==**

**Figure 3: Thermal impedance** 

**==> picture [174 x 168] intentionally omitted <==**

**Figure 4: Output characteristics** 

**==> picture [163 x 164] intentionally omitted <==**

**Figure 5: Transfer characteristics** 

**==> picture [163 x 164] intentionally omitted <==**

**Figure 6: Gate charge vs gate-source voltage** 

**==> picture [177 x 158] intentionally omitted <==**

**Figure 7: Static drain-source on-resistance** 

**==> picture [175 x 165] intentionally omitted <==**

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**Electrical characteristics** 

**Figure 8: Capacitance variations** 

**==> picture [175 x 163] intentionally omitted <==**

**Figure 10: Normalized gate threshold voltage vs temperature** 

**==> picture [167 x 159] intentionally omitted <==**

**Figure 12: Source-drain diode forward characteristics** 

**==> picture [166 x 163] intentionally omitted <==**

**Figure 9: Output capacitance stored energy** 

**==> picture [176 x 163] intentionally omitted <==**

**Figure 11: Normalized on-resistance vs temperature** 

**==> picture [174 x 162] intentionally omitted <==**

**Figure 13: Normalized V(BR)DSS vs temperature** 

**==> picture [183 x 167] intentionally omitted <==**

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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 586] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 14: Test circuit for resistive load  Figure 15: Test circuit for gate charge<br>switching times  behavior<br>Figure 16: Test circuit for inductive load<br>Figure 17: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>Figure 19: Switching time waveform<br>Figure 18: Unclamped inductive waveform<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

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**STF24N60DM2** 

**Package information** 

## **4.1 TO-220FP package information** 

**Figure 20: TO-220FP package outline** 

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**Package information** 

**Table 9: TO-220FP package mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|4.4||4.6|
|B|2.5||2.7|
|D|2.5||2.75|
|E|0.45||0.7|
|F|0.75||1|
|F1|1.15||1.70|
|F2|1.15||1.70|
|G|4.95||5.2|
|G1|2.4||2.7|
|H|10||10.4|
|L2||16||
|L3|28.6||30.6|
|L4|9.8||10.6|
|L5|2.9||3.6|
|L6|15.9||16.4|
|L7|9||9.3|
|Dia|3||3.2|



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**Revision history** 

## **5 Revision history** 

**Table 10: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|12-Nov-2013|1|First release.|
|21-Jan-2014|2|– Modified: dv/dt value in Table 2<br>– Modified: IARvalue in Table 4<br>– Modified: IDSSand VGS(th)in Table 5<br>– Minor text changes|
|03-Mar-2014|3|– Modified: Figure 1<br>– Modified: PTOTvalue and note 1 in Table 2<br>– Modified: Rthj-casevalue in Table 3<br>– Modified: IARvalue in Table 4<br>– Minor text changes|
|05-Mar-2015|4|– Document status promoted from preliminary to production data.<br>– Updated title, features and description in cover page.|
|20-Sep-2016|5|Updated_Figure 2: "Safe operating area"_.<br>Minor text changes|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2016 STMicroelectronics – All rights reserved 

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