# Power MOSFET, N Channel, 500 V, 8.5 A, 0.4 ohm, TO-220FP, Through Hole

![Product image](https://novapart.co/image/farnell:2098199/)

**URL**: https://novapart.co/products/STF11NM50N/power-mosfet-n-channel-500-v-85-a-04-ohm-to-220fp
**SKU**: STF11NM50N
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.1000
**Stock**: 25+
**Lead Time**: 113 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:8.5A; Drain Source Voltage Vds:500V; On Resistance Rds(on):0.4ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:3V; Powe

## Specifications

| Parameter | Value |
|---|---|
| Msl | - |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 25W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-220FP |
| Drain Source Voltage Vds | 500V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 8.5A |
| Drain Source On State Resistance | 0.4ohm |
| Gate Source Threshold Voltage Max | 3V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2098199/)

## **STF11NM50N** 

## N-channel 500 V, 0.40 Ω typ., 8.5 A MDmesh™ II Power MOSFET in a TO-220FP package 

Datasheet - production data 

## **Features** 

|**Order code**|**VDS@ TJ max**|**RDS(on)max**|**ID**|
|---|---|---|---|
|STF11NM50N|550 V|0.47 Ω|8.5 A|



- 100% avalanche tested 

- Low input capacitance and gate charge 

- Low gate input resistance 

## **Applications** 

**==> picture [42 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
TO-220FP<br>**----- End of picture text -----**<br>


- Switching applications 

**Figure 1: Internal schematic diagram** 

## **Description** 

This device is an N-channel Power MOSFET developed using the second generation of MDmesh™ technology. This revolutionary Power MOSFET associates a vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters. 

**Table 1: Device summary** 

|**Order code**|**Marking**|**Package**|**Packaging**|
|---|---|---|---|
|STF11NM50N|11NM50N|TO-220FP|Tube|



June 2016 

DocID028675 Rev 2 

1/13 

This is information on a product in full production. 

_www.st.com_ 

|**Contents**<br>**STF11NM50N **|**Contents**<br>**STF11NM50N **|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>TO-220FP package information ...................................................... 10|
|**5**|**Revision history ............................................................................ 12**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|500|V|
|VGS|Gate-source voltage|±25|V|
|ID_(1)_|Drain current (continuous) at TC= 25 °C|8.5|A|
|ID_(1)_|Drain current (continuous) at TC= 100 °C|6|A|
|IDM_(1)(2)_|Drain current (pulsed)|34|A|
|PTOT|Total dissipation at TC= 25 °C|25|W|
|dv/dt_(3)_|Peak diode recoveryvoltage slope|15|V/ns|
|VISO|Insulation withstand voltage (RMS) from all three leads to external<br>heat sink (t = 1 s; TC= 25 °C)|2500|V|
|Tstg|Storage temperature range|-55 to 150|°C|
|Tj|Operating junction temperature range|||



## **Notes:** 

- (1)Limited by maximum junction temperature 

(2)Pulse width limited by safe operating area. 

(3)ISD ≤ 8.5 A, di/dt ≤ 400 A/µs, VDS(peak) ≤ V(BR)DSS, VDD ≤ 80% V(BR)DSS 

## **Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case max|5|°C/W|
|Rthj-amb|Thermal resistancejunction-ambient max|62.5|°C/W|



## **Table 4: Avalanche characteristics** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|IAR|Avalanche current, repetitive or not-repetitive<br>(pulse width limited by Tj max)|3|A|
|EAS|Single pulse avalanche energy<br>(startingTJ=25 °C, ID=IAR, VDD=50 V)|150|mJ|



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**Electrical characteristics** 

## **2 Electrical characteristics** 

(TCASE = 25 °C unless otherwise specified) 

**Table 5: On/off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source<br>breakdown voltage|ID= 1 mA, VGS= 0 V|500|||V|
|IDSS|Zero gate voltage drain<br>current|VGS= 0 V, VDS= 500 V|||1|µA|
|||VGS= 0 V, VDS= 500 V,<br>TC= 125 °C_(1)_|||100||
|IGSS|Gate-bodyleakage current|VDS= 0 V, VGS= ±25 V|||±100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 µA|2|3|4|V|
|RDS(on)|Static drain-source on-<br>resistance|VGS= 10 V, ID= 4.5 A||0.40|0.47|Ω|



## **Notes:** 

- (1)Defined by design, not subject to production test. 

**Table 6: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 50 V, f = 1 MHz,<br>VGS= 0 V|-|547|-|pF|
|Coss|Output capacitance||-|42|-|pF|
|Crss|Reverse transfer capacitance||-|2|-|pF|
|Coss eq.<br>_(1)_|Equivalent output capacitance|VGS= 0 V, VDS= 0 to 400 V|-|210|-|pF|
|Qg|Totalgate charge|VDD= 400 V, ID= 8.5 A,<br>VGS= 10 V (see_Figure 14:_<br>_"Test circuit for gate charge_<br>_behavior"_|-|19|-|nC|
|Qgs|Gate-source charge||-|3.7|-|nC|
|Qgd|Gate-drain charge||-|10|-|nC|
|RG|Gate input resistance|f=1 MHz, ID=0 A|-|5.8|-|Ω|



## **Notes:** 

(1)Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDS 

**Table 7: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD= 250 V, ID= 4.25 A,<br>RG= 4.7 Ω, VGS= 10 V<br>(see_Figure 13: "Test circuit for_<br>_resistive load switching times"_<br>and_Figure 18: "Switching time_<br>_waveform"_)|-|8|-|ns|
|tr|Rise time||-|10|-|ns|
|td(off)|Turn-off delaytime||-|33|-|ns|
|tf|Fall time||-|10|-|ns|



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**Electrical characteristics** 

**Table 8: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD_(1)_<br>ISDM|Source-drain current<br>Source-drain current (pulsed)||-||8.5<br>34|A<br>A|
|VSD_(2)_|Forward on voltage|ISD= 8.5 A, VGS= 0 V|-||1.5|V|
|trr|Reverse recoverytime|ISD= 8.5 A, di/dt = 100 A/µs<br>VDD= 60 V (see_Figure 15:_<br>_"Test circuit for inductive_<br>_load switching and diode_<br>_recovery times"_)|-|230||ns|
|Qrr|Reverse recoverycharge||-|2.1||µC|
|IRRM|Reverse recovery current||-|18||A|
|trr|Reverse recoverytime|ISD= 8.5 A, di/dt = 100 A/µs<br>VDD= 60 V, Tj= 150 °C<br>(see_Figure 15: "Test circuit_<br>_for inductive load switching_<br>_and diode recovery times"_)|-|275||ns|
|Qrr|Reverse recoverycharge||-|2.5||µC|
|IRRM|Reverse recovery current||-|18||A|



## **Notes:** 

(1)Pulse width limited by safe operating area. 

(2)Pulsed: pulse duration = 300 µs, duty cycle 1.5% 

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## **Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2: Safe operating area** 

**==> picture [198 x 162] intentionally omitted <==**

**Figure 3: Thermal impedance** 

**==> picture [168 x 162] intentionally omitted <==**

**Figure 4: Output characteristics** 

**==> picture [180 x 159] intentionally omitted <==**

**Figure 5: Transfer characteristics** 

**==> picture [176 x 164] intentionally omitted <==**

**Figure 6: Gate charge vs gate-source voltage** 

**==> picture [188 x 164] intentionally omitted <==**

**Figure 7: Static drain-source on resistance** 

**==> picture [178 x 165] intentionally omitted <==**

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**Electrical characteristics** 

**Figure 8: Capacitance variations** 

**Figure 9: Output capacitance stored energy** 

**==> picture [187 x 164] intentionally omitted <==**

**Figure 10: Normalized gate threshold voltage vs Figure 11: Normalized on-resistance vs temperature temperature** 

**Figure 12: Normalized V(BR)DSS vs temperature** 

**==> picture [171 x 162] intentionally omitted <==**

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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 580] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 13: Test circuit for resistive load  Figure 14: Test circuit for gate charge<br>switching times  behavior<br>Figure 15: Test circuit for inductive load<br>switching and diode recovery times  Figure 16: Unclamped inductive load test<br>circuit<br>Figure 18: Switching time waveform<br>Figure 17: Unclamped inductive waveform<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

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**Package information** 

## **4.1 TO-220FP package information** 

**Figure 19: TO-220FP package outline** 

~~©~~ 10/13 DocID028675 Rev 2 

**STF11NM50N** 

**Package information** 

**Table 9: TO-220FP package mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|4.4||4.6|
|B|2.5||2.7|
|D|2.5||2.75|
|E|0.45||0.7|
|F|0.75||1|
|F1|1.15||1.70|
|F2|1.15||1.70|
|G|4.95||5.2|
|G1|2.4||2.7|
|H|10||10.4|
|L2||16||
|L3|28.6||30.6|
|L4|9.8||10.6|
|L5|2.9||3.6|
|L6|15.9||16.4|
|L7|9||9.3|
|Dia|3||3.2|



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**Revision history** 

## **5 Revision history** 

**Table 10: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|25-Nov-2015|1|First release. Part number previously included in datasheet<br>DocID17156.|
|09-Jun-2016|2|Updated IGSSunit from µA to nA in_Table 5: "On/off states"_.<br>Updated_Table 7: "Switching times"_modifying references in test<br>conditions.<br>Document reformatted with the current standard with minor text<br>changes to improve readability.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2016 STMicroelectronics – All rights reserved 

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