# Power MOSFET, N Channel, 600 V, 7.5 A, 0.55 ohm, TO-220FP, Through Hole

![Product image](https://novapart.co/image/farnell:2807243/)

**URL**: https://novapart.co/products/STF10N60M2/power-mosfet-n-channel-600-v-75-a-055-ohm-to-220fp
**SKU**: STF10N60M2
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.4680
**Stock**: 200+
**Lead Time**: 2 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:7.5A; Drain Source Voltage Vds:600V; On Resistance Rds(on):0.55ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:3V; P

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | MDmesh M2 |
| Qualification | - |
| Power Dissipation | 25W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-220FP |
| Drain Source Voltage Vds | 600V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 7.5A |
| Drain Source On State Resistance | 0.55ohm |
| Gate Source Threshold Voltage Max | 3V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2807243/)

## **STF10N60M2** 

## N-channel 600 V, 0.55 Ω typ., 7.5 A MDmesh™ M2 Power MOSFET in a TO-220FP package 

Datasheet - production data 

## **Features** 

|**Order code**|**VDS@TJmax.**|**RDS(on) max.**|**ID**|
|---|---|---|---|
|STF10N60M2|650 V|0.60 Ω|7.5 A|



- Extremely low gate charge 

- Excellent output capacitance (COSS) profile 

- 100% avalanche tested  Zener-protected 

**==> picture [42 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
TO-220FP<br>**----- End of picture text -----**<br>


## **Applications** 

- Switching applications 

**Figure 1: Internal schematic diagram** 

**==> picture [179 x 165] intentionally omitted <==**

**----- Start of picture text -----**<br>
D(2)<br>G(1)<br>S(3) AM15572v1_no_tab<br>**----- End of picture text -----**<br>


## **Description** 

This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. 

**Table 1: Device summary** 

|**Order code**|**Marking**|**Package**|**Packing**|
|---|---|---|---|
|STF10N60M2|10N60M2|TO-220FP|Tube|



This is information on a product in full production. 

_www.st.com_ 

March 2017 

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|**Contents**<br>**STF10N60M2**|**Contents**<br>**STF10N60M2**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.2<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>TO-220FP package information ...................................................... 10|
|**5**|**Revision history ............................................................................ 12**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VGS|Gate-source voltage|±25|V|
|ID_(1)_|Drain current (continuous) at Tcase= 25 °C|7.5|A|
||Drain current (continuous) at Tcase= 100 °C|4.9||
|IDM_(2)_|Drain current (pulsed)|30|A|
|PTOT|Total dissipation at Tcase= 25 °C|25|W|
|dv/dt_(3)_|Peak diode recoveryvoltage slope|15|V/ns|
|dv/dt_(4)_|MOSFET dv/dt ruggedness|50||
|VISO_(5)_|Insulation withstand voltage (RMS) from all three leads to<br>external heat sink|2500|V|
|Tstg|Storage temperature range|-55 to 150|°C|
|Tj|Operating junction temperature range|||



## **Notes:** 

- (1)Limited by package. 

- (2)Pulse limited by safe operating area. 

- (3) ISD ≤ 7.5 A, di/dt ≤ 400 A/μs; VDS peak < V(BR)DSS, VDD = 400 V 

- (4) VDS ≤ 480 V. 

- (5)t = 1 s; TC = 25 °C. 

||**Table 3: Thermal data**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|Rthj-case|Thermal resistancejunction-case|5|°C/W|
|Rthj-amb|Thermal resistance junction-ambient|62.5||



## **Table 4: Avalanche characteristics** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|IAR_(1)_|Avalanche current, repetitive or not repetitive|1.5|A|
|EAS_(2)_|Singlepulse avalanche energy|110|mJ|



## **Notes:** 

- (1) Pulse width limited by Tjmax. 

- (2) Starting Tj = 25 °C, ID = IAR, VDD = 50 V. 

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**Electrical characteristics** 

## **2 Electrical characteristics** 

(Tcase = 25 °C unless otherwise specified) 

**Table 5: Static** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|VGS= 0 V, ID= 1 mA|600|||V|
|IDSS|Zero gate voltage drain<br>current|VGS= 0 V, VDS= 600 V|||1|µA|
|||VGS= 0 V, VDS= 600 V,<br>Tcase= 125 °C_(1)_|||100||
|IGSS|Gate-bodyleakage current|VDS= 0 V, VGS= ±25 V|||±10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250µA|2|3|4|V|
|RDS(on)|Static drain-source on-<br>resistance|VGS= 10 V, ID= 3 A||0.55|0.60|Ω|



## **Notes:** 

(1)Defined by design, not subject to production test. 

**Table 6: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 100 V, f = 1 MHz,<br>VGS= 0 V|-|400|-|pF|
|Coss|Output capacitance||-|22|-||
|Crss|Reverse transfer<br>capacitance||-|0.84|-||
|Coss<br>eq._(1)_|Equivalent output<br>capacitance|VDS= 0 to 480 V, VGS= 0 V|-|83|-|pF|
|RG|Intrinsicgate resistance|f = 1 MHz, ID= 0 A|-|6.4|-|Ω|
|Qg|Totalgate charge|VDD= 480 V, ID= 7.5 A,<br>VGS= 0 to 10 V (see_Figure 15:_<br>_"Test circuit for gate charge_<br>_behavior"_)|-|13.5|-|nC|
|Qgs|Gate-source charge||-|2.1|-||
|Qgd|Gate-drain charge||-|7.2|-||



## **Notes:** 

(1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 

**Table 7: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDD= 300 V, ID= 3.75 A<br>RG= 4.7 Ω, VGS= 10 V (see<br>_Figure 14: "Test circuit for_<br>_resistive load switching times"_<br>and_Figure 19: "Switching time_<br>_waveform"_)|-|8.8|-|ns|
|tr|Rise time||-|8|-||
|td(off)|Turn-off delaytime||-|32.5|-||
|tf|Fall time||-|13.2|-||



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**Electrical characteristics** 

**Table 8: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD_(1)_|Source-drain current||-||7.5|A|
|ISDM_(2)_|Source-drain current<br>(pulsed)||-||30|A|
|VSD_(3)_|Forward on voltage|VGS= 0 V, ISD= 7.5 A|-||1.6|V|
|trr|Reverse recoverytime|ISD= 7.5  A, di/dt = 100 A/µs,<br>VDD= 60 V (see_Figure 16:_<br>_"Test circuit for inductive load_<br>_switching and diode recovery_<br>_times"_)|-|270||ns|
|Qrr|Reverse recoverycharge||-|2||µC|
|IRRM|Reverse recovery current||-|14.4||A|
|trr|Reverse recoverytime|ISD= 7.5 A, di/dt = 100 A/µs,<br>VDD= 60 V, Tj= 150 °C (see<br>_Figure 16: "Test circuit for_<br>_inductive load switching and_<br>_diode recovery times"_)|-|376||ns|
|Qrr|Reverse recoverycharge||-|2.8||µC|
|IRRM|Reverse recovery current||-|15||A|



## **Notes:** 

(1) Limited by package. 

(2) Pulse width is limited by safe operating area. 

(3) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. 

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## **Electrical characteristics** 

## **2.2 Electrical characteristics (curves)** 

**Figure 2: Safe operating area** 

**==> picture [191 x 164] intentionally omitted <==**

**Figure 3: Thermal impedance** 

**==> picture [167 x 164] intentionally omitted <==**

**==> picture [433 x 188] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 4: Output characteristics  Figure 5: Transfer characteristics<br>AM15823v1 AM15824v1<br>ID ID(A)<br>(A) VGS=7, 8, 9, 10V VDS=18V<br>14 14<br>6V<br>12 12<br>10 10<br>8 8<br>6 6<br>5V<br>4 4<br>2 2<br>4V<br>0 0<br>0 5 10 15 20 VDS(V) 0 2 4 6 8 10 VGS(V)<br>**----- End of picture text -----**<br>


**Figure 6: Gate charge vs gate-source voltage** 

**==> picture [196 x 168] intentionally omitted <==**

**----- Start of picture text -----**<br>
AM15825v1<br>VGS VDS<br>(V)<br>(V)<br>12 VDS VDD=480V<br>ID=7.5A 500<br>10<br>400<br>8<br>300<br>6<br>200<br>4<br>100<br>2<br>0 0<br>0 2 4 6 8 10 12 Qg(nC)<br>**----- End of picture text -----**<br>


**Figure 7: Static drain-source on-resistance** 

**==> picture [182 x 166] intentionally omitted <==**

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**Electrical characteristics** 

**Figure 8: Capacitance variations** 

**Figure 9: Normalized gate threshold voltage vs temperature** 

**==> picture [190 x 166] intentionally omitted <==**

**----- Start of picture text -----**<br>
VGS(th)<br>(norm)<br>ID=250 µA<br>1.1<br>1.0<br>0.9<br>0.8<br>0.7<br>-50 -25 0 25 50 75 100 125 TJ(°C)<br>**----- End of picture text -----**<br>


**Figure 10: Normalized on-resistance vs temperature** 

**Figure 11: Normalized V(BR)DSS vs temperature** 

**==> picture [203 x 168] intentionally omitted <==**

**----- Start of picture text -----**<br>
RDS(on) AM15829v1<br>(norm)<br>2.5 ID=6.5 A<br>2.3 VGS=10V<br>2.1<br>1.9<br>1.7<br>1.5<br>1.3<br>1.1<br>0.9<br>0.7<br>0.5<br>-50 -25 0 25 50 75 100 125 TJ(°C)<br>**----- End of picture text -----**<br>


**Figure 12: Source-drain diode forward characteristics** 

**Figure 13: Output capacitance stored energy** 

**==> picture [200 x 168] intentionally omitted <==**

**----- Start of picture text -----**<br>
AM15830v1<br>VSD(V)<br>1.4<br>1.2<br>TJ=-50°C<br>1<br>0.8<br>0.6 —— TJ=25°C<br>TJ=150°C<br>0.4<br>0.2<br>0<br>0 1 2 3 4 5 6 7 ISD(A)<br>**----- End of picture text -----**<br>


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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 622] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 14: Test circuit for resistive load  Figure 15: Test circuit for gate charge<br>switching times  behavior<br>Figure 16: Test circuit for inductive load<br>switching and diode recovery times  Figure 17: Unclamped inductive load test<br>circuit<br>Figure 19: Switching time waveform<br>Figure 18: Unclamped inductive waveform<br>DocID024712 Rev 4<br>**----- End of picture text -----**<br>


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**STF10N60M2** 

**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

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**Package information** 

## **4.1 TO-220FP package information** 

**==> picture [161 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 20: TO-220FP package outline<br>**----- End of picture text -----**<br>


~~©~~ 10/13 DocID024712 Rev 4 

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**Package information** 

**Table 9: TO-220FP package mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|4.4||4.6|
|B|2.5||2.7|
|D|2.5||2.75|
|E|0.45||0.7|
|F|0.75||1|
|F1|1.15||1.70|
|F2|1.15||1.70|
|G|4.95||5.2|
|G1|2.4||2.7|
|H|10||10.4|
|L2||16||
|L3|28.6||30.6|
|L4|9.8||10.6|
|L5|2.9||3.6|
|L6|15.9||16.4|
|L7|9||9.3|
|Dia|3||3.2|



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**Revision history** 

## **5 Revision history** 

**Table 10: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|29-May-2013|1|First release.|
|14-Oct-2013|2|Modified: RGvalue in_Table 6_<br>Minor text changes|
|06-Dec-2013|3|Added: I2PAKFP package<br>– Modified: title<br>– Modified: RDS(on)typical values in_Table 5_<br>– Modified: RGvalue in_Table 6_<br>– Modified:_Figure 7_and IDvalue in_Figure 10_<br>– Added:_Table 10_, and_Figure 21_<br>– Minor text changes|
|09-Mar-2017|4|The device in I2PAKFP has been removed and this document has<br>been updated accordingly.<br>Updated the title and the description in cover page.<br>Updated_Table 4: "Avalanche characteristics"_.<br>Minor text changes.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2017 STMicroelectronics – All rights reserved 

DocID024712 Rev 4 

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