# Power MOSFET, N Channel, 30 V, 80 A, 4200 µohm, TO-252 (DPAK), Surface Mount

![Product image](https://novapart.co/image/farnell:3367029RL/)

**URL**: https://novapart.co/products/STD96N3LLH6/power-mosfet-n-channel-30-v-80-a-4200-ohm-to-252
**SKU**: STD96N3LLH6
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.3540
**Stock**: 1000+
**Lead Time**: 127 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | STripFET VI DeepGATE |
| Qualification | - |
| Power Dissipation | 70W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 30V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 80A |
| Drain Source On State Resistance | 4200µohm |
| Gate Source Threshold Voltage Max | 2.5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3367029RL/)

**==> picture [61 x 39] intentionally omitted <==**

## **STD96N3LLH6** N-channel 30 V, 0.0037 Ω, 80 A, DPAK STripFET™ VI DeepGATE™ Power MOSFET 

## **Features** 

|**Type**|**VDSS**|**RDS(on)max**|**ID**|
|---|---|---|---|
|STD96N3LLH6|30 V|0.0042Ω|80 A|



- RDS(on) * Qg industry benchmark 

- Extremely low on-resistance RDS(on) 

- High avalanche ruggedness 

- Low gate drive power losses 

**==> picture [57 x 81] intentionally omitted <==**

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3<br>1<br>DPAK<br>**----- End of picture text -----**<br>


## **Application** 

- Switching applications 

   - Automotive 

## **Description** 

This product is an N-channel Power MOSFET that utilizes the 6[th] generation of design rules  of ST’s proprietary STripFET™ technology, with a new gate structure. The resulting Power MOSFET exhibits the lowest RDS(on) in all packages. 

## **Figure 1. Internal schematic diagram** 

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D (TAB or 2)<br>G(1)<br>S(3)<br>AM01474v1<br>**----- End of picture text -----**<br>


**Table 1. Device summary** 

|**Order codes**|**Marking**|**Package**|**Packaging**|
|---|---|---|---|
|STD96N3LLH6|96N3LLH6|DPAK|Tape and reel|



1/15 

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Doc ID 18432 Rev 1 

_www.st.com_ 

**Contents** 

**STD96N3LLH6** 

|**Contents**|**Contents**|
|---|---|
|**1**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3**|
|**2**|**Electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4**|
||2.1<br>Electrical characteristics (curves)     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**3**|**Test circuits     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8**|
|**4**|**Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10**|
|**5**|**Packaging mechanical data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12**|
|**6**|**Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14**|



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**Electrical ratings** 

## **1 Electrical ratings** 

## **Table 2. Absolute maximum ratings** 

|**Table 2.**|**Absolute maximum ratings**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|VDS|Drain-source voltage (VGS= 0)|30|V|
|VGS|Gate-source voltage|± 20|V|
|ID<br>(1)|Drain current (continuous) at TC= 25 °C|80|A|
|ID|Drain current (continuous) at TC= 100 °C|61|A|
|IDM<br>(2)|Drain current (pulsed)|320|A|
|PTOT|Total dissipation at TC= 25 °C|70|W|
||Derating factor|0.47|W/°C|
|EAS<br>(3)|Single pulse avalanche energy|150|mJ|
|Tstg|Storage temperature|-55 to 175|°C|
|Tj|Max. operating junction temperature|175|°C|



1. Limited by wire bonding. 

2. Pulse width limited by safe operating area. 

3. Starting Tj = 25°C, IAV = 55 A, L = 0.1 mH 

## **Table 3. Thermal data** 

|**Table 3.**|**Thermal data**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|Rthj-case|Thermal resistance junction-case max|2.14|°C/W|
|Rthj-amb|Thermal resistance junction-ambient max|100|°C/W|
|Rthj-pcb<br>(1)|Thermal resistance junction-pcb max|35|°C/W|
|Tl|Maximum lead temperature for soldering purpose|275|°C|



1. When mounted on FR-4 board of 1 inch[2] , 2 oz Cu. 

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**STD96N3LLH6** 

**Electrical characteristics** 

## **2 Electrical characteristics** 

(TCASE = 25 °C unless otherwise specified) 

## **Table 4. Static** 

|**Table 4.**|**Static**||||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|V(BR)DSS|Drain-source breakdown<br>Voltage|ID= 250 µA, VGS= 0|30|||V|
|IDSS|Zero gate voltage drain<br>current (VGS= 0)|VDS= 30 V<br>VDS= 30 V, Tc = 125 °C|||1<br>10|µA<br>µA|
|IGSS|Gate body leakage current<br>(VDS= 0)|VGS= ± 20 V|||±100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 µA|1||2.5|V|
|RDS(on)|Static drain-source on<br>resistance|VGS= 10 V, ID= 40 A||0.0037|0.0042|Ω|
|||VGS= 5.5 V, ID= 40 A||0.0055|0.007|Ω|



## **Table 5. Dynamic** 

|**Table 5.**|**Dynamic**||||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min**|**Typ.**|**Max.**|**Unit**|
|Ciss<br>Coss<br>Crss|Input capacitance<br>Output capacitance<br>Reverse transfer<br>capacitance|VDS= 25 V, f=1 MHz,<br>VGS= 0|-|2200<br>400<br>280|-|pF<br>pF<br>pF|
|Qg<br>Qgs<br>Qgd|Total gate charge<br>Gate-source charge<br>Gate-drain charge|VDD= 15 V, ID= 80 A<br>VGS= 4.5 V<br>_Figure 13_|-|20<br>8.2<br>7.5|-|nC<br>nC<br>nC|
|Qgs1<br>Qgs2|Pre Vthgate-to-source<br>charge<br>Post Vthgate-to-source<br>charge|VDD= 15 V, ID= 80 A<br>_Figure 18_|-|3.4<br>6.2|-|nC<br>nC|
|RG|Gate input resistance|f = 1 MHz gate bias<br>Bias = 0 test signal<br>level = 20 mV<br>open drain|-|1|-|Ω|



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**Electrical characteristics** 

## **Table 6. Switching on/off (inductive load)** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)<br>tr|Turn-on delay time<br>Rise time|VDD= 15 V, ID= 40 A,<br>RG= 4.7Ω,VGS= 5 V<br>_Figure 12_|-|19<br>91|-|ns<br>ns|
|td(off)<br>tf|Turn-off delay time<br>Fall time|VDD= 15 V, ID= 40 A,<br>RG= 4.7Ω,  VGS= 5 V<br>_Figure 12_|-|24.5<br>23.4|-|ns<br>ns|



## **Table 7. Source drain diode** 

|**Table 7.**|**Source drain diode**||||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|ISD<br>ISDM<br>(1)|Source-drain current<br>Source-drain current (pulsed)||-||80<br>320|A<br>A|
|VSD<br>(2)|Forward on voltage|ISD= 40 A, VGS= 0|-||1.1|V|
|trr<br>Qrr<br>IRRM|Reverse recovery time<br>Reverse recovery charge<br>Reverse recovery current|ISD= 80 A,<br>di/dt = 100 A/µs,<br>VDD= 24 V<br>_Figure 14_|-|28.6<br>22.8<br>1.6||ns<br>nC<br>A|



1. Pulse width limited by safe operating area 

2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% 

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**STD96N3LLH6** 

**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

## **Figure 2. Safe operating area** 

## **Figure 3. Thermal impedance** 

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ID AM03376v1 K 280dpc<br>(A)<br>δ=0.5<br>100<br>0.2<br>100µs 0.1 0.05<br>10 10-1<br>1ms 0.02<br>Zth=k Rthj-c<br>1 Tc=25°CTj=175°C 10ms 0.01 δ=tp/τ<br>Sinlge<br>pulse -2 Single pulse tp τ<br>0.1 10<br>0.1 1 10 VDS(V) 10-5 10-4 10-3 10-2 10-1 tp [(s)]<br>Figure 4. Output characteristics Figure 5. Transfer characteristics<br>AM03379v1 AM03380v1<br>ID ID<br>(A) VGS=10V (A) VDS=2V<br>300 7V 300<br>6V<br>250 250<br>200 200<br>5V<br>150 150<br>100 4V 100<br>50 50<br>3V<br>0 0<br>0 2 4 VDS(V) 0 2 4 6 8 VGS(V)<br>Figure 6. Normalized BVDSS vs temperature Figure 7. Static drain source on resistance<br>BVDSS AM03381v1 RDS(on) AM03382v1<br>(norm) (mΩ)<br>@250µA 7 VGS=10V<br>1.05 6<br>5<br>1.00 4<br>3<br>0.95 2<br>1<br>0.90 0<br>-55 -30 -5 20 45 70 95 120 145 TJ(°C) 0 10 20 30 40 ID(A)<br>DS(on)<br>Operation in this area is<br>Limited by max R<br>**----- End of picture text -----**<br>


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**STD96N3LLH6** 

**Electrical characteristics** 

**Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations** 

**==> picture [463 x 176] intentionally omitted <==**

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VGS AM03378v1 C AM03377v1<br>(V) (pF)<br>VDD=15V<br>12<br>ID=80A<br>10<br>Ciss<br>8<br>1000<br>6<br>Coss<br>4<br>Crss<br>2<br>0 100<br>0 10 20 30 40 50 Qg(nC) 5 10 15 20 20 VDS(V)<br>**----- End of picture text -----**<br>


**Figure 10. Normalized gate threshold voltage Figure 11. Normalized on resistance vs vs temperature temperature** 

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VGS(th) AM03383v1<br>(norm)<br>@250µA<br>1.2<br>1.0<br>0.8<br>0.6<br>0.4<br>0.2<br>0<br>-55 -30 -5 20 45 70 95 120 145 TJ(°C)<br>**----- End of picture text -----**<br>


**==> picture [228 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
RDS(on) AM03384v1<br>(norm)<br>VGS=10V<br>1.8<br>ID=40A<br>1.6<br>1.4<br>1.2<br>1.0<br>0.8<br>0.6<br>-55 -30 -5 20 45 70 95 120 145 TJ(°C)<br>**----- End of picture text -----**<br>


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**Test circuits** 

## **3 Test circuits** 

**Figure 12. Switching times test circuit for Figure 13. Gate charge test circuit resistive load** 

**==> picture [463 x 162] intentionally omitted <==**

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VDD<br>12V 47kΩ<br>1kΩ<br>100nF<br>RL 2200 3.3<br>µF µF<br>VDD IG=CONST<br>VD Vi=20V=VGMAX 100Ω D.U.T.<br>VGS<br>2200<br>RG D.U.T. µF 2.7kΩ VG<br>PW<br>47kΩ<br>1kΩ<br>PW<br>AM01468v1 AM01469v1<br>**----- End of picture text -----**<br>


**Figure 14. Test circuit for inductive load Figure 15. Unclamped inductive load test switching and diode recovery times circuit** 

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**----- Start of picture text -----**<br>
L<br>A A A<br>D<br>G D.U.T. FASTDIODE L=100µH VD 2200 3.3<br>S B 3.3 1000 µF µF VDD<br>25 Ω B B D µF µF VDD ID<br>G<br>RG S<br>Vi D.U.T.<br>Pw<br>AM01470v1 AM01471v1<br>**----- End of picture text -----**<br>


**Figure 16. Unclamped inductive waveform Figure 17. Switching time waveform** 

**==> picture [463 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
V(BR)DSS ton toff<br>VD tdon tr tdoff tf<br>90% 90%<br>IDM<br>10%<br>ID 0 10% VDS<br>VDD VDD 90%<br>VGS<br>AM01472v1 0 10% AM01473v1<br>**----- End of picture text -----**<br>


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**Test circuits** 

## **Figure 18. Gate charge waveform** 

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**----- Start of picture text -----**<br>
Id<br>Vds<br>Vgs<br>Vgs(th)<br>Qgs1 Qgs2 Qgd<br>**----- End of picture text -----**<br>


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**Package mechanical data** 

## **4 Package mechanical data** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 

**Table 8. DPAK (TO-252) mechanical data** 

|**Dim.**|**mm**|**mm**|**mm**|
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|2.20||2.40|
|A1|0.90||1.10|
|A2|0.03||0.23|
|b|0.64||0.90|
|b4|5.20||5.40|
|c|0.45||0.60|
|c2|0.48||0.60|
|D|6.00||6.20|
|D1||5.10||
|E|6.40||6.60|
|E1||4.70||
|e||2.28||
|e1|4.40||4.60|
|H|9.35||10.10|
|L|1|||
|L1||2.80||
|L2||0.80||
|L4|0.60||1|
|R||0.20||
|V2|0°||8°|



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**Package mechanical data** 

## **Figure 19. DPAK (TO-252) drawing** 

**==> picture [405 x 284] intentionally omitted <==**

**----- Start of picture text -----**<br>
0068772_G<br>**----- End of picture text -----**<br>


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**Packaging mechanical data** 

## **5 Packaging mechanical data** 

**Table 9. DPAK (TO-252) tape and reel mechanical data** 

||**Tape**|**Tape**||**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Dim.**|**mm**||**Dim.**|**mm**||
||**Min.**|**Max.**||**Min.**|**Max.**|
|A0|6.8|7|A||330|
|B0|10.4|10.6|B|1.5||
|B1||12.1|C|12.8|13.2|
|D|1.5|1.6|D|20.2||
|D1|1.5||G|16.4|18.4|
|E|1.65|1.85|N|50||
|F|7.4|7.6|T||22.4|
|K0|2.55|2.75||||
|P0|3.9|4.1||Base qty.|2500|
|P1|7.9|8.1||Bulk qty.|2500|
|P2|1.9|2.1||||
|R|40|||||
|T|0.25|0.35||||
|W|15.7|16.3||||



**Figure 20. DPAK footprint[(a)]** 

**==> picture [405 x 150] intentionally omitted <==**

**----- Start of picture text -----**<br>
6.7 1.8 3<br>1.6<br>2.3<br>6.7<br>2.3<br>1.6<br>AM08850v1<br>**----- End of picture text -----**<br>


a. All dimension are in millimeters 

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**Packaging mechanical data** 

**==> picture [395 x 327] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 21. Tape for DPAK (TO-252)<br>10 pitches cumulative<br>tolerance on tape +/- 0.2 mm<br>Top cover P0 D P2<br>T tape<br>E<br>| paeneedooeas F<br>K0 W<br>B1 B0<br>f ekaciainiaioy<br>For machine ref. only A0 P1 D1<br>including draft and<br>radii concentric around B0 —_—_—_—_»<br>User direction of feed<br>R<br>ELSES<br>—_——_—_» Bending radius<br>User direction of feed<br>**----- End of picture text -----**<br>


**==> picture [39 x 6] intentionally omitted <==**

**----- Start of picture text -----**<br>
AM08852v1<br>**----- End of picture text -----**<br>


## **Figure 22. Reel for DPAK (TO-252)** 

**==> picture [377 x 249] intentionally omitted <==**

**----- Start of picture text -----**<br>
T<br>REEL DIMENSIONS<br>40mm min.<br>Access hole<br>At sl ot location<br>B<br>D<br>C<br>N<br>A<br>Full radius Tape slot  G measured at hub<br>in core for<br>tape start 25 mm min.<br>width<br>AM08851v2<br>**----- End of picture text -----**<br>


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**Revision history** 

## **6 Revision history** 

**Table 10. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|27-Jan-2011|1|First release.|



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## Links

- [View this product on Novapart](https://novapart.co/products/STD96N3LLH6/power-mosfet-n-channel-30-v-80-a-4200-ohm-to-252)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/stmicroelectronics/std96n3llh6/mosfet-n-ch-30v-80a-to-252-3/dp/3367029RL)
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