# Power MOSFET, N Channel, 800 V, 6 A, 0.8 ohm, TO-252 (DPAK), Surface Mount

![Product image](https://novapart.co/image/farnell:3129675/)

**URL**: https://novapart.co/products/STD8N80K5/power-mosfet-n-channel-800-v-6-a-08-ohm-to-252
**SKU**: STD8N80K5
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.9310
**Stock**: 1000+
**Lead Time**: 113 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:6A; Drain Source Voltage Vds:800V; On Resistance Rds(on):0.8ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4V; Po

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | MDmesh K5 |
| Qualification | - |
| Power Dissipation | 110W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 800V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 6A |
| Drain Source On State Resistance | 0.8ohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3129675/)

**STD8N80K5** 

Datasheet 

N-channel 800 V, 0.8 Ω typ., 6 A MDmesh™ K5 Power MOSFET in a DPAK package 

## **Features** 

**==> picture [55 x 63] intentionally omitted <==**

**----- Start of picture text -----**<br>
TAB<br>2 3<br>&.<br>1<br>DPAK<br>**----- End of picture text -----**<br>


|**Order code**<br>~~SS~~|**VDS**|**RDS(on ) max.**|**ID**|**PTOT**|
|---|---|---|---|---|
|STD8N80K5<br>~~SS~~|800 V|0.95 Ω|6 A|110 W|



- Industry’s lowest RDS(on) x area 

- Industry’s best FoM (figure of merit) 

- Ultra-low gate charge 

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D(2, TAB)<br>**----- End of picture text -----**<br>


- 100% avalanche tested 

- Zener-protected 

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G(1)<br>S(3) AM01475V1<br>**----- End of picture text -----**<br>


## **Applications** 

- Switching applications 

## **Description** 

This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. 

## **Product status** ~~ea~~ 

|**Product summary**<br>~~Saas~~|**Product summary**<br>~~Saas~~|
|---|---|
|**Order code**|STD8N80K5|
|**Marking**|8N80K5|
|**Package**|DPAK|
|**Packing**|Tape and reel|



**DS9561** - **Rev 3** - **August 2018** For further information contact your local STMicroelectronics sales office. 

www.st.com 

**STD8N80K5 Electrical ratings** 

**1** 

## **Electrical ratings** 

**Table 1. Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VGS|Gate-source voltage|±30|V|
|ID|Drain current (continuous) at TC= 25 °C|6|A|
|ID|Drain current (continuous) at TC= 100 °C|4|A|
|IDM (1)|Drain current pulsed|24|A|
|PTOT|Total dissipation at TC= 25 °C|110|W|
|dv/dt(2)|Peak diode recovery voltage slope|4.5|V/ns|
|dv/dt(3)|MOSFET dv/dt ruggedness|50||
|Tj|Operating junction temperature range|- 55 to 150|°C|
|Tstg|Storage temperature range|||



_1. Pulse width limited by safe operating area._ 

_2. ISD≤ 6 A, di/dt ≤ 100 A/μs; VDS peak ≤ V(BR)DSS_ 

_3. VDS ≤ 640 V_ 

## **Table 2. Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistance junction-case|1.14|°C/W|
|Rthj-pcb(1)|Thermal resistance junction-pcb|50|°C/W|



_1. When mounted on 1inch² FR-4 board, 2 oz Cu_ 

**Table 3. Avalanche characteristics** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|IAR|Avalanche current, repetitive or not repetitive<br>(pulse width limited by Tjmax.)|2|A|
|EAS|Single pulse avalanche energy<br>(starting TJ= 25 °C, ID= IAR, VDD= 50 V)|114|mJ|



**DS9561** - **Rev 3** 

**page 2/19** 

**STD8N80K5 Electrical characteristics** 

## **2 Electrical characteristics** 

TC = 25 °C unless otherwise specified 

**Table 4. On/off-state** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|VGS= 0 V, ID= 1 mA|800|||V|
|IDSS|Zero gate voltage drain<br>current|VGS= 0 V, VDS= 800 V|||1|µA|
|||VGS= 0 V, VDS= 800 V<br>TC= 125 °C(1)|||50|µA|
|IGSS|Gate body leakage current|VDS= 0 V, VGS= ±20 V|||±10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 100 µA|3|4|5|V|
|RDS(on)|Static drain-source on-<br>resistance|VGS= 10 V, ID= 3 A||0.8|0.95|Ω|



_1. Defined by design, not subject to production test._ 

**Table 5. Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 100 V, f = 1 MHz,<br>VGS= 0 V|-|450|-|pF|
|Coss|Output capacitance||-|50|-|pF|
|Crss|Reverse transfer capacitance||-|1|-|pF|
|Co(tr) (1)|Equivalent capacitance time<br>related|VDS= 0 to 640 V, VGS= 0 V|-|57|-|pF|
|Co(er) (2)|Equivalent capacitance<br>energy related|||24|-|pF|
|Rg|Intrinsic gate resistance|f = 1 MHz , ID= 0 A|-|6|-|Ω|
|Qg|Total gate charge|VDD= 640 V, ID= 6 A<br>VGS= 0 to 10 V<br>(seeFigure 15. Test circuit for<br>gate charge behavior)|-|16.5|-|nC|
|Qgs|Gate-source charge||-|3.2|-|nC|
|Qgd|Gate-drain charge||-|11|-|nC|



_1. Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS._ 

_2. Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS._ 

**Table 6. Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD= 400 V, ID= 3 A, RG=<br>4.7 Ω, VGS= 10 V (seeFigure<br>14. Test circuit for resistive<br>load switching timesand<br>Figure 19. Switching time<br>waveform)|-|12|-|ns|
|tr|Rise time||-|14|-|ns|
|td(off)|Turn-off delay time||-|32|-|ns|
|tf|Fall time||-|20|-|ns|



**DS9561** - **Rev 3** 

**page 3/19** 

**STD8N80K5 Electrical characteristics** 

## **Table 7. Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||6|A|
|ISDM (1)|Source-drain current (pulsed)||-||24|A|
|VSD (2)|Forward on voltage|ISD= 6 A, VGS= 0 V|-||1.5|V|
|trr|Reverse recovery time|ISD= 6 A, di/dt = 100 A/µs,<br>VDD= 60 V, seeFigure<br>16. Test circuit for inductive<br>load switching and diode<br>recovery times)|-|300||ns|
|Qrr|Reverse recovery charge||-|3||µC|
|IRRM|Reverse recovery current||-|20||A|
|trr|Reverse recovery time|ISD= 6 A, di/dt = 100 A/µs,<br>VDD= 60 V, Tj= 150 °C<br>(seeFigure 16. Test circuit for<br>inductive load switching and<br>diode recovery times)|-|415||ns|
|Qrr|Reverse recovery charge||-|3.8||µC|
|IRRM|Reverse recovery current||-|18||A|



_1. Pulse width limited by safe operating area._ 

_2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%._ 

**Table 8. Gate-source Zener diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)GSO|Gate-source breakdown<br>voltage|IGS= ±1 mA, ID= 0 A|±30|-|-|V|



The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry. 

**DS9561** - **Rev 3** 

**page 4/19** 

**STD8N80K5 Electrical characteristics (curves)** 

## **2.1 Electrical characteristics (curves)** 

**Figure 1. Safe operating area** 

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**----- Start of picture text -----**<br>
ID AM15630v1<br>(A)<br>10 10µs<br>Ron limit 100µs<br>1<br>1ms<br>10ms<br>0.1 Tj=150°C<br>Tc=25°C<br>Single pulse<br>0.01<br>0.1 1 10 100 VDS(V)<br>Limited by max    R<br>DS(on)<br>Operation in this area is<br>**----- End of picture text -----**<br>


**Figure 3. Output characteristics** 

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**----- Start of picture text -----**<br>
AM15633v1<br>ID (A)<br>VGS=10, 11V<br>12<br>9V<br>10<br>8<br>8V<br>6<br>4<br>7V<br>2<br>6V<br>0<br>0 4 8 12 16 VDS(V)<br>**----- End of picture text -----**<br>


**Figure 5. Gate charge vs. gate-source voltage** 

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AM15635v1<br>VGS<br>VDS<br>(V) VDS VDDID=6A=640V (V)<br>12 600<br>10 500<br>8 400<br>6 300<br>4 200<br>2 100<br>0 0<br>0 4 8 12 16 Qg(nC)<br>**----- End of picture text -----**<br>


**Figure 2. Thermal impedance** 

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K GC20460<br>10 [0]<br>10 [-1]<br>10 [-2]<br>10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] tp (s)<br>**----- End of picture text -----**<br>


**Figure 4. Transfer characteristics** 

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AM15634v1<br>ID (A)<br>12 VDS=20V<br>10<br>8<br>6<br>4<br>2<br>0<br>5 6 7 8 9 10 VGS(V)<br>**----- End of picture text -----**<br>


**Figure 6. Static drain-source on-resistance** 

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AM15636v1<br>RDS(on)<br>(Ω)<br>VGS=10V<br>1.6<br>1.2<br>0.8<br>0.4<br>0<br>1 2 3 4 5 6 ID(A)<br>**----- End of picture text -----**<br>


**DS9561** - **Rev 3** 

**page 5/19** 

**STD8N80K5 Electrical characteristics (curves)** 

**Figure 7. Capacitance variations** 

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**----- Start of picture text -----**<br>
C AM15637v1<br>(pF)<br>1000<br>Ciss<br>100<br>Coss<br>10<br>Crss<br>1<br>0.1 1 10 100 VDS(V)<br>**----- End of picture text -----**<br>


**Figure 8. Source-drain diode forward characteristics** 

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**----- Start of picture text -----**<br>
AM15641v1<br>VSD<br>(V) TJ=-50°C<br>0.9<br>TJ=25°C<br>0.8<br>0.7<br>TJ=150°C<br>0.6<br>0.5<br>1 2 3 4 5 ISD(A)<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
Figure 9. Normalized gate threshold voltage vs.<br>Figure 10. Normalized on-resistance vs. temperature<br>temperature<br>VGS(th) AM15639v1 RDS(on) AM15640v1<br>(norm) ID=100µA (norm) VGS=10V<br>VDS=VGS 2.4 ID=3 A<br>1<br>2<br>1.6<br>0.8<br>1.2<br>0.6<br>0.8<br>0.4<br>0.4 -50 0 50 100 TJ(°C)<br>-50 0 50 100 TJ(°C)<br>**----- End of picture text -----**<br>


**Figure 11. Normalized V(BR)DSS vs. temperature** 

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V(BR)DSS AM15642v1<br>(norm)<br>1.1 ID = 1mA<br>1.06<br>1.02<br>0.98<br>0.94<br>0.9<br>-50 0 50 100 TJ(°C)<br>**----- End of picture text -----**<br>


**Figure 12. Maximum avalanche energy vs. starting TJ** 

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AM15643v1<br>EAS (mJ)<br>VDD=50V<br>ID=2A<br>100<br>80<br>60<br>40<br>20<br>0<br>0 40 80 120 TJ(°C)<br>**----- End of picture text -----**<br>


**DS9561** - **Rev 3** 

**page 6/19** 

**STD8N80K5 Electrical characteristics (curves)** 

**Figure 13. Output capacitance stored energy** 

**==> picture [180 x 147] intentionally omitted <==**

**----- Start of picture text -----**<br>
AM15638v1<br>Eoss (µJ)<br>6<br>4<br>2<br>0<br>0 200 400 600 VDS(V)<br>**----- End of picture text -----**<br>


**DS9561** - **Rev 3** 

**page 7/19** 

**STD8N80K5 Test circuits** 

**3 Test circuits** 

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Figure 14. Test circuit for resistive load switching times Figure 15. Test circuit for gate charge behavior<br>VDD<br>12 V 47 kΩ<br>1 kΩ<br>100 nF<br>RL 2200 3.3<br>+ μF μF VDD<br>VD VGS IG= CONST 100 Ω D.U.T.<br>VGS RG D.U.T. pulse width 2200 + 2.7 kΩ VG<br>pulse width μF<br>47 kΩ<br>1 kΩ<br>AM01468v1 AM01469v1<br>**----- End of picture text -----**<br>


**==> picture [513 x 184] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 16. Test circuit for inductive load switching and<br>Figure 17. Unclamped inductive load test circuit<br>diode recovery times<br>A A A L<br>G D D.U.T. fastdiode 100 µH VD 2200 3.3<br>25 Ω S B B B D µF3.3 + 1000µF VDD ID + µF µF VDD<br>G D.U.T.<br>+ RG S Vi D.U.T.<br>_ pulse width<br>AM01471v1<br>AM01470v1<br>**----- End of picture text -----**<br>


**==> picture [513 x 172] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 19. Switching time waveform<br>Figure 18. Unclamped inductive waveform<br>ton toff<br>V(BR)DSS<br>td(on) tr td(off) tf<br>VD<br>90% 90%<br>IDM<br>ID 0 10% VDS 10%<br>VDD VDD VGS 90%<br>AM01472v1 0 10%<br>AM01473v1<br>**----- End of picture text -----**<br>


**DS9561** - **Rev 3** 

**page 8/19** 

**STD8N80K5 Package information** 

**4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: www.st.com. ECOPACK[®] is an ST trademark. 

**DS9561** - **Rev 3** 

**page 9/19** 

**STD8N80K5 DPAK (TO-252) type A2 package information** 

## **4.1 DPAK (TO-252) type A2 package information** 

**Figure 20. DPAK (TO-252) type A2 package outline** 

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0068772_type-A2_rev25<br>**----- End of picture text -----**<br>


**DS9561** - **Rev 3** 

**page 10/19** 

**STD8N80K5 DPAK (TO-252) type A2 package information** 

**Table 9. DPAK (TO-252) type A2 mechanical data** 

|**Di**|**mm**|**mm**|**mm**|
|---|---|---|---|
|**m.**|**Min.**|**Typ.**|**Max.**|
|A|2.20||2.40|
|A1|0.90||1.10|
|A2|0.03||0.23|
|b|0.64||0.90|
|b4|5.20||5.40|
|c|0.45||0.60|
|c2|0.48||0.60|
|D|6.00||6.20|
|D1|4.95|5.10|5.25|
|E|6.40||6.60|
|E1|5.10|5.20|5.30|
|e|2.159|2.286|2.413|
|e1|4.445|4.572|4.699|
|H|9.35||10.10|
|L|1.00||1.50|
|L1|2.60|2.80|3.00|
|L2|0.65|0.80|0.95|
|L4|0.60||1.00|
|R||0.20||
|V2|0°||8°|



**DS9561** - **Rev 3** 

**page 11/19** 

**STD8N80K5 DPAK (TO-252) type C2 package information** 

## **4.2 DPAK (TO-252) type C2 package information** 

**Figure 21. DPAK (TO-252) type C2 package outline** 

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0068772_C2_25<br>**----- End of picture text -----**<br>


**DS9561** - **Rev 3** 

**page 12/19** 

**STD8N80K5 DPAK (TO-252) type C2 package information** 

**Table 10. DPAK (TO-252) type C2 mechanical data** 

|**Di**|**mm**|**mm**|**mm**|
|---|---|---|---|
|**m.**|**Min.**|**Typ.**|**Max.**|
|A|2.20|2.30|2.38|
|A1|0.90|1.01|1.10|
|A2|0.00||0.10|
|b|0.72||0.85|
|b4|5.13|5.33|5.46|
|c|0.47||0.60|
|c2|0.47||0.60|
|D|6.00|6.10|6.20|
|D1|5.10||5.60|
|E|6.50|6.60|6.70|
|E1|5.20||5.50|
|e|2.186|2.286|2.386|
|H|9.80|10.10|10.40|
|L|1.40|1.50|1.70|
|L1|2.90 REF|||
|L2|0.90||1.25|
|L3|0.51 BSC|||
|L4|0.60|0.80|1.00|
|L6|1.80 BSC|||
|θ1|5°|7°|9°|
|θ2|5°|7°|9°|
|V2|0°||8°|



**DS9561** - **Rev 3** 

**page 13/19** 

**STD8N80K5 DPAK (TO-252) type C2 package information** 

**Figure 22. DPAK (TO-252) recommended footprint (dimensions are in mm)** 

**==> picture [111 x 196] intentionally omitted <==**

FP_0068772_25 

**DS9561** - **Rev 3** 

**page 14/19** 

**STD8N80K5 DPAK (TO-252) packing information** ~~To~~ 

## **4.3** 

## **DPAK (TO-252) packing information** 

## **Figure 23. DPAK (TO-252) tape outline** 

**==> picture [398 x 316] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 pitches cumulative<br>tolerance on tape +/- 0.2 mm<br>Top cover P0 D P2<br>T tape<br>E<br>F<br>B1 J) K0 B0 paeg e s W<br>I<br>f f  PEREllos oe oes:<br>For machine ref. only A0 P1 D1<br>including draft and<br>radii concentric around B0<br>User direction of feed<br>R<br>—— Bending radius<br>User direction of feed<br>AM08852v1<br>**----- End of picture text -----**<br>


**DS9561** - **Rev 3** 

**page 15/19** 

**STD8N80K5 DPAK (TO-252) packing information** 

**Figure 24. DPAK (TO-252) reel outline** 

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**----- Start of picture text -----**<br>
T<br>40mm min.<br>access hole<br>at slot location<br>B<br>D<br>C<br>N<br>A<br>Tape slot  G measured<br>in core for  at hub<br>Full radius  tape start<br>2.5mm min.width<br>**----- End of picture text -----**<br>


AM06038v1 

**Table 11. DPAK (TO-252) tape and reel mechanical data** 

||**Tape**|**Tape**||**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Di**|**mm**||**Di**|**mm**||
|**m.**|**Min.**|**Max.**|**m.**|**Min.**|**Max.**|
|A0|6.8|7|A||330|
|B0|10.4|10.6|B|1.5||
|B1||12.1|C|12.8|13.2|
|D|1.5|1.6|D|20.2||
|D1|1.5||G|16.4|18.4|
|E|1.65|1.85|N|50||
|F|7.4|7.6|T||22.4|
|K0|2.55|2.75||||
|P0|3.9|4.1|Base qty.||2500|
|P1|7.9|8.1|Bulk qty.||2500|
|P2|1.9|2.1||||
|R|40|||||
|T|0.25|0.35||||
|W|15.7|16.3||||



**DS9561** - **Rev 3** 

**page 16/19** 

**STD8N80K5** 

## **Revision history** 

**Table 12. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|23-Mar-2013|1|First release. Part number previously included in datasheet DM00062075|
|29-Mar-2013|2|Added: MOSFET dv/dt ruggedness on_Table 2_|
|20-Aug-2018|3|UpdatedSection 4 Package information.<br>Minor text changes.|



**DS9561** - **Rev 3** 

**page 17/19** 

**STD8N80K5 Contents** 

## **Contents** 

|**1**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2**|
|---|---|---|
|**2**|**Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3**||
||**2.1**|Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5|
|**3**|**Test**|**circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8**|
|**4**|**Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9**||
||**4.1**|DPAK (TO-252) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
||**4.2**|DPAK (TO-252) type C2 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|
||**4.3**|DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14|
|**Revision**||**history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17**|



**DS9561** - **Rev 3** 

**page 18/19** 

**STD8N80K5** 

## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2018 STMicroelectronics – All rights reserved 

**DS9561** - **Rev 3** 

**page 19/19** 



## Links

- [View this product on Novapart](https://novapart.co/products/STD8N80K5/power-mosfet-n-channel-800-v-6-a-08-ohm-to-252)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/stmicroelectronics/std8n80k5/mosfet-n-ch-800v-6a-110w-to-252/dp/3129675)
---

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