# Power MOSFET, N Channel, 30 V, 80 A, 4500 µohm, TO-252 (DPAK), Surface Mount

![Product image](https://novapart.co/image/farnell:2807193/)

**URL**: https://novapart.co/products/STD86N3LH5/power-mosfet-n-channel-30-v-80-a-4500-ohm-to-252
**SKU**: STD86N3LH5
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.4360
**Stock**: 1000+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:80A; Drain Source Voltage Vds:30V; On Resistance Rds(on):0.0045ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:1.8V

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | STripFET H5 |
| Qualification | AEC-Q101 |
| Power Dissipation | 70W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 30V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 80A |
| Drain Source On State Resistance | 4500µohm |
| Gate Source Threshold Voltage Max | 1.8V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2807193/)

## **STD86N3LH5** 

## Automotive-grade N-channel 30 V, 0.0045 Ω typ, 80 A STripFET H5 Power MOSFET in a DPAK package 

**Datasheet** - **production data** 

## **Features** 

|**Features**||||
|---|---|---|---|
|**Order code**|**VDSS**|**RDS(on)max**|**ID**|
|STD86N3LH5|30 V|< 0.005Ω|80 A|



- Designed for automotive applications and AEC-Q101 qualified 

- Low on-resistance R DS(on) 

- High avalanche ruggedness 

- Low gate drive power losses 

## **Application** 

- Switching applications 

## **Figure 1. Internal schematic diagram** 

## **Description** 

This device is an N-channel Power MOSFET developed using STMicroelectronics’ STripFET™ H5 technology. The device has been optimized to achieve very low on-state resistance, contributing to a FoM that is among the best in its class. 

**Table 1. Device summary** 

|**Order code**|**Marking**|**Package**|**Packaging**|
|---|---|---|---|
|STD86N3LH5|86N3LH5|DPAK|Tape and reel|



_www.st.com_ 

May 2015 

DocID15575 Rev 3 

1/17 

This is information on a product in full production. 

**Contents** 

**STD86N3LH5** 

|**Contents**|**Contents**|
|---|---|
|**1**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3**|
|**2**|**Electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4**|
||2.1<br>Electrical characteristics (curves)         . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**3**|**Test circuit     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8**|
|**4**|**Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10**|
|**5**|**Packing information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14**|
|**6**|**Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2. Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage (VGS= 0 V)|30|V|
|VDS|Drain-source voltage (VGS= 0 V) @ TJMAX|35|V|
|VGS|Gate-source voltage|± 20|V|
|ID<br>(1)|Drain current (continuous) at TC= 25 °C|80|A|
|ID|Drain current (continuous) at TC= 100 °C|55|A|
|IDM<br>(2)|Drain current (pulsed)|320|A|
|PTOT|Total dissipation at TC= 25 °C|70|W|
||Derating factor|0.47|W/°C|
|EAS<br>(3)|Single pulse avalanche energy|165|mJ|
|Tstg|Storage temperature|-55 to 175|°C|
|Tj|Max. operating junction temperature|175|°C|



1. Limited by wire bonding 

2. Pulse width limited by safe operating area 

3. Starting Tj = 25°C, ID = 40 A, VDD = 25 V 

**Table 3. Thermal resistance** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistance junction-case max|2.14|°C/W|
|Rthj-pcb<br>(1)|Thermal resistance junction-pcb max|50|°C/W|



1. When mounted on 1 inch² FR-4 Oz Cu board 

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**STD86N3LH5** 

**Electrical characteristics** 

## **2 Electrical characteristics** 

(TCASE = 25 °C unless otherwise specified) 

**Table 4. Static** 

|||**Table 4. Static**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|V(BR)DSS|Drain-source breakdown<br>Voltage|ID= 250 µA, VGS= 0 V|30|-|-|V|
|IDSS|Zero gate voltage drain<br>current (VGS= 0 V)|VDS= 20 V<br>VDS= 20 V,Tc = 125 °C|-|-|1<br>10|µA<br>µA|
|IGSS|Gate body leakage current<br>(VDS= 0 V)|VGS= ± 20 V|-|-|±100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 µA|1|1.8|2.5|V|
|RDS(on)|Static drain-source on-<br>resistance|VGS= 10 V, ID= 40 A|-|0.0045|0.005|Ω|
|||VGS= 5 V, ID= 40 A|-|0.0055|0.0065|Ω|



**Table 5. Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 25 V, f=1 MHz,<br>VGS= 0 V|-|1850|-|pF|
|Coss|Output capacitance||-|380|-|pF|
|Crss|Reverse transfer<br>capacitance||-|58|-|pF|
|Qg|Total gate charge|VDD= 15 V, ID= 80 A<br>VGS= 5 V<br>_Figure 16_|-|14|-|nC|
|Qgs|Gate-source charge||-|6.8|-|nC|
|Qgd|Gate-drain charge||-|4.7|-|nC|
|Qgs1|Pre Vthgate-to-source<br>charge|VDD= 15 V, ID= 80 A<br>VGS= 5 V<br>_Figure 16_|-|2.3|-|nC|
|Qgs2|Post Vthgate-to-source<br>charge||-|4.5|-|nC|
|RG|Gate input resistance|f = 1 MHz gate bias<br>Bias = 0 test signal<br>level = 20 mV, open drain|-|1.2|-|Ω|



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**Electrical characteristics** 

**Table 6. Switching on/off (inductive load)** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD= 15 V, ID= 40 A,<br>RG= 4.7Ω,VGS= 5 V<br>_Figure 15_|-|6|-|ns|
|tr|Rise time||-|14|-|ns|
|td(off)|Turn-off delay time||-|23.6|-|ns|
|tf|Fall time||-|10.8|-|ns|



**Table 7. Source drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD<br>ISDM<br>(1)|Source-drain current<br>Source-drain current (pulsed)||-||80<br>320|A<br>A|
|VSD<br>(2)|Forward on voltage|ISD= 40 A, VGS= 0|-||1.1|V|
|trr|Reverse recovery time|ISD= 80 A,<br>di/dt = 100 A/µs,<br>VDD= 20 V<br>_Figure 17_|-|31.8||ns|
|Qrr|Reverse recovery charge||-|26.1||nC|
|IRRM|Reverse recovery current||-|1.6||A|



1. Pulse width limited by safe operating area 

2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% 

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**STD86N3LH5** 

**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2. Safe operating area** 

**==> picture [157 x 155] intentionally omitted <==**

## **Figure 3. Thermal impedance** 

**==> picture [161 x 155] intentionally omitted <==**

**Figure 4. Output characteristics** 

**==> picture [168 x 155] intentionally omitted <==**

## **Figure 5. Transfer characteristics** 

**==> picture [168 x 156] intentionally omitted <==**

**Figure 6. Normalized BVDSS vs temperature** 

**==> picture [168 x 153] intentionally omitted <==**

## **Figure 7. Static drain-source on resistance** 

**==> picture [205 x 154] intentionally omitted <==**

**----- Start of picture text -----**<br>
RDS(on) AM03396v1<br>(mΩ)<br>6.5<br>6.0 VGS=5V<br>5.5<br>5.0<br>VGS=10V<br>4.5<br>4.0<br>3.5<br>3.0<br>0 10 20 30 40 50 60 70 80 ID(A)<br>**----- End of picture text -----**<br>


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**Electrical characteristics** 

**Figure 8. Gate charge vs gate-source voltage** 

**==> picture [179 x 155] intentionally omitted <==**

**Figure 10. Normalized gate threshold voltage vs temperature** 

**==> picture [171 x 154] intentionally omitted <==**

**Figure 9. Capacitance variations** 

**==> picture [171 x 155] intentionally omitted <==**

**Figure 11. Normalized on resistance vs temperature** 

**==> picture [166 x 153] intentionally omitted <==**

**Figure 12. Source-drain diode forward characteristics** 

**==> picture [164 x 153] intentionally omitted <==**

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**Test circuit** 

## **3 Test circuit** 

**Figure 13. Switching times test circuit for resistive load** 

**Figure 14. Gate charge test circuit** 

**==> picture [462 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>12V 47kΩ<br>1kΩ<br>100nF<br>RL 2200 3.3<br>μF μF<br>VDD IG=CONST<br>VD Vi=20V=VGMAX 100Ω D.U.T.<br>VGS<br>2200<br>RG D.U.T. μF 2.7kΩ VG<br>PW<br>47kΩ<br>1kΩ<br>PW<br>AM01468v1 AM01469v1<br>**----- End of picture text -----**<br>


**Figure 15. Test circuit for inductive load Figure 16. Unclamped inductive load test circuit switching and diode recovery times** 

**==> picture [462 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
L<br>A A A<br>D<br>FAST L=100μH VD<br>G D.U.T. DIODE 2200 3.3<br>S B 3.3 1000 μF μF VDD<br>25 Ω B B D μF μF VDD ID<br>G<br>RG S<br>Vi D.U.T.<br>Pw<br>AM01470v1 AM01471v1<br>**----- End of picture text -----**<br>


**Figure 17. Unclamped inductive waveform** 

**Figure 18. Switching time waveform** 

**==> picture [462 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
V(BR)DSS ton toff<br>VD tdon tr tdoff tf<br>90% 90%<br>IDM<br>10%<br>ID 0 10% VDS<br>VDD VDD 90%<br>VGS<br>AM01472v1 0 10% AM01473v1<br>**----- End of picture text -----**<br>


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**Test circuit** 

**Figure 19. Gate charge waveform** 

**==> picture [186 x 150] intentionally omitted <==**

**----- Start of picture text -----**<br>
Id<br>Vds<br>Vgs<br>Vgs(th)<br>Qgs1 Qgs2 Qgd<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 

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**Package information** 

## **Figure 20. DPAK (TO-252) type A2 outline** 

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**Package information** 

**Table 8. DPAK (TO-252) type A2 mechanical data** 

||**Table 8. DPAK(TO-252) type A2 mechanical data**|**Table 8. DPAK(TO-252) type A2 mechanical data**|**Table 8. DPAK(TO-252) type A2 mechanical data**|
|---|---|---|---|
|**Dim.**|**mm**|||
||**Min.**|**Typ.**|**Max.**|
|A|2.20||2.40|
|A1|0.90||1.10|
|A2|0.03||0.23|
|b|0.64||0.90|
|b4|5.20||5.40|
|c|0.45||0.60|
|c2|0.48||0.60|
|D|6.00||6.20|
|D1|4.95|5.10|5.25|
|E|6.40||6.60|
|E1|5.10|5.20|5.30|
|e|2.16|2.28|2.40|
|e1|4.40||4.60|
|H|9.35||10.10|
|L|1.00||1.50|
|L1|2.60|2.80|3.00|
|L2|0.65|0.80|0.95|
|L4|0.60||1.00|
|R||0.20||
|V2|0°||8°|



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**Package information** 

## **Figure 21. DPAK (TO-252) footprint[(a)]** 

- a. All dimensions are in millimeters 

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**Packing information** 

## **5 Packing information** 

## **Figure 22. Tape for DPAK (TO-252)** 

**==> picture [399 x 316] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 pitches cumulative<br>tolerance on tape +/- 0.2 mm<br>Top cover P0 D P2<br>T tape<br>E<br>F<br>K0 W<br>B1 B0<br>A) | Tl IRIE Co<br>For machine ref. only A0 P1 D1<br>including draft and<br>radii concentric around B0 SS»<br>User direction of feed<br>R<br>ol eh tel al fa l ta a<br>|» Bending radius<br>User direction of feed<br>AM08852v1<br>**----- End of picture text -----**<br>


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**Packing information** 

## **Figure 23. Reel for DPAK (TO-252)** 

**==> picture [405 x 256] intentionally omitted <==**

**----- Start of picture text -----**<br>
T<br>REEL DIMENSIONS<br>40mm min.<br>Access hole<br>At sl ot location<br>B<br>D<br>C<br>N<br>A<br>Full radius Tape slot  G measured at hub<br>in core for<br>tape start 25 mm min.<br>width<br>AM08851v2<br>**----- End of picture text -----**<br>


**Table 9. DPAK (TO-252) tape and reel mechanical data** 

||**Tape**|**Tape**||**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Dim.**|**mm**<br>**Min.**<br>**Max.**||**Dim.**|**mm**||
||**Min.**|||**Min.**|**Max.**|
|A0|6.8|7|A||330|
|B0|10.4|10.6|B|1.5||
|B1||12.1|C|12.8|13.2|
|D|1.5|1.6|D|20.2||
|D1|1.5||G|16.4|18.4|
|E|1.65|1.85|N|50||
|F|7.4|7.6|T||22.4|
|K0|2.55|2.75||||
|P0|3.9|4.1||Base qty.|2500|
|P1|7.9|8.1||Bulk qty.|2500|
|P2|1.9|2.1<br>0.35<br>16.3||||
|R|40|||||
|T|0.25|||||
|W|15.7|||||



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**Revision history** 

## **6 Revision history** 

**Table 10. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|10-Apr-2009|1|First release.|
|22-Mar-2011|2|VGSvalue has been corrected in_Table 2_and_Table 4_.|
|13-May-2015|3|Updated title, features and description in cover page.<br>Updated_Section 4: Package information_.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2015 STMicroelectronics – All rights reserved 

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## Links

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- [Supplier page](https://es.farnell.com/stmicroelectronics/std86n3lh5/mosfet-aec-q101-n-ch-30v-to-252/dp/2807193)
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