# Power MOSFET, N Channel, 650 V, 5 A, 0.98 ohm, TO-252 (DPAK), Surface Mount

![Product image](https://novapart.co/image/farnell:2460390/)

**URL**: https://novapart.co/products/STD7N65M2/power-mosfet-n-channel-650-v-5-a-098-ohm-to-252
**SKU**: STD7N65M2
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.4380
**Stock**: 1000+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:5A; Drain Source Voltage Vds:650V; On Resistance Rds(on):0.98ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:3V;

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 60W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 650V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 5A |
| Drain Source On State Resistance | 0.98ohm |
| Gate Source Threshold Voltage Max | 3V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2460390/)

## **STD7N65M2** 

N-channel 650 V, 0.98 Ω typ., 5 A MDmesh™ M2 Power MOSFET in a DPAK package 

**Datasheet** - **production data** 

## **Features** 

**==> picture [79 x 66] intentionally omitted <==**

**----- Start of picture text -----**<br>
TAB<br>3<br>1<br>DPAK<br>**----- End of picture text -----**<br>


|**Order code**|**VDS**|**RDS(on)**<br>**max**|**ID**|
|---|---|---|---|
|STD7N65M2|650 V|1.15Ω|5 A|



- Extremely low gate charge 

- Excellent output capacitance (Coss) profile 

- 100% avalanche tested 

- Zener-protected 

## **Applications** 

- Switching applications 

## **Figure 1. Internal schematic diagram** 

**==> picture [165 x 163] intentionally omitted <==**

**----- Start of picture text -----**<br>
D(2, TAB)<br>G(1)<br>S(3)<br>AM15572v1<br>**----- End of picture text -----**<br>


## **Description** 

This device is an N-channel Power MOSFET developed using the MDmesh™ M2 technology. Thanks to the strip layout associated to an improved vertical structure, the device exhibits both low on-resistance and optimized switching characteristics. It is therefore suitable for the most demanding high efficiency converters. 

**Table 1. Device summary** 

- **Order code Marking Package Packaging** STD7N65M2 7N65M2 DPAK Tape and reel 

- ~~———~~ 

_www.st.com_ 

May 2015 

DocID026787 Rev 2 

1/17 

This is information on a product in full production. 

**Contents** 

**STD7N65M2** 

|**Contents**|**Contents**|
|---|---|
|**1**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3**|
|**2**|**Electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4**|
||2.1<br>Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**3**|**Test circuits     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8**|
|**4**|**Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9**|
||4.1<br>DPAK (TO-252) type A package information  . . . . . . . . . . . . . . . . . . . . . . . 9|
||4.2<br>DPAK (TO-252) type C package information  . . . . . . . . . . . . . . . . . . . . . . .11|
|**5**|**Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14**|
|**6**|**Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2. Absolute maximum ratings** 

||**Table 2. Absolute maximum ratings**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|VGS|Gate-source voltage|± 25|V|
|ID|Drain current (continuous) at TC= 25 °C|5|A|
|ID|Drain current (continuous) at TC= 100 °C|3.2|A|
|IDM<br>(1)|Drain current (pulsed)|20|A|
|PTOT|Total dissipation at TC= 25 °C|60|W|
|dv/dt(2)|Peak diode recovery voltage slope|15|V/ns|
|dv/dt(3)|MOSFET dv/dt ruggedness|50||
|Tstg|Storage temperature|- 55 to 150|°C|
|Tj|Operating junction temperature|||



1. Pulse width limited by safe operating area 

2. ISD ≤ 5 A, di/dt ≤ 400 A/µs; VDS peak < V(BR)DSS, VDD=400 V 

3. VDS ≤ 520 V 

**Table 3. Thermal data** 

||**Table 3. Thermal data**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|Rthj-case|Thermal resistance junction-case max|2.08|°C/W|
|Rthj-pcb|Thermal resistance junction-pcb max|50(1)|°C/W|



1. When mounted on 1 inch² FR-4, 2 Oz copper board. 

**Table 4. Avalanche characteristics** 

||**Table 4. Avalanche characteristics**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|IAR|Avalanche current, repetitive or not repetitive (pulse width<br>limited by Tjmax)|1|A|
|EAS|Single pulse avalanche energy (starting Tj=25°C, ID= IAR;<br>VDD=50 V)|103|mJ|



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**STD7N65M2** 

**Electrical characteristics** 

## **2 Electrical characteristics** 

(TC = 25 °C unless otherwise specified) 

**Table 5. On /off states** 

|||**Table 5. On /off states**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|V(BR)DSS|Drain-source<br>breakdown voltage|VGS= 0, ID= 1 mA|650|||V|
|IDSS|Zero gate voltage<br>drain current|VGS= 0, VDS= 650 V|||1|µA|
|||VGS= 0, VDS= 650 V,<br>TC=125 °C|||100|µA|
|IGSS|Gate-body leakage<br>current|VDS= 0, VGS= ± 25 V|||±10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 µA|2|3|4|V|
|RDS(on)|Static drain-source<br>on-resistance|VGS= 10 V, ID= 2.5 A||0.98|1.15|Ω|



## **Table 6. Dynamic** 

|||**Table 6. Dynamic**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|Ciss|Input capacitance|VDS= 100 V, f = 1 MHz,<br>VGS= 0|-|270|-|pF|
|Coss|Output capacitance||-|14.5|-|pF|
|Crss|Reverse transfer<br>capacitance||-|0.8|-|pF|
|Coss eq.<br>(1)|Equivalent output<br>capacitance|VDS= 0 to 520 V, VGS= 0|-|108|-|pF|
|RG|Intrinsic gate<br>resistance|f = 1 MHz open drain|-|7|-|Ω|
|Qg|Total gate charge|VDD= 520 V, ID= 5 A,<br>VGS= 10 V<br>(see_Figure 15_)|-|9|-|nC|
|Qgs|Gate-source charge||-|2.3|-|nC|
|Qgd|Gate-drain charge||-|4.3|-|nC|



1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 

**Table 7. Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD= 325 V, ID= 2.5 A,<br>RG= 4.7Ω,VGS= 10 V<br>(see_Figure 14_and_19_)|-|8|-|ns|
|tr|Rise time||-|20|-|ns|
|td(off)|Turn-off delay time||-|30|-|ns|
|tf|Fall time||-|20|-|ns|



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**Electrical characteristics** 

**Table 8. Source drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||5|A|
|ISDM (1)|Source-drain current (pulsed)||-||20|A|
|VSD (2)|Forward on voltage|ISD= 5 A, VGS= 0|-||1.6|V|
|trr|Reverse recovery time|ISD= 5 A, di/dt = 100 A/µs<br>VDD= 60 V (see_Figure 19_)|-|275||ns|
|Qrr|Reverse recovery charge||-|1.62||µC|
|IRRM|Reverse recovery current||-|11.8||A|
|trr|Reverse recovery time|ISD= 5 A, di/dt = 100 A/µs<br>VDD= 60 V, Tj= 150 °C<br>(see_Figure 19_)|-|430||ns|
|Qrr|Reverse recovery charge||-|2.54||µC|
|IRRM|Reverse recovery current||-|11.9||A|



1. Pulse width limited by safe operating area. 

2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% 

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**STD7N65M2** 

**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2. Safe operating area** 

**==> picture [228 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
ID GIPG060820141409FSR<br>(A)<br>10<br>10μs<br>100μs<br>1<br>1ms<br>10ms<br>0.1<br>Tj=150°C<br>Tc=25°C<br>Single pulse<br>0.01<br>0.1 1 10 100 VDS(V)<br>DS(on)<br>Operation in this area is<br>Limited by max R<br>**----- End of picture text -----**<br>


## **Figure 3. Thermal impedance** 

**==> picture [165 x 167] intentionally omitted <==**

**Figure 4. Output characteristics** 

## **Figure 5. Transfer characteristics** 

**==> picture [462 x 176] intentionally omitted <==**

**----- Start of picture text -----**<br>
GIPG060820141159FSR GIPG060820141210FSR<br>ID(A) ID<br>VGS=7, 8, 9, 10V (A)<br>VDS=20V<br>8 8<br>6V<br>6 6<br>4 4<br>5V<br>2 2<br>4V<br>0<br>00 5 10 15 20 VDS(V) 0 2 4 6 8 VGS(V)<br>**----- End of picture text -----**<br>


**Figure 6. Gate charge vs gate-source voltage** 

**==> picture [228 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
VGS GIPG060820141216FSRVDS<br>(V) VDS VDD=520V (V)<br>12 ID=5A 600<br>10 500<br>8 400<br>6 300<br>4 200<br>2 100<br>0 0<br>0 2 4 6 8 10 Qg(nC)<br>**----- End of picture text -----**<br>


**Figure 7. Static drain-source on-resistance** 

**==> picture [228 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
GIPG060820141221FSR<br>RDS(on)<br>(Ω)<br>VGS=10V<br>1.04<br>1.02<br>1.0<br>0.98<br>0.96<br>0.94<br>0.92<br>0 1 2 3 4 5 ID(A)<br>**----- End of picture text -----**<br>


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**Electrical characteristics** 

**Figure 8. Capacitance variations** 

**==> picture [228 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
C GIPG060820141238FSR<br>(pF)<br>1000<br>Ciss<br>100<br>10 Coss<br>1 Crss<br>0.1<br>0.1 1 10 100 VDS(V)<br>**----- End of picture text -----**<br>


**Figure 10. Normalized gate threshold voltage vs temperature** 

**Figure 9. Output capacitance stored energy** 

**==> picture [228 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
Eoss GIPG060820141302FSR<br>(μJ)<br>2.4<br>1.8<br>1.2<br>0.6<br>0<br>0 100 200 300 400 500 600 VDS(V)<br>**----- End of picture text -----**<br>


**Figure 11. Normalized on-resistance vs temperature** 

**==> picture [462 x 176] intentionally omitted <==**

**----- Start of picture text -----**<br>
VGS(th) AM18065v1 RDS(on) AM18066v1<br>(norm) (norm)<br>ID=2.5A<br>ID=250μA VGS=10V<br>1.1 2.2<br>1.0 1.8<br>0.9 1.4<br>0.8 1.0<br>0.7 0.6<br>0.6 0.2<br>-75 25 0 25 75 125 TJ(°C) -75 -25 0 25 75 125 TJ(°C)<br>**----- End of picture text -----**<br>


**Figure 12. Source-drain diode forward characteristics** 

**Figure 13. Normalized V(BR)DSS vs temperature** 

**==> picture [462 x 176] intentionally omitted <==**

**----- Start of picture text -----**<br>
VSD (V) GIPG060820141313FSR V(BR)DSS(norm) AM18067v1<br>TJ=-50°C ID=1mA<br>1.1<br>1.08<br>1<br>1.04<br>0.9 T J =25°C<br>1.00<br>0.8<br>0.96<br>0.7<br>0.6 TJ=150°C 0.92<br>0.5 0.88<br>0 1 2 3 4 5 ISD(A) -75 -25 0 25 75 125 TJ(°C)<br>**----- End of picture text -----**<br>


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**Test circuits** 

## **3 Test circuits** 

**Figure 14. Switching times test circuit for resistive load** 

**Figure 15. Gate charge test circuit** 

**==> picture [462 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>12V 47kΩ<br>1kΩ<br>100nF<br>RL 2200 3.3<br>μF μF<br>VDD IG=CONST<br>VD Vi=20V=VGMAX 100Ω D.U.T.<br>VGS<br>2200<br>RG D.U.T. μF 2.7kΩ VG<br>PW<br>47kΩ<br>1kΩ<br>PW<br>AM01468v1 AM01469v1<br>**----- End of picture text -----**<br>


**Figure 16. Test circuit for inductive load Figure 17. Unclamped inductive load test circuit switching and diode recovery times** 

**==> picture [462 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
L<br>A A A<br>D<br>FAST L=100μH VD<br>G D.U.T. DIODE 2200 3.3<br>S B 3.3 1000 μF μF VDD<br>25 Ω B B D μF μF VDD ID<br>G<br>RG S<br>Vi D.U.T.<br>Pw<br>AM01470v1 AM01471v1<br>**----- End of picture text -----**<br>


## **Figure 18. Unclamped inductive waveform** 

## **Figure 19. Switching time waveform** 

**==> picture [462 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
�������� ton toff<br>�� tdon tr tdoff tf<br>90% 90%<br>���<br>10%<br>�� 0 10% VDS<br>��� ��� 90%<br>VGS<br>��������� 0 10% AM01473v1<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _www.st.com_ . ECOPACK[®] is an ST trademark. 

## **4.1 DPAK (TO-252) type A package information** 

**==> picture [233 x 11] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 20. DPAK (TO-252) type A package outline<br>**----- End of picture text -----**<br>


**==> picture [405 x 403] intentionally omitted <==**

**----- Start of picture text -----**<br>
������������<br>**----- End of picture text -----**<br>


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**Package information** 

**Table 9. DPAK (TO-252) type A package mechanical data** 

||**Table 9. DPAK(TO-252) type Apackage mechanical data**|**Table 9. DPAK(TO-252) type Apackage mechanical data**|**Table 9. DPAK(TO-252) type Apackage mechanical data**|
|---|---|---|---|
|**Dim.**|**mm**|||
||**Min.**|**Typ.**|**Max.**|
|A|2.20||2.40|
|A1|0.90||1.10|
|A2|0.03||0.23|
|b|0.64||0.90|
|b4|5.20||5.40|
|c|0.45||0.60|
|c2|0.48||0.60|
|D|6.00||6.20|
|D1|4.95|5.10|5.25|
|E|6.40||6.60|
|E1|4.60|4.70|4.80|
|e|2.16|2.28|2.40|
|e1|4.40||4.60|
|H|9.35||10.10|
|L|1.00||1.50|
|(L1)|2.60|2.80|3.00|
|L2|0.65|0.80|0.95|
|L4|0.60||1.00|
|R||0.20||
|V2|0°||8°|



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**Package information** 

## **4.2 DPAK (TO-252) type C package information** 

**==> picture [233 x 11] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 21. DPAK (TO-252) type C package outline<br>**----- End of picture text -----**<br>


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**Package information** 

**Table 10. DPAK (TO-252) type C package mechanical data** 

|**Dim.**|**mm**|**mm**|**mm**|
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|2.20|2.30|2.38|
|A1|0.90|1.01|1.10|
|A2|0.00||0.10|
|b|0.72||0.85|
|b4|5.13|5.33|5.46|
|c|0.47||0.60|
|c2|0.47||0.60|
|D|6.00|6.10|6.20|
|D1|5.25|||
|E|6.50|6.60|6.70|
|e|2.186|2.286|2.386|
|E1|4.70|||
|H|9.80|10.10|10.40|
|L|1.40|1.50|1.70|
|L1|2.90 REF|||
|L2|0.90||1.25|
|L3|0.51 BSC|||
|L4|0.60|0.80|1.00|
|L6|1.80 BSC|||
|Θ1|5°|7°|9°|
|Θ2|5°|7°|9°|
|V2|0°||8°|



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**Package information** 

## **Figure 22. DPAK footprint[(a)]** 

**==> picture [405 x 348] intentionally omitted <==**

**----- Start of picture text -----**<br>
�����������<br>**----- End of picture text -----**<br>


- a. All dimensions are in millimeters 

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**STD7N65M2** 

**Packaging mechanical data** 

## **5 Packaging mechanical data** 

## **Figure 23. Tape for DPAK (TO-252)** 

**==> picture [399 x 316] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 pitches cumulative<br>tolerance on tape +/- 0.2 mm<br>Top cover P0 D P2<br>T tape<br>E<br>F<br>K0 W<br>B1 B0<br>A) | Tl IRIE Co<br>For machine ref. only A0 P1 D1<br>including draft and<br>radii concentric around B0 SS»<br>User direction of feed<br>R<br>ol eh tel al fa l ta a<br>|» Bending radius<br>User direction of feed<br>AM08852v1<br>**----- End of picture text -----**<br>


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**Packaging mechanical data** 

## **Figure 24. Reel for DPAK (TO-252)** 

**==> picture [405 x 256] intentionally omitted <==**

**----- Start of picture text -----**<br>
T<br>REEL DIMENSIONS<br>40mm min.<br>Access hole<br>At slot location<br>B<br>D<br>C<br>N<br>A<br>Full radius Tape slot  G measured at hub<br>in core for<br>tape start 25 mm min.<br>width<br>AM08851v2<br>**----- End of picture text -----**<br>


**Table 11. DPAK (TO-252) tape and reel mechanical data** 

||**Tape**|**Tape**||**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Dim.**|**mm**<br>**Min.**<br>**Max.**||**Dim.**|**mm**||
||**Min.**|||**Min.**|**Max.**|
|A0|6.8|7|A||330|
|B0|10.4|10.6|B|1.5||
|B1||12.1|C|12.8|13.2|
|D|1.5|1.6|D|20.2||
|D1|1.5||G|16.4|18.4|
|E|1.65|1.85|N|50||
|F|7.4|7.6|T||22.4|
|K0|2.55|2.75||||
|P0|3.9|4.1||Base qty.|2500|
|P1|7.9|8.1||Bulk qty.|2500|
|P2|1.9|2.1<br>0.35<br>16.3||||
|R|40|||||
|T|0.25|||||
|W|15.7|||||



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**Revision history** 

## **6 Revision history** 

**Table 12. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|07-Aug-2014|1|First release.|
|06-May-2015|2|Document status promoted from preliminary to production data.<br>Updated_Section 4: Package information_.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2015 STMicroelectronics – All rights reserved 

DocID026787 Rev 2 

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## Links

- [View this product on Novapart](https://novapart.co/products/STD7N65M2/power-mosfet-n-channel-650-v-5-a-098-ohm-to-252)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/stmicroelectronics/std7n65m2/mosfet-n-channel-650v-5a-to-252/dp/2460390)
---

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