# Power MOSFET, N Channel, 1 kV, 2.2 A, 5.6 ohm, TO-252 (DPAK), Surface Mount

![Product image](https://novapart.co/image/farnell:3129804RL/)

**URL**: https://novapart.co/products/STD4NK100Z/power-mosfet-n-channel-1-kv-22-a-56-ohm-to-252
**SKU**: STD4NK100Z
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.9920
**Stock**: 1000+
**Lead Time**: 106 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:2.2A; Drain Source Voltage Vds:1kV; On Resistance Rds(on):5.6ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:3

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | SuperMESH |
| Qualification | AEC-Q101 |
| Power Dissipation | 90W |
| Transistor Mounting | Surface Mount |
| Transistor Polarity | N Channel |
| Power Dissipation Pd | 90W |
| Rds(On) Test Voltage | 10V |
| On Resistance Rds(On) | 5.6ohm |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 1kV |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 2.2A |
| Drain Source On State Resistance | 5.6ohm |
| Automotive Qualification Standard | AEC-Q101 |
| Gate Source Threshold Voltage Max | 3.75V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3129804RL/)

## **STD4NK100Z** 

Automotive-grade N-channel 1000 V, 5.6 Ω typ., 2.2 A SuperMESH™ Power MOSFET Zener-protected in a DPAK **Datasheet** - **production data** 

## **Features** 

|**Features**||||
|---|---|---|---|
|**Order code**|**VDSS**|**RDS(on)max**|**ID**|
|STD4NK100Z|1000 V|6.8Ω|2.2 A|



- Designed for automotive applications and AEC-Q101 qualified 

- Extremely high dv/dt capability 

- 100% avalanche tested 

- Gate charge minimized 

- Very low intrinsic capacitance 

- Zener-protected 

## **Figure 1. Internal schematic diagram** 

## **Applications** 

- Switching application 

## **Description** 

This device is an N-channel Zener-protected Power MOSFET developed using STMicroelectronics’ SuperMESH™ technology, achieved through optimization of ST’s well established strip-based PowerMESH™ layout. In addition to a significant reduction in onresistance, this device is designed to ensure a high level of dv/dt capability for the most demanding applications. 

**Table 1. Device summary** 

|**Order code**|**Marking**|**Package**|**Packaging**|
|---|---|---|---|
|STD4NK100Z|4NK100Z|DPAK|Tape and reel|



_Note: HTRB test has been performed at 80% of V(BR)DSS according to AEC-Q101 rev. C. All the other tests have been done according to the new rev. D._ 

April 2015 

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This is information on a product in full production. 

_www.st.com_ 

**Contents** 

**STD4NK100Z** 

## **Contents** 

|**1**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3**|
|---|---|
|**2**|**Electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4**|
||2.1<br>Electrical characteristics (curves)       . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**3**|**Test circuits     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8**|
|**4**|**Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9**|
|**5**|**Packing information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13**|
|**6**|**Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2. Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|1000|V|
|VGS|Gate-source voltage|± 30|V|
|ID|Drain current (continuous) at TC= 25 °C|2.2|A|
|ID|Drain current (continuous) at TC=100 °C|1|A|
|IDM<br>(1)|Drain current (pulsed)|8.8|A|
|PTOT|Total dissipation at TC= 25 °C|90|W|
|VESD(G-S)|Gate source ESD (HBM-C=100pF, R=1.5 kΩ)|3000|V|
|dv/dt<br>(2)|Peak diode recovery voltage slope|4.5|V/ns|
|TJ<br>Tstg|Operating junction temperature<br>Storage temperature|-55 to 150|°C|



1. Pulse width limited by safe operating area 

2. ISD ≤ 2.2 A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. 

**Table 3. Thermal data** 

||**Table 3. Thermal data**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|Rthj-case|Thermal resistance junction-case max|1.39|°C/W|
|Rthj-pcb<br>(1)|Thermal resistance junction-pcb max|50|°C/W|



1. When mounted on 1inch² FR-4 board, 2 oz Cu 

**Table 4. Avalanche characteristics** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|IAR|Avalanche current, repetitive or not-repetitive<br>(pulse width limited by TJMAX)|2.2|A|
|EAS|Single pulse avalanche energy<br>(starting TJ=25 °C, ID=IAR, VDD=50 V)|110|mJ|



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**Electrical characteristics** 

## **2 Electrical characteristics** 

(TCASE=25 °C unless otherwise specified) 

**Table 5. On/off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|ID= 1 mA, VGS= 0|1000|||V|
|IDSS|Zero gate voltage drain<br>current (VGS= 0)|VDS= 1000 V,<br>VDS= 1000 V, Tc = 125 °C|||1<br>50|µA<br>µA|
|IGSS|Gate body leakage current<br>(VGS= 0)|VGS= ± 20 V|||±10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 50 µA|3|3.75|4.5|V|
|RDS(on)|Static drain-source<br>on-resistance|VGS= 10 V, ID =1.1 A||5.6|6.8|Ω|



**Table 6. Dynamic** 

|||**Table 6. Dynamic**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|Ciss|Input capacitance||-|601|-|pF|
|Coss|Output capacitance|VDS=25 V, f=1 MHz,<br>VGS=0|-|53|-|pF|
|Crss|Reverse transfer<br>capacitance||-|12|-|pF|
|Coss. eq<br>(1)|Equivalent output<br>capacitance|VGS=0, VDS=0 V to 800 V|-|15|-|pF|
|td(on)|Turn-on delay time|VDD=500 V, ID= 1.25 A,<br>RG=4.7Ω,VGS=10 V<br>(see_Figure 16_)|-|15|-|ns|
|tr|Rise time||-|7.5|-|ns|
|td(off)|Off-voltage rise time||-|32|-|ns|
|tf|Fall time||-|39|-|ns|
|Qg|Total gate charge|VDD=800 V, ID= 2.5 A<br>VGS=10 V<br>(see_Figure 15_)|-|18|-|nC|
|Qgs|Gate-source charge||-|3.6|-|nC|
|Qgd|Gate-drain charge||-|9.2|-|nC|



1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 

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**Electrical characteristics** 

**Table 7. Source drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||2.2|A|
|ISDM<br>(1)|Source-drain current (pulsed)||-||8.8|A|
|VSD<br>(2)|Forward on voltage|ISD= 2.2 A, VGS=0|-||1.6|V|
|trr|Reverse recovery time|ISD= 2.5 A,<br>di/dt = 100 A/µs,<br>VDD=100 V<br>(see_Figure 14_)|-|584||ns|
|Qrr|Reverse recovery charge||-|2.3||µC|
|IRRM|Reverse recovery current||-|8||A|
|trr|Reverse recovery time|ISD= 2.5 A,<br>di/dt = 100 A/µs,<br>VDD=100 V, Tj=150 °C<br>(see_Figure 14_)|-|628||ns|
|Qrr|Reverse recovery charge||-|2.5||µC|
|IRRM|Reverse recovery current||-|8.1||A|



1. Pulse width limited by safe operating area 

2. Pulsed: pulse duration=300 µs, duty cycle 1.5% 

**Table 8. Gate-source Zener diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)GSO|Gate-source breakdown voltage|Igs=± 1 mA, ID=0|30|-||V|



The built-in back-to-back Zener diodes have specifically been designed to enhance the device's ESD capability. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components. 

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**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2. Safe operating area** 

## **Figure 3. Thermal impedance** 

## **Figure 4. Output characteristics** 

## **Figure 5. Transfer characteristics** 

## **Figure 6. Normalized V(BR)DSS vs. temperature** 

**Figure 7. Static drain-source on-resistance** 

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**Electrical characteristics** 

**Figure 8. Gate charge vs. gate-source voltage** 

**==> picture [166 x 153] intentionally omitted <==**

**Figure 10. Normalized gate threshold voltage vs. temperature** 

**==> picture [169 x 153] intentionally omitted <==**

**Figure 12. Source-drain diode forward characteristics** 

**==> picture [165 x 154] intentionally omitted <==**

**Figure 9. Capacitance variations** 

**==> picture [166 x 153] intentionally omitted <==**

**Figure 11. Normalized on-resistance vs. temperature** 

**==> picture [166 x 153] intentionally omitted <==**

**Figure 13. Maximum avalanche energy vs Tj** 

**==> picture [161 x 152] intentionally omitted <==**

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**STD4NK100Z** 

**Test circuits** 

## **3 Test circuits** 

**Figure 14. Switching times test circuit for resistive load** 

**Figure 15. Gate charge test circuit** 

**==> picture [463 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>12V 47kΩ<br>1kΩ<br>100nF<br>RL 2200 3.3<br>μF μF<br>VDD IG=CONST<br>VD Vi=20V=VGMAX 100Ω D.U.T.<br>VGS<br>2200<br>RG D.U.T. μF 2.7kΩ VG<br>PW<br>47kΩ<br>1kΩ<br>PW<br>AM01468v1 AM01469v1<br>**----- End of picture text -----**<br>


**Figure 16. Test circuit for inductive load switching and diode recovery times** 

**Figure 17. Unclamped inductive load test circuit** 

**==> picture [463 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
L<br>A A A<br>D<br>FAST L=100μH VD<br>G D.U.T. DIODE 2200 3.3<br>S B 3.3 1000 μF μF VDD<br>25 Ω B B D μF μF VDD ID<br>G<br>RG S<br>Vi D.U.T.<br>Pw<br>AM01470v1 AM01471v1<br>**----- End of picture text -----**<br>


## **Figure 18. Unclamped inductive waveform** 

## **Figure 19. Switching time waveform** 

**==> picture [463 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
V(BR)DSS ton toff<br>VD tdon tr tdoff tf<br>90% 90%<br>IDM<br>10%<br>ID 0 10% VDS<br>VDD VDD 90%<br>VGS<br>AM01472v1 0 10% AM01473v1<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 

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**Package information** 

## **Figure 20. DPAK (TO-252) type A2 outline** 

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**Package information** 

**Table 9. DPAK (TO-252) type A2 mechanical data** 

||**Table 9. DPAK(TO-252) type A2 mechanical data**|**Table 9. DPAK(TO-252) type A2 mechanical data**|**Table 9. DPAK(TO-252) type A2 mechanical data**|
|---|---|---|---|
|**Dim.**|**mm**|||
||**Min.**|**Typ.**|**Max.**|
|A|2.20||2.40|
|A1|0.90||1.10|
|A2|0.03||0.23|
|b|0.64||0.90|
|b4|5.20||5.40|
|c|0.45||0.60|
|c2|0.48||0.60|
|D|6.00||6.20|
|D1|4.95|5.10|5.25|
|E|6.40||6.60|
|E1|5.10|5.20|5.30|
|e|2.16|2.28|2.40|
|e1|4.40||4.60|
|H|9.35||10.10|
|L|1.00||1.50|
|L1|2.60|2.80|3.00|
|L2|0.65|0.80|0.95|
|L4|0.60||1.00|
|R||0.20||
|V2|0°||8°|



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**Package information** 

## **Figure 21. DPAK (TO-252) footprint[(a)]** 

- a. All dimensions are in millimeters 

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**Packing information** 

## **5 Packing information** 

**Table 10. DPAK (TO-252) tape and reel mechanical data** 

||**Tape**|**Tape**||**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Dim.**|**mm**||**Dim.**|**mm**||
||**Min.**|**Max.**||**Min.**|**Max.**|
|A0|6.8|7|A||330|
|B0|10.4|10.6|B|1.5||
|B1||12.1|C|12.8|13.2|
|D|1.5|1.6|D|20.2||
|D1|1.5||G|16.4|18.4|
|E|1.65|1.85|N|50||
|F|7.4|7.6|T||22.4|
|K0|2.55|2.75||||
|P0|3.9|4.1||Base qty.|2500|
|P1|7.9|8.1||Bulk qty.|2500|
|P2|1.9|2.1||||
|R|40|||||
|T|0.25|0.35||||
|W|15.7|16.3||||



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**Packing information** 

## **Figure 22. Tape for DPAK (TO-252)** 

**==> picture [390 x 297] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 pitches cumulative<br>tolerance on tape +/- 0.2 mm<br>Top cover P0 D P2<br>T tape<br>E<br>J / 000 one al o 00<br>F<br>K0 W<br>B1 B0<br>A R EI IEIES<br>For machine ref. only A0 P1 D1<br>including draft and<br>radii concentric around B0 —<br>User direction of feed<br>R<br>SbabSRE<br>Bending radius<br>User direction of feed<br>**----- End of picture text -----**<br>


**==> picture [39 x 6] intentionally omitted <==**

**----- Start of picture text -----**<br>
AM08852v1<br>**----- End of picture text -----**<br>


## **Figure 23. Reel for DPAK (TO-252)** 

**==> picture [377 x 249] intentionally omitted <==**

**----- Start of picture text -----**<br>
T<br>REEL DIMENSIONS<br>40mm min.<br>Access hole<br>At sl ot location<br>B<br>D<br>C<br>N<br>A<br>Full radius Tape slot  G measured at hub<br>in core for<br>tape start 25 mm min.<br>width<br>AM08851v2<br>**----- End of picture text -----**<br>


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**Revision history** 

## **6 Revision history** 

## **Table 11. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|01-Oct-2013|1|First release.|
|13-Apr-2015|2|Document status promoted from preliminary to production data.<br>Updated title and features in cover page.<br>Updated_Section 2.1: Electrical characteristics (curves)_and<br>_Section 4: Package information_.<br>Minor text changes.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2015 STMicroelectronics – All rights reserved 

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## Links

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- [Supplier page](https://es.farnell.com/stmicroelectronics/std4nk100z/mosfet-aecq101-n-ch-1kv-2-2a-to/dp/3129804RL)
---

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