# Power MOSFET, P Channel, 40 V, 50 A, 0.012 ohm, TO-252 (DPAK), Surface Mount

![Product image](https://novapart.co/image/farnell:3129906/)

**URL**: https://novapart.co/products/STD45P4LLF6AG/power-mosfet-p-channel-40-v-50-a-0012-ohm-to-252
**SKU**: STD45P4LLF6AG
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.4730
**Stock**: 1000+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:P Channel; Continuous Drain Current Id:-50A; Drain Source Voltage Vds:-40V; On Resistance Rds(on):0.012ohm; Rds(on) Test Voltage Vgs:-10V; Threshold Voltage V

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | P Channel |
| Product Range | STripFET F6 |
| Qualification | AEC-Q101 |
| Power Dissipation | 58W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 40V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 50A |
| Drain Source On State Resistance | 0.012ohm |
| Gate Source Threshold Voltage Max | 2.5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3129906/)

## **STD45P4LLF6AG** 

Automotive-grade P-channel -40 V, 12 mΩ typ., -50 A STripFET™ F6 Power MOSFET in a DPAK package 

Datasheet - production data 

## **Features** 

|**Order code**|**VDS**|**RDS(on) max.**|**ID**|
|---|---|---|---|
|STD45P4LLF6AG|-40 V|15 mΩ|-50 A|



- Designed for automotive applications and AEC-Q101 qualified 

- Very low on-resistance 

- Very low gate charge 

- High avalanche ruggedness 

**Figure 1: Internal schematic diagram** 

- Low gate drive power loss 

**==> picture [473 x 213] intentionally omitted <==**

**----- Start of picture text -----**<br>
D(2, TAB)<br>Applications<br> Switching applications<br>Description<br>This device is a P-channel Power MOSFET<br>G(1) developed using the STripFET™ F6 technology,<br>with a new trench gate structure. The resulting<br>Power MOSFET exhibits very low RDS(on) in all<br>packages.<br>S(3)<br>AM11258v1<br>Table 1: Device summary<br>Order code  Marking  Package  Packing<br>$+ STD45P4LLF6AG  45P4LLF6  DPAK  Tape and reel<br>**----- End of picture text -----**<br>


This is information on a product in full production. 

July 2015 

DocID027807 Rev 2 

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_www.st.com_ 

**Contents** 

**STD45P4LLF6AG** 

|**Contents**<br>**STD45P4LLF6AG**|**Contents**<br>**STD45P4LLF6AG**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>DPAK (TO-252) type A2 package information................................. 10|
||4.2<br>DPAK (TO-252) packing information ............................................... 13|
|**5**|**Revision history ............................................................................ 15**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|-40|V|
|VGS|Gate-source voltage|±18 V|V|
|ID|Drain current (continuous) at Tcase= 25 °C|-50|A|
||Drain current (continuous) at Tcase= 100 °C|-31||
|IDM_(1)_|Drain current (pulsed)|-200|A|
|PTOT|Total dissipation at Tcase= 25 °C|58|W|
|EAS_(2)_|Singlepulse avalanche energy|160|mJ|
|Tstg|Storage temperature|–55 to 150|°C|
|Tj_(3)_|Operating junction temperature|||



## **Notes:** 

- (1) Pulse width is limited by safe operating area. 

(2) starting Tj = 25 °C, RG = 47 Ω, ID(min) = -25 A. 

(3) HTRB performed at Tj = 175 °C, VDS = 100% V(BR)DSS. 

**Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case|2.14|°C/W|
|Rthj-amb|Thermal resistancejunction-ambient|50||



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**Electrical characteristics** 

## **2 Electrical characteristics** 

(Tcase = 25 °C unless otherwise specified) 

**Table 4: Static** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|VGS= 0 V, ID= -250 µA|-40|||V|
|IDSS|Zero gate voltage drain<br>current|VGS= 0 V, VDS= -40 V|||-1|µA|
|||VGS= 0 V, VDS= -40 V,<br>Tcase= 125 °C|||-10||
|IGSS|Gate-bodyleakage current|VDS= 0 V, VGS= -18 V|||-100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= -250µA|-1||-2.5|V|
|RDS(on)|Static drain-source on-<br>resistance|VGS= -10 V, ID= -25 A||12|15|mΩ|
|||VGS= -4.5 V, ID= -25 A||17|20||



## **Table 5: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= -25 V, f = 1 MHz,<br>VGS= 0 V|-|3525|-|pF|
|Coss|Output capacitance||-|345|-||
|Crss|Reverse transfer<br>capacitance||-|240|-||
|Qg|Totalgate charge|VDD= -20 V, ID= -50 A,<br>VGS= -10 V (see_Figure 14:_<br>_"Gate charge test circuit"_)|-|65.5|-|nC|
|Qgs|Gate-source charge||-|11.5|-||
|Qgd|Gate-drain charge||-|13|-||



## **Table 6: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDD= -20 V, ID= -25 A<br>RG= 4.7 Ω, VGS= -10 V (see<br>_Figure 13: "Switching times test_<br>_circuit for resistive load"_)|-|12|-|ns|
|tr|Rise time||-|35.5|-||
|td(off)|Turn-off delaytime||-|63.5|-||
|tf|Fall time||-|31|-||



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**Electrical characteristics** 

||**Table 7: Source-drain diode**|**Table 7: Source-drain diode**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|ISD|Source-drain current||-||-50|A|
|ISDM_(1)_|Source-drain current<br>(pulsed)||-||-200|A|
|VSD_(2)_|Forward on voltage|VGS= 0 V, ISD= -50 A|-||-1.3|V|
|trr|Reverse recoverytime|ISD= -50 A, di/dt = -100 A/µs,<br>VDD= -32 V (see_Figure 15: "Test_<br>_circuit for inductive load_<br>_switching and diode recovery_<br>_times"_)|-|27.5||ns|
|Qrr|Reverse recovery<br>charge||-|24.5||nC|
|IRRM|Reverse recovery<br>current||-|-1.8||A|



## **Notes:** 

(1) Pulse width is limited by safe operating area. 

(2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. 

DocID027807 Rev 2 

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**Electrical characteristics STD45P4LLF6AG 2.1 Electrical characteristics (curves)** 

**==> picture [386 x 168] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 2: Safe operating area  Figure 3: Thermal impedance<br>**----- End of picture text -----**<br>


**Figure 4: Output characteristics Figure 5: Transfer characteristics** 

**==> picture [156 x 142] intentionally omitted <==**

**==> picture [157 x 142] intentionally omitted <==**

**Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance** 

**==> picture [161 x 143] intentionally omitted <==**

**==> picture [162 x 143] intentionally omitted <==**

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**Electrical characteristics** 

**==> picture [375 x 20] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 9: Normalized gate threshold voltage<br>Figure 8: Capacitance variations<br>vs temperature<br>**----- End of picture text -----**<br>


**==> picture [371 x 20] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 10: Normalized on-resistance vs  Figure 11: Normalized V(BR)DSS vs<br>temperature  temperature<br>**----- End of picture text -----**<br>


**Figure 12: Source-drain diode forward characteristics** 

For the P-channel Power MOSFET, current and voltage polarities are reversed. 

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**Test circuits** 

## **3 Test circuits** 

**==> picture [401 x 172] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 13: Switching times test circuit for<br>Figure 14: Gate charge test circuit<br>resistive load<br>**----- End of picture text -----**<br>


**Figure 15: Test circuit for inductive load switching and diode recovery times** 

**==> picture [215 x 126] intentionally omitted <==**

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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

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**Package information** 

## **4.1 DPAK (TO-252) type A2 package information** 

**Figure 16: DPAK (TO-252) type A2 package outline** 

**==> picture [407 x 551] intentionally omitted <==**

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**Package information** 

**Table 8: DPAK (TO-252) type A2 mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|2.20||2.40|
|A1|0.90||1.10|
|A2|0.03||0.23|
|b|0.64||0.90|
|b4|5.20||5.40|
|c|0.45||0.60|
|c2|0.48||0.60|
|D|6.00||6.20|
|D1|4.95|5.10|5.25|
|E|6.40||6.60|
|E1|5.10|5.20|5.30|
|e|2.16|2.28|2.40|
|e1|4.40||4.60|
|H|9.35||10.10|
|L|1.00||1.50|
|L1|2.60|2.80|3.00|
|L2|0.65|0.80|0.95|
|L4|0.60||1.00|
|R||0.20||
|V2|0°||8°|



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**Package information** 

**Figure 17: DPAK (TO-252) recommended footprint (dimensions are in mm)** 

**==> picture [329 x 281] intentionally omitted <==**

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**Package information** 

## **4.2 DPAK (TO-252) packing information** 

**Figure 18: DPAK (TO-252) tape outline** 

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**STD45P4LLF6AG** 

**Package information** 

**Figure 19: DPAK (TO-252) reel outline** 

**Table 9: DPAK (TO-252) tape and reel mechanical data** 

|**Tape**|**Tape**|**Tape**|**Reel**|**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Dim.**|**mm**||**Dim.**|**mm**||
||**Min.**|**Max.**||**Min.**|**Max.**|
|A0|6.8|7|A||330|
|B0|10.4|10.6|B|1.5||
|B1||12.1|C|12.8|13.2|
|D|1.5|1.6|D|20.2||
|D1|1.5||G|16.4|18.4|
|E|1.65|1.85|N|50||
|F|7.4|7.6|T||22.4|
|K0|2.55|2.75||||
|P0|3.9|4.1|Baseqty.||2500|
|P1|7.9|8.1|Bulkqty.||2500|
|P2|1.9|2.1||||
|R|40|||||
|T|0.25|0.35||||
|W|15.7|16.3||||



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**Revision history** 

## **5 Revision history** 

**Table 10: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|28-Apr-2015|1|First release.|
|22-Jul-2015|2|Modified: VGSvalues in absoute maximum ratings table and static table.<br>Updated: DPAK (TO-252) type A2 package information section updated.<br>Minor text changes.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2015 STMicroelectronics – All rights reserved 

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- [Supplier page](https://es.farnell.com/stmicroelectronics/std45p4llf6ag/mosfet-aecq101-p-ch-40v-50a-to252/dp/3129906)
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