# Power MOSFET, P Channel, 80 V, 40 A, 0.0185 ohm, TO-252 (DPAK), Surface Mount

![Product image](https://novapart.co/image/farnell:3367023/)

**URL**: https://novapart.co/products/STD40P8F6AG/power-mosfet-p-channel-80-v-40-a-00185-ohm-to-252
**SKU**: STD40P8F6AG
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.6400
**Stock**: 200+
**Lead Time**: 127 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | P Channel |
| Product Range | STripFET F6 |
| Qualification | AEC-Q101 |
| Power Dissipation | 100W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 80V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 40A |
| Drain Source On State Resistance | 0.0185ohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3367023/)

## **STD40P8F6AG** 

## Automotive-grade P-channel -80 V, 18.5 mΩ typ., -40 A STripFET™ F6 Power MOSFET in a DPAK package 

Datasheet - production data 

## **Features** 

|**Order code**|**VDSS**|**RDS(on) max.**|**ID**|
|---|---|---|---|
|STD40P8F6AG|-80 V|28 mΩ|-40 A|



- Designed for automotive applications and AEC-Q101 qualified 

- Very low on-resistance 

- Very low gate charge 

- High avalanche ruggedness 

**Figure 1: Internal schematic diagram** 

- Low gate drive power loss 

D(2, TAB) **Applications**  Switching applications **Description** This device is a P-channel Power MOSFET G(1) developed using the STripFET™ F6 technology, with a new trench gate structure. The resulting Power MOSFET exhibits very low RDS(on) in all packages. S(3) AM11258v1 **Table 1: Device summary Order code Marking Package Packing** ~~$$$~~ STD40P8F6AG 40P8F6 DPAK Tape and reel ~~—-~~ 

This is information on a product in full production. 

July 2016 

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_www.st.com_ 

|**Contents**<br>**STD40P8F6AG**|**Contents**<br>**STD40P8F6AG**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>DPAK type A2 package information ................................................ 10|
||4.2<br>DPAK packing information .............................................................. 13|
|**5**|**Revision history ............................................................................ 15**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|-80|V|
|VGS|Gate-source voltage|±20|V|
|ID|Drain current (continuous) at TC= 25 °C|-40|A|
|ID|Drain current (continuous) at TC= 100 °C|-28|A|
|IDM_(1)_|Drain current (pulsed)|-160|A|
|PTOT|Total dissipation at TC= 25 °C|100|W|
|EAS|Single pulse avalanche energy (starting TJ= 25 °C, ID= -40 A,<br>VDD= -60 V)|240|mJ|
|Tstg|Storage temperature range|-55 to 175|°C|
|Tj|Junction temperature range|||



## **Notes:** 

(1)Pulse width limited by safe operating area. 

**Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case max|1.5|°C/W|
|Rthj-pcb|Thermal resistance junction-pcb max_(1)_|50|°C/W|



## **Notes:** 

- (1)When mounted on 1 inch2 FR-4, 2 Oz copper board. 

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**Electrical characteristics** 

## **2 Electrical characteristics** 

(TC = 25 °C unless otherwise specified) 

**Table 4: Static** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|VGS= 0 V, ID= -1 mA|-80|||V|
|IDSS|Zero gate voltage Drain<br>current|VGS= 0 V, VDS= -60 V|||-1|µA|
|||VGS= 0 V, VDS= -60 V,<br>TC= 125 °C_(1)_|||-10|µA|
|IGSS|Gate-body leakage current|VDS= 0 V, VGS= ±20 V|||±100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= -250µA|-2||-4|V|
|RDS(on)|Static drain-source<br>on-resistance|VGS= -10 V, ID= -20 A||18.5|28|mΩ|



## **Notes:** 

(1)Defined by design, not subject to production test. 

## **Table 5: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= -25 V, f = 1 MHz,<br>VGS= 0 V|-|4112|-|pF|
|Coss|Output capacitance||-|366|-|pF|
|Crss|Reverse transfer<br>capacitance||-|188|-|pF|
|Qg|Totalgate charge|VDD= -40 V, ID= -40 A,<br>VGS= -10 V (see_Figure 14:_<br>_"Gate charge test circuit"_)|-|73|-|nC|
|Qgs|Gate-source charge||-|17.1|-|nC|
|Qgd|Gate-drain charge||-|18|-|nC|



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**Electrical characteristics** 

|||**Table 6: Switching times**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|td(on)|Turn-on delaytime|VDD= -40 V, ID= -20 A, RG= 4.7 Ω,<br>VGS= -10 V (see_Figure 13:_<br>_"Switching times test circuit for_<br>_resistive load"_)|-|17.5|-|ns|
|tr|Rise time||-|28.5|-|ns|
|td(off)|Turn-off-delaytime||-|68.5|-|ns|
|tf|Fall time||-|34.5|-|ns|



**Table 7: Source drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||-40|A|
|ISDM_(1)_|Source-drain current<br>(pulsed)||-||-160|A|
|VSD_(2)_|Forward on voltage|VGS= 0 V, ISD= -40 A|-||-1.2|V|
|trr|Reverse recovery<br>time|ISD= -40 A, di/dt = 100 A/µs,<br>VDD= -64 V, (see_Figure 15: "Test_<br>_circuit for inductive load switching_<br>_and diode recovery times"_)|-|35||ns|
|Qrr|Reverse recovery<br>charge||-|44||nC|
|IRRM|Reverse recovery<br>current||-|-2.5||A|



## **Notes:** 

(1)Pulse width limited by safe operating area. 

(2)Pulse test: pulse duration = 300 µs, duty cycle 1.5%. 

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**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

For the P-channel Power MOSFET, current and voltage polarities are reversed. 

**==> picture [335 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 2: Safe operating area  Figure 3: Thermal impedance<br>**----- End of picture text -----**<br>


**==> picture [350 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 4: Output characteristics  Figure 5: Transfer characteristics<br>**----- End of picture text -----**<br>


**Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance** 

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**Electrical characteristics** 

**==> picture [385 x 168] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 8: Capacitance variations  Figure 9: Normalized V(BR)DSS vs temperature<br>**----- End of picture text -----**<br>


**==> picture [409 x 180] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 10: Normalized gate threshold voltage  Figure 11: Normalized on-resistance vs<br>vs temperature  temperature<br>**----- End of picture text -----**<br>


**Figure 12: Source-drain diode forward characteristics** 

**==> picture [181 x 166] intentionally omitted <==**

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**Test circuits** 

## **3 Test circuits** 

**==> picture [401 x 172] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 13: Switching times test circuit for<br>Figure 14: Gate charge test circuit<br>resistive load<br>**----- End of picture text -----**<br>


**Figure 15: Test circuit for inductive load switching and diode recovery times** 

**==> picture [215 x 126] intentionally omitted <==**

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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

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**Package information** 

## **4.1 DPAK type A2 package information** 

**==> picture [219 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 16: DPAK (TO-252) type A2 package outline<br>**----- End of picture text -----**<br>


**==> picture [406 x 561] intentionally omitted <==**

**----- Start of picture text -----**<br>
0068772_type-A2_rev21<br>**----- End of picture text -----**<br>


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**Package information** 

**Table 8: DPAK (TO-252) type A2 mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|2.20||2.40|
|A1|0.90||1.10|
|A2|0.03||0.23|
|b|0.64||0.90|
|b4|5.20||5.40|
|c|0.45||0.60|
|c2|0.48||0.60|
|D|6.00||6.20|
|D1|4.95|5.10|5.25|
|E|6.40||6.60|
|E1|5.10|5.20|5.30|
|e|2.16|2.28|2.40|
|e1|4.40||4.60|
|H|9.35||10.10|
|L|1.00||1.50|
|L1|2.60|2.80|3.00|
|L2|0.65|0.80|0.95|
|L4|0.60||1.00|
|R||0.20||
|V2|0°||8°|



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**Package information** 

**Figure 17: DPAK (TO-252) recommended footprint (dimensions are in mm)** 

**==> picture [407 x 273] intentionally omitted <==**

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**Package information** 

## **4.2 DPAK packing information** 

**Figure 18: DPAK (TO-252) tape outline** 

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**Package information** 

**Figure 19: DPAK (TO-252) reel outline** 

**Table 9: DPAK (TO-252) tape and reel mechanical data** 

|**Tape**|**Tape**|**Tape**|**Reel**|**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Dim.**|**mm**||**Dim.**|**mm**||
||**Min.**|**Max.**||**Min.**|**Max.**|
|A0|6.8|7|A||330|
|B0|10.4|10.6|B|1.5||
|B1||12.1|C|12.8|13.2|
|D|1.5|1.6|D|20.2||
|D1|1.5||G|16.4|18.4|
|E|1.65|1.85|N|50||
|F|7.4|7.6|T||22.4|
|K0|2.55|2.75||||
|P0|3.9|4.1|Baseqty.||2500|
|P1|7.9|8.1|Bulkqty.||2500|
|P2|1.9|2.1||||
|R|40|||||
|T|0.25|0.35||||
|W|15.7|16.3||||



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**Revision history** 

## **5 Revision history** 

**Table 10: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|19-Jul-2016|1|First release.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2016 STMicroelectronics – All rights reserved 

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## Links

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- [Supplier page](https://es.farnell.com/stmicroelectronics/std40p8f6ag/mosfet-aec-q101-p-ch-80v-40a-100w/dp/3367023)
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