# Power MOSFET, P Channel, 60 V, 35 A, 0.028 ohm, TO-252 (DPAK), Surface Mount

![Product image](https://novapart.co/image/farnell:2807190/)

**URL**: https://novapart.co/products/STD35P6LLF6/power-mosfet-p-channel-60-v-35-a-0028-ohm-to-252
**SKU**: STD35P6LLF6
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.5270
**Stock**: 1000+
**Lead Time**: 132 days (indicative)

## Description

Transistor Polarity:P Channel; Continuous Drain Current Id:-35A; Drain Source Voltage Vds:-60V; On Resistance Rds(on):0.025ohm; Rds(on) Test Voltage Vgs:-10V; Threshold Voltage Vgs:-2.5V

## Specifications

| Parameter | Value |
|---|---|
| Msl | - |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | P Channel |
| Product Range | STripFET F6 |
| Qualification | - |
| Power Dissipation | 70W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 60V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 35A |
| Drain Source On State Resistance | 0.028ohm |
| Gate Source Threshold Voltage Max | 2.5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2807190/)

## **STD35P6LLF6** 

P-channel 60 V, 0.025 Ω typ., 35 A STripFET™ F6 Power MOSFET in a DPAK package 

Datasheet - production data 

## **Features** 

|**Order code**|**VDSS**|**RDS(on) max.**|**ID**|**PTOT**|
|---|---|---|---|---|
|STD35P6LLF6|60 V|0.028 Ω|35 A|70 W|



- Very low on-resistance 

- Very low gate charge 

- High avalanche ruggedness 

- Low gate drive power loss 

**Figure 1: Internal schematic diagram** 

## **Applications** 

- Switching applications 

D(2, TAB)  Switching applications **Description** This device is a P-channel Power MOSFET developed using the STripFET™ F6 technology, with a new trench gate structure. The resulting Power MOSFET exhibits very low RDS(on)DS(on) in all G(1) packages. S(3) AM11258v1 **Table 1: Device summary Order code Marking Package Packaging** STD35P6LLF6 35P6LLF6 DPAK Tape and Reel ~~$$ 1]~~ April 2017 DocID025600 Rev 3 This is information on a product in full production. 

This device is a P-channel Power MOSFET developed using the STripFET™ F6 technology, with a new trench gate structure. The resulting Power MOSFET exhibits very low RDS(on)DS(on) in all packages. 

_www.st.com_ 

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|**Contents**<br>**STD35P6LLF6**|**Contents**<br>**STD35P6LLF6**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>DPAK package information ............................................................. 10|
||4.2<br>Packing information ......................................................................... 13|
|**5**|**Revision history ............................................................................ 15**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|60|V|
|VGS|Gate-source voltage|± 20|V|
|ID|Drain current (continuous) at TC= 25 °C|35|A|
|ID|Drain current (continuous) at TC= 100 °C|25|A|
|IDM_(1)_|Drain current (pulsed)|140|A|
|PTOT|Total dissipation at TC= 25 °C|70|W|
|Tstg|Storage temperature range|-55 to 175|°C|
|Tj|Operating junction temperature range|||



**==> picture [32 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
Notes:<br>**----- End of picture text -----**<br>


(1)Pulse width limited by safe operating area. 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case max|2.14|°C/W|



For the P-channel Power MOSFET, current polarity of voltages and current have to be reversed. 

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**STD35P6LLF6** 

**Electrical characteristics** 

## **2 Electrical characteristics** 

(TC = 25 °C unless otherwise specified) 

**Table 4: Static** 

|**Symbol**<br>~~a~~|**Parameter**<br>~~a~~<br>~~a~~|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS<br>~~a~~|Drain-source breakdown<br>voltage<br>~~aee~~|VGS= 0 V, ID= 250 µA<br>~~ee~~|60<br>~~ee~~|~~ee~~|~~ee~~|V<br>~~ee~~|
|IDSS<br>~~a~~<br>~~pf~~|Zero gate voltage Drain<br>current<br>~~aee~~<br>~~pf~~<br>~~ee~~|VGS= 0 V, VDS= 60 V<br>~~ee~~|~~ee~~<br>~~oan~~|~~ee~~<br>~~oan~~|1<br>~~ee~~<br>~~oan~~|µA<br>~~ee~~<br>~~oan~~|
|||VGS= 0 V, VDS= 60 V,<br>TC= 125 °C_(1)_<br>~~ee~~<br>~~ee~~|~~oan~~<br>~~ee ee~~<br>~~ee~~|~~oan~~<br>~~ee~~<br>~~ee~~|10<br>~~oan~~<br>~~ee~~<br>~~ee~~|µA<br>~~oan~~<br>~~ee~~<br>~~ee~~|
|IGSS<br>~~pf~~<br>~~ee~~|Gate-body leakage<br>current<br>~~pf~~<br>~~ee~~<br>~~ee~~|VDS= 0 V, VGS= ± 20 V<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~oan~~<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|~~oan~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|±100<br>~~oan~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|nA<br>~~oan~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|VGS(th)<br>~~a~~|Gate threshold voltage<br>~~a~~|VDS= VGS, ID= 250µA<br>~~ee ~~<br>~~a~~|1<br> ~~ee~~<br>~~a~~|~~ee~~<br>~~a~~|2.5<br>~~ee~~<br>~~a~~|V<br>~~ee~~<br>~~a~~|
|RDS(on)|Static drain-source on-<br>resistance<br>~~ee~~|VGS= 10 V, ID= 17.5 A||0.025|0.028|Ω|
|||VGS= 4.5 V, ID= 17.5 A<br>~~ee~~|~~ee~~|0.03<br>~~ee~~|0.036<br>~~ee~~||



## **Notes:** 

(1)Defined by design, not subject to production test. 

**Table 5: Dynamic** 

|**Symbol**<br>~~PO~~|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss<br>~~PO~~<br>~~a~~|Input capacitance|VDS= 25 V, f = 1 MHz,<br>VGS= 0 V<br>~~TT~~<br>~~|~~|-<br>~~TT~~|3780<br>~~TT~~|-<br>~~TT~~|pF<br>~~TT~~|
|Coss<br>~~a~~<br>~~a~~|Output capacitance<br>~~a~~||-<br>~~TT~~|262<br>~~TT~~|-<br>~~TT~~|pF<br>~~TT~~|
|Crss<br>~~Pf~~|Reverse transfer<br>capacitance<br>~~Pf~~||-<br>~~|~~|170<br>~~td~~|-<br>~~td~~|pF<br>~~td~~|
|Qg<br>~~Pf~~<br>~~te~~<br>~~-—~~|Total gate charge<br>~~Pf~~<br>~~te~~|VDD= 30 V, ID= 35 A,<br>VGS= 0 to 4.5 V (see_Figure_<br>_14: "Gate charge test circuit"_)<br>~~|~~<br>~~te~~<br>~~Se~~|-<br>~~| ~~<br>~~te~~<br>~~Se~~|30<br> ~~td~~<br>~~te~~<br>~~Se~~|-<br>~~td~~<br>~~te~~<br>~~Se~~|nC<br>~~td~~<br>~~te~~<br>~~Se~~|
|Qgs<br>~~te~~<br>~~-—~~|Gate-source charge<br>~~te~~||-<br>~~te~~<br>~~Se~~|10.8<br>~~te~~<br>~~Se~~|-<br>~~te~~<br>~~Se~~|nC<br>~~te~~<br>~~Se~~|
|Qgd<br>~~te~~<br>~~-—~~|Gate-drain charge<br>~~te~~||-<br>~~te~~<br>~~Se~~|10.5<br>~~te~~<br>~~Se~~|-<br>~~te~~<br>~~Se~~|nC<br>~~te~~<br>~~Se~~|
|RG|Gate input resistance|ID= 0 A, gate DC bias = 0 V,<br>f = 1 MHz, magnitude of<br>alternative signal = 20 mV|-|1.7|-|Ω|



**Table 6: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDD= 30 V, ID= 17.5 A<br>RG= 4.7 Ω, VGS= 10 V (see<br>_Figure 13: "Switching times_<br>_test circuit for resistive load"_)|-|51.4|-|ns|
|tr|Rise time||-|39|-|ns|
|td(off)|Turn-off-delay time||-|171|-|ns|
|tf|Fall time||-|21|-|ns|



For the P-channel Power MOSFET, current polarity of voltages and current have to be reversed. 

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**STD35P6LLF6** 

**Electrical characteristics** 

**Table 7: Source drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VSD_(1)_|Forward on voltage|VGS= 0 V, ISD= 35 A|-||1.5|V|
|trr|Reverse recoverytime|ISD= 35 A, di/dt = 100 A/µs,<br>VDD= 48 V, (see_Figure 15:_<br>_"Test circuit for inductive load_<br>_switching and diode recovery_<br>_times"_)|-|34||ns|
|Qrr|Reverse recoverycharge||-|48||nC|
|IRRM|Reverse recovery current||-|2.8||A|



## **Notes:** 

(1)Pulse test: pulse duration = 300 µs, duty cycle 1.5% 

For the P-channel Power MOSFET, current polarity of voltages and current have to be reversed. 

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**STD35P6LLF6** 

## **Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2: Safe operating area** 

**==> picture [171 x 158] intentionally omitted <==**

**Figure 3: Thermal impedance** 

**==> picture [154 x 153] intentionally omitted <==**

**Figure 4: Output characteristics** 

**==> picture [170 x 159] intentionally omitted <==**

**Figure 5: Transfer characteristics** 

**==> picture [170 x 160] intentionally omitted <==**

**==> picture [455 x 201] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 6: Normalized gate threshold voltage vs<br>Figure 7: Normalized V(BR)DSS vs temperature<br>temperature<br>**----- End of picture text -----**<br>


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**STD35P6LLF6** 

**Electrical characteristics** 

**==> picture [448 x 188] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 8: Static drain-source on-resistance  Figure 9: Normalized on-resistance vs. temperature<br>**----- End of picture text -----**<br>


**Figure 10: Gate charge vs gate-source voltage Figure 11: Capacitance variations voltage** 

**==> picture [170 x 161] intentionally omitted <==**

**==> picture [181 x 160] intentionally omitted <==**

**Figure 12: Source-drain diode forward characteristics** 

**==> picture [169 x 162] intentionally omitted <==**

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**Test circuits** 

## **3 Test circuits** 

**==> picture [401 x 172] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 13: Switching times test circuit for<br>Figure 14: Gate charge test circuit<br>resistive load<br>**----- End of picture text -----**<br>


**Figure 15: Test circuit for inductive load switching and diode recovery times** 

**==> picture [215 x 126] intentionally omitted <==**

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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

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**STD35P6LLF6** 

**Package information** 

## **4.1 DPAK package information** 

**==> picture [219 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 16: DPAK (TO-252) type A2 package outline<br>**----- End of picture text -----**<br>


**==> picture [406 x 561] intentionally omitted <==**

**----- Start of picture text -----**<br>
0068772_type-A2_rev21<br>**----- End of picture text -----**<br>


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**Package information** 

**Table 8: DPAK (TO-252) type A2 mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|2.20||2.40|
|A1|0.90||1.10|
|A2|0.03||0.23|
|b|0.64||0.90|
|b4|5.20||5.40|
|c|0.45||0.60|
|c2|0.48||0.60|
|D|6.00||6.20|
|D1|4.95|5.10|5.25|
|E|6.40||6.60|
|E1|5.10|5.20|5.30|
|e|2.16|2.28|2.40|
|e1|4.40||4.60|
|H|9.35||10.10|
|L|1.00||1.50|
|L1|2.60|2.80|3.00|
|L2|0.65|0.80|0.95|
|L4|0.60||1.00|
|R||0.20||
|V2|0°||8°|



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**Package information** 

**Figure 17: DPAK (TO-252) type A2 recommended footprint (dimensions are in mm)** 

**==> picture [407 x 273] intentionally omitted <==**

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**Package information** 

## **4.2 Packing information** 

**Figure 18: DPAK (TO-252) tape outline** 

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**Package information** 

**Figure 19: DPAK (TO-252) reel outline** 

**Table 9: DPAK (TO-252) tape and reel mechanical data** 

|**Tape**|**Tape**|**Tape**|**Reel**|**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Dim.**|**mm**||**Dim.**|**mm**||
||**Min.**|**Max.**||**Min.**|**Max.**|
|A0|6.8|7|A||330|
|B0|10.4|10.6|B|1.5||
|B1||12.1|C|12.8|13.2|
|D|1.5|1.6|D|20.2||
|D1|1.5||G|16.4|18.4|
|E|1.65|1.85|N|50||
|F|7.4|7.6|T||22.4|
|K0|2.55|2.75||||
|P0|3.9|4.1|Baseqty.||2500|
|P1|7.9|8.1|Bulkqty.||2500|
|P2|1.9|2.1||||
|R|40|||||
|T|0.25|0.35||||
|W|15.7|16.3||||



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**Revision history** 

## **5 Revision history** 

**Table 10: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|11-Dec-2013|1|First release.|
|24-Feb-2015|2|In title description on cover page, changed 0.02 Ω to 0.023 Ω<br>In features table on cover page, changed 0.028 Ω to 0.026 Ω<br>Updated Table 2: Absolute maximum ratings<br>Updated Table 4: Static – renamed table and updated Static<br>drainsource on-resistance values<br>Updated Table 5: Dynamic – test conditions and all typical values<br>Updated Table 6: Switching times – test conditions and all typical<br>values<br>Updated Table 7: Source-drain diode – test conditions and all<br>typical values<br>Added Section 2.2: Electrical characteristics (curves)<br>Updated Section 4: Package mechanical data Minor text changes|
|03-Apr-2017|3|Updated VSDmaximum value in_Table 7: "Source drain diode"_.<br>Updated_Section 4.1: "DPAK package information"_<br>Minor text changes.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2017 STMicroelectronics – All rights reserved 

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