# Power MOSFET, N Channel, 100 V, 32 A, 0.02 ohm, TO-252 (DPAK), Surface Mount

![Product image](https://novapart.co/image/farnell:3132724/)

**URL**: https://novapart.co/products/STD30N10F7/power-mosfet-n-channel-100-v-32-a-002-ohm-to-252
**SKU**: STD30N10F7
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.4970
**Stock**: 1000+
**Lead Time**: 2 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:32A; Drain Source Voltage Vds:100V; On Resistance Rds(on):0.0; Available until stocks are exhausted Alternative available

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (17-Dec-2015) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | STripFET F7 |
| Qualification | - |
| Power Dissipation | 50W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 100V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 32A |
| Drain Source On State Resistance | 0.02ohm |
| Gate Source Threshold Voltage Max | 4.5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3132724/)

## **STD30N10F7** 

N-channel 100 V, 0.02 Ω typ., 32 A, STripFET™ F7 Power MOSFET in a DPAK package 

Datasheet - production data 

## **Features** 

|**Order code**|**VDS**|**RDS(on) max.**|**ID**|**PTOT**|
|---|---|---|---|---|
|STD30N10F7|100 V|0.024 Ω|32 A|50 W|



- Among the lowest RDS(on) on the market 

- Excellent FoM (figure of merit) 

- Low Crss/Ciss ratio for EMI immunity 

- High avalanche ruggedness 

**Figure 1: Internal schematic diagram** 

## **Applications** 

- Switching applications 

**==> picture [60 x 114] intentionally omitted <==**

**----- Start of picture text -----**<br>
D(2, TAB)<br>G(1)<br>S(3)<br>**----- End of picture text -----**<br>


## **Description** 

This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low onstate resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. 

AM01475v1_noZen **Table 1: Device summary Order code Marking Package Packing** ~~<j~~ STD30N10F7 30N10F7 DPAK Tape and reel 

This is information on a product in full production. 

_www.st.com_ 

May 2017 

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|**Contents**<br>**STD30N10F7**|**Contents**<br>**STD30N10F7**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>DPAK (TO-252) type A package information..................................... 9|
||4.2<br>DPAK (TO-252) packing information ............................................... 12|
|**5**|**Revision history ............................................................................ 14**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|100|V|
|VGS|Gate-source voltage|±20|V|
|ID|Drain current (continuous) at TC= 25 °C|32|A|
||Drain current (continuous) at TC= 100 °C|23||
|IDM_(1)_|Drain current (pulsed) at TC= 25 °C|132|A|
|PTOT|Total dissipation at TC= 25 °C|50|W|
|TJ|Operating junction temperature range|-55 to 175|°C|
|Tstg|Storage temperature range||°C|



## **Notes:** 

- (1)Pulse width is limited by safe operating area 

**Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case|3|°C/W|
|Rthj-pcb_(1)_|Thermal resistancejunction-pcb|50||



## **Notes:** 

- (1)When mounted on a 1-inch² FR-4, 2 Oz copper board. 

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**Electrical characteristics** 

## **2 Electrical characteristics** 

(Tcase = 25 °C unless otherwise specified) 

**Table 4: Static** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|VGS= 0 V, ID= 250 μA|100|||V|
|IDSS|Zero gate voltage drain<br>current|VGS= 0 V, VDS= 100 V|||1|µA|
|||VGS= 0 V, VDS= 100 V,<br>TC= 125 °C_(1)_|||100||
|IGSS|Gate-body leakage<br>current|VDS= 0 V, VGS= ±20 V|||100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250µA|2.5||4.5|V|
|RDS(on)|Static drain-source<br>on-resistance|VGS= 10 V, ID= 16 A||0.02|0.024|Ω|



## **Notes:** 

(1)Defined by design, not subject to production test. 

**Table 5: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 50 V, f = 1 MHz, VGS= 0 V|-|1270|-|pF|
|Coss|Output capacitance||-|290|-|pF|
|Crss|Reverse transfer<br>capacitance||-|24|-|pF|
|Qg|Totalgate charge|VDD= 50 V, ID= 32 A,<br>VGS= 0 to 10 V<br>(see_Figure 14: "Test circuit for_<br>_gate charge behavior"_)|-|19|-|nC|
|Qgs|Gate-source charge||-|9|-|nC|
|Qgd|Gate-drain charge||-|4.5|-|nC|



**Table 6: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDD= 50 V, ID= 16 A,<br>RG= 4.7 Ω, VGS= 10 V<br>(see_Figure 13: "Test circuit for_<br>_resistive load switching times"_<br>and_Figure 18: "Switching time_<br>_waveform"_)|-|12|-|ns|
|tr|Rise time||-|17.5|-|ns|
|td(off)|Turn-off delaytime||-|22|-|ns|
|tf|Fall time||-|5.6|-|ns|



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**Electrical characteristics** 

**Table 7: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VSD_(1)_|Forward on voltage|VGS= 0 V, ISD= 32 A|-||1.1|V|
|trr|Reverse recoverytime|ISD= 32 A, di/dt = 100 A/µs,<br>VDD= 80 V, TJ= 150 °C<br>(see_Figure 15: "Test circuit for_<br>_inductive load switching and_<br>_diode recovery times"_)|-|41||ns|
|Qrr|Reverse recoverycharge||-|47||nC|
|IRRM|Reverse recovery current||-|2.3||A|



## **Notes:** 

(1)Pulsed: pulse duration = 300 µs, duty cycle 1.5% 

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## **Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 3: Thermal impedance** 

**==> picture [339 x 178] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 2: Safe operating area<br>ID AM16172v1 K<br>(A) d<br>0.2<br>100 Operation in this area is<br>limited by RDS(on) 0.1<br>0.05<br>0.02<br>10<br>100µs 10 A 0.01<br>1 Single pulse<br>1ms 107<br>10ms<br>0.1<br>Tj=175°C<br>Tc=25°C<br>Single pulse<br>0.01 10°<br>0.1 1 10 VDS(V) 10° 10% 10% 10%<br>**----- End of picture text -----**<br>


**Figure 4: Output characteristics** 

**Figure 5: Transfer characteristics** 

**Figure 6: Gate charge vs gate-source voltage** 

**Figure 7: Static drain-source on-resistance** 

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**Electrical characteristics** 

**Figure 8: Capacitance variations** 

**Figure 9: Normalized gate threshold voltage vs temperature** 

**Figure 10: Normalized on-resistance vs temperature** 

**Figure 11: Source-drain diode forward characteristics** 

**Figure 12: Normalized V(BR)DSS vs temperature** 

**==> picture [5 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
µ<br>**----- End of picture text -----**<br>


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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 375] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 13: Test circuit for resistive load  Figure 14: Test circuit for gate charge<br>switching times  behavior<br>Figure 15: Test circuit for inductive load  Figure 16: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>**----- End of picture text -----**<br>


**==> picture [403 x 170] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 17: Unclamped inductive waveform  Figure 18: Switching time waveform<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

## **4.1 DPAK (TO-252) type A package information** 

**Figure 19: DPAK (TO-252) type A package outline** 

**==> picture [408 x 315] intentionally omitted <==**

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**Package information** 

**Table 8: DPAK (TO-252) type A mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|2.20||2.40|
|A1|0.90||1.10|
|A2|0.03||0.23|
|b|0.64||0.90|
|b4|5.20||5.40|
|c|0.45||0.60|
|c2|0.48||0.60|
|D|6.00||6.20|
|D1|4.95|5.10|5.25|
|E|6.40||6.60|
|E1|4.60|4.70|4.80|
|e|2.16|2.28|2.40|
|e1|4.40||4.60|
|H|9.35||10.10|
|L|1.00||1.50|
|(L1)|2.60|2.80|3.00|
|L2|0.65|0.80|0.95|
|L4|0.60||1.00|
|R||0.20||
|V2|0°||8°|



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**Package information** 

**Figure 20: DPAK (TO-252) type A recommended footprint (dimensions are in mm)** 

**==> picture [407 x 273] intentionally omitted <==**

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**Package information** 

## **4.2 DPAK (TO-252) packing information** 

**Figure 21: DPAK (TO-252) tape outline** 

~~©~~ 12/15 DocID025607 Rev 4 

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**Package information** 

**Figure 22: DPAK (TO-252) reel outline** 

**Table 9: DPAK (TO-252) tape and reel mechanical data** 

|**Tape**|**Tape**|**Tape**|**Reel**|**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Dim.**|**mm**||**Dim.**|**mm**||
||**Min.**|**Max.**||**Min.**|**Max.**|
|A0|6.8|7|A||330|
|B0|10.4|10.6|B|1.5||
|B1||12.1|C|12.8|13.2|
|D|1.5|1.6|D|20.2||
|D1|1.5||G|16.4|18.4|
|E|1.65|1.85|N|50||
|F|7.4|7.6|T||22.4|
|K0|2.55|2.75||||
|P0|3.9|4.1|Baseqty.||2500|
|P1|7.9|8.1|Bulkqty.||2500|
|P2|1.9|2.1||||
|R|40|||||
|T|0.25|0.35||||
|W|15.7|16.3||||



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**Revision history** 

## **5 Revision history** 

**Table 10: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|28-Nov-2013|1|First release|
|03-Apr-2014|2|– Updated:_Figure 13,14,15_and_Figure 16_<br>– Updated:_Section 4.1: DPAK,STD30N10F7_<br>– Minor text changes.|
|27-Jan-2016|3|– Updated title<br>– Updated_Section 2: Electrical characteristics_<br>– Updated_Section 4: Package information_<br>– Minor text changes.|
|16-May-2017|4|Modified_Table 2: "Absolute maximum ratings"_.<br>Updated_Section 4: "Package information"_.<br>Minor text changes.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2017 STMicroelectronics – All rights reserved 

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- [Supplier page](https://es.farnell.com/stmicroelectronics/std30n10f7/mosfet-n-ch-100v-32a-175deg-c/dp/3132724)
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