# Power MOSFET, N Channel, 100 V, 25 A, 0.035 ohm, TO-252 (DPAK), Surface Mount

![Product image](https://novapart.co/image/farnell:9946330/)

**URL**: https://novapart.co/products/STD25NF10LA/power-mosfet-n-channel-100-v-25-a-0035-ohm-to-252
**SKU**: STD25NF10LA
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.6800
**Stock**: 1000+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:25A; Drain Source Voltage Vds:100V; On Resistance Rds(on):0.03ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:2.5V; Power Dissipation

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 100W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 100V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 25A |
| Drain Source On State Resistance | 0.035ohm |
| Gate Source Threshold Voltage Max | 2.5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:9946330/)

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## **STD25NF10LA** N-channel 100 V,  0.030 Ω, 25 A DPAK STripFET™ II Power MOSFET 

## **Features** 

|**Order code**|**VDSS**|**RDS(on)max**|**ID**|
|---|---|---|---|
|STD25NF10LA|100 V|< 0.035Ω|25 A|



- Exceptional dv/dt capability 

- 100% avalanche tested 

- Logic level device 

**==> picture [58 x 53] intentionally omitted <==**

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TAB<br>3<br>1<br>DPAK<br>**----- End of picture text -----**<br>


## **Applications** 

- Switching application 

- Automotive 

## **Description** 

This Power MOSFET has been developed using STMicroelectronics’ unique STripFET process, which is specifically designed to minimize input capacitance and gate charge. This renders the device suitable for use as primary switch in advanced high-efficiency isolated DC-DC converters for telecom and computer applications, and applications with low gate charge driving requirements. 

## **Figure 1. Internal schematic diagram** 

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D(TAB)<br>G(1)<br>S(3) AM09016v1<br>**----- End of picture text -----**<br>


## **Table 1. Device summary** 

|**Order code**|**Marking**|**Package**|**Packaging**|
|---|---|---|---|
|STD25NF10LA|D25NF10LA|DPAK|Tape and reel|



October 2011 

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_www.st.com_ 

**Contents** 

**STD25NF10LA** 

|**Contents**|**Contents**|
|---|---|
|**1**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3**|
|**2**|**Electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4**|
||2.1<br>Electrical characteristics (curves)       . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**3**|**Test circuit   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8**|
|**4**|**Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9**|
|**5**|**Packing mechanical data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12**|
|**6**|**Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2. Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|100|V|
|VGS|Gate- source voltage|± 16|V|
|ID<br>(1)|Drain current (continuous) at TC= 25 °C|25|A|
|ID|Drain current (continuous) at TC= 100 °C|21|A|
|IDM<br>(2)|Drain current (pulsed)|100|A|
|Ptot|Total dissipation at TC= 25 °C|100|W|
||Derating Factor|0.67|W/°C|
|dv/dt(3)|Peak diode recovery avalanche energy|20|V/ns|
|EAS<br>(4)|Single pulse avalanche energy|450|mJ|
|Tstg|Storage temperature|-55 to 175|°C|
|Tj|Max. operating junction temperature|||



1. Current limited by package 

2. Pulse width limited by safe operating area. 

3. ISD ≤ 25 A, di/dt ≤ 300 A/µs, VDD =V(BR)DSS, TJ ≤ TJMAX 

4. Starting Tj = 25 °C, ID = 12.5 A VDD = 50 V 

## **Table 3. Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistance junction-case max|1.5|°C/W|
|Rthj-pcb|Thermal resistance junction-pcb max(1)|50|°C/W|



1. When Mounted on 1 inch2 FR-4 board, 2 oz. of Cu. 

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**STD25NF10LA** 

**Electrical characteristics** 

## **2 Electrical characteristics** 

(TCASE=25°C unless otherwise specified) 

## **Table 4. On/off states** 

|**Table 4.**|**On/off states**||||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|V(BR)DSS|Drain-source<br>breakdown voltage|ID= 250 µA, VGS=0|100|||V|
|IDSS|Zero gate voltage<br>drain current|VDS= 100 V<br>VDS= 100 V, TC= 125 °C<br>VGS=0|||1<br>10|µA<br>µA|
|IGSS|Gate-body leakage<br>current|VGS= ± 16 V, VDS= 0|||±100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 µA|1||2.5|V|
|RDS(on)|Static drain-source on<br>resistance|VGS= 10 V, ID= 12.5 A<br>VGS= 4.5 V, ID= 12.5 A||0.030<br>0.035|0.035<br>0.040|Ω<br>Ω|



## **Table 5. Dynamic** 

|**Table 5.**|**Dynamic**||||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|Ciss<br>Coss<br>Crss|Input capacitance<br>Output capacitance<br>Reverse transfer<br>capacitance|VDS= 25 V, f = 1 MHz,<br>VGS= 0|-|1710<br>250<br>110||pF<br>pF<br>pF|
|td(on)<br>tr<br>td(off)<br>tf|Turn-on delay time<br>Rise time<br>Turn-off delay time<br>Fall time|VDD= 50 V, ID= 12.5 A<br>RG= 4.7ΩVGS= 5 V<br>(see_Figure 13_)|-|20<br>40<br>58<br>20||ns<br>ns<br>ns<br>ns|
|Qg<br>Qgs<br>Qgd|Total gate charge<br>Gate-source charge<br>Gate-drain charge|VDD= 80 V, ID= 25 A,<br>VGS= 5 V, RG= 4.7Ω<br>(see_Figure 14_)|-|38<br>8.5<br>21|52|nC<br>nC<br>nC|



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**Electrical characteristics** 

## **Table 6. Source drain diode** 

|**Table 6.**|**Source drain diode**||||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|ISD<br>ISDM (1)|Source-drain current<br>Source-drain current (pulsed)||-||25<br>100|A<br>A|
|VSD (2)|Forward on voltage|ISD= 25 A, VGS= 0|-||1.5|V|
|trr<br>Qrr<br>IRRM|Reverse recovery time<br>Reverse recovery charge<br>Reverse recovery current|ISD= 25 A, di/dt = 100 A/µs,<br>VDD= 50 V, Tj= 150 °C<br>(see_Figure 15_)|-|88<br>317<br>7.2||ns<br>nC<br>A|



1. Pulse width limited by safe operating area. 

2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% 

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**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

## **Figure 2. Safe operating area** 

**Figure 3. Thermal impedance** 

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**Figure 4. Output characteristics** 

## **Figure 5. Transfer characteristics** 

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**Figure 6. Normalized breakdown voltage vs. temperature** 

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**Figure 7. Static drain-source on resistance** 

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**Electrical characteristics** 

## **Figure 8. Gate charge vs. gate-source voltage Figure 9.** 

## **Capacitance variations** 

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**Figure 10. Normalized gate threshold voltage vs. temperature** 

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**Figure 11. Normalized on resistance vs. temperature** 

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**Figure 12. Source-drain diode forward characteristics** 

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**Test circuit** 

## **3 Test circuit** 

**Figure 13. Switching times test circuit for Figure 14. Gate charge test circuit resistive load** 

**==> picture [462 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>12V 47kΩ<br>1kΩ<br>100nF<br>RL 2200 3.3<br>μF μF<br>VDD IG=CONST<br>VD Vi=20V=VGMAX 100Ω D.U.T.<br>VGS<br>2200<br>RG D.U.T. μF 2.7kΩ VG<br>PW<br>47kΩ<br>1kΩ<br>PW<br>AM01468v1 AM01469v1<br>**----- End of picture text -----**<br>


**Figure 15. Test circuit for inductive load switching and diode recovery times** 

**Figure 16. Unclamped Inductive load test circuit** 

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**----- Start of picture text -----**<br>
L<br>A A A<br>D<br>G D.U.T. FASTDIODE L=100μH VD 2200 3.3<br>S B 3.3 1000 μF μF VDD<br>25 Ω B B D μF μF VDD ID<br>G<br>RG S<br>Vi D.U.T.<br>Pw<br>AM01470v1 AM01471v1<br>**----- End of picture text -----**<br>


## **Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform** 

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V(BR)DSS ton toff<br>VD tdon tr tdoff tf<br>90% 90%<br>IDM<br>10%<br>ID 0 10% VDS<br>VDD VDD 90%<br>VGS<br>AM01472v1 0 10% AM01473v1<br>**----- End of picture text -----**<br>


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**Package mechanical data** 

## **4 Package mechanical data** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 

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**Package mechanical data** 

**Table 7. DPAK (TO-252) mechanical data** 

|**Dim.**|**mm**|**mm**|**mm**|
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|2.20||2.40|
|A1|0.90||1.10|
|A2|0.03||0.23|
|b|0.64||0.90|
|b4|5.20||5.40|
|c|0.45||0.60|
|c2|0.48||0.60|
|D|6.00||6.20|
|D1||5.10||
|E|6.40||6.60|
|E1||4.70||
|e||2.28||
|e1|4.40||4.60|
|H|9.35||10.10|
|L|1||1.50|
|L1||2.80||
|L2||0.80||
|L4|0.60||1|
|R||0.20||
|V2|0°||8°|



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**Package mechanical data** 

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**----- Start of picture text -----**<br>
Figure 19. DPAK (TO-252) drawing<br>**----- End of picture text -----**<br>


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0068772_H<br>**----- End of picture text -----**<br>


## **Figure 20. DPAK footprint[(a)]** 

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6.7 1.8 3<br>1.6<br>2.3<br>6.7<br>2.3<br>1.6<br>AM08850v1<br>**----- End of picture text -----**<br>


a. All dimensions are in millimeters 

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**Packing mechanical data** 

## **5 Packing mechanical data** 

**Table 8. DPAK (TO-252) tape and reel mechanical data** 

||**Tape**|**Tape**||**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Dim.**|**mm**||**Dim.**|**mm**||
||**Min.**|**Max.**||**Min.**|**Max.**|
|A0|6.8|7|A||330|
|B0|10.4|10.6|B|1.5||
|B1||12.1|C|12.8|13.2|
|D|1.5|1.6|D|20.2||
|D1|1.5||G|16.4|18.4|
|E|1.65|1.85|N|50||
|F|7.4|7.6|T||22.4|
|K0|2.55|2.75||||
|P0|3.9|4.1||Base qty.|2500|
|P1|7.9|8.1||Bulk qty.|2500|
|P2|1.9|2.1||||
|R|40|||||
|T|0.25|0.35||||
|W|15.7|16.3||||



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**Packing mechanical data** 

## **Figure 21. Tape for DPAK (TO-252)** 

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**----- Start of picture text -----**<br>
10 pitches cumulative<br>tolerance on tape +/- 0.2 mm<br>Top cover P0 D P2<br>T “ye tape<br>[ 0OO0 0GG 000G@ O 00O E<br>F<br>K0 W<br>B1 B0<br>A SL IR E IEY<br>| 7 a<br>For machine ref. only A0 P1 D1<br>including draft and<br>radii concentric around B0 —_—__><br>User direction of feed<br>R<br>V eal e aca ai e<br>Son8556<br>ee CG SN<br>————_—_—_—_ > Bending radius<br>User direction of feed<br>**----- End of picture text -----**<br>


**==> picture [38 x 6] intentionally omitted <==**

**----- Start of picture text -----**<br>
AM08852v1<br>**----- End of picture text -----**<br>


## **Figure 22. Reel for DPAK (TO-252)** 

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**----- Start of picture text -----**<br>
T<br>REEL DIMENSIONS<br>40mm min.<br>Access hole<br>At sl ot location<br>B<br>D<br>C<br>N<br>A<br>Full radius Tape slot  G measured at hub<br>in core for<br>tape start 25 mm min.<br>width<br>AM08851v2<br>**----- End of picture text -----**<br>


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**STD25NF10LA** 

**Revision history** 

## **6 Revision history** 

**Table 9. Revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|05-Oct-2011|1|First release.|



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## Links

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- [Supplier page](https://es.farnell.com/stmicroelectronics/std25nf10la/mosfet-n-d-pak/dp/9946330)
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