# Power MOSFET, N Channel, 650 V, 11 A, 0.32 ohm, TO-252 (DPAK), Surface Mount

![Product image](https://novapart.co/image/farnell:4036295/)

**URL**: https://novapart.co/products/STD16N65M2/power-mosfet-n-channel-650-v-11-a-032-ohm-to-252
**SKU**: STD16N65M2
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.8670
**Stock**: 1000+
**Lead Time**: 2 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | MDmesh M2 Series |
| Qualification | - |
| Power Dissipation | 110W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 650V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 11A |
| Drain Source On State Resistance | 0.32ohm |
| Gate Source Threshold Voltage Max | 3V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:4036295/)

## **STD16N65M2** 

## N-channel 650 V, 0.32 Ω typ., 11 A MDmesh M2 Power MOSFET in a DPAK package 

− **Datasheet production data** 

## **Features** 

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TAB<br>3<br>2<br>1<br>DPAK<br>**----- End of picture text -----**<br>


**Order code VDS @ TJmax RDS(on) max ID** STD16N65M2 710 V 0.36 Ω 11 A ~~——_——~~ 

- Extremely low gate charge 

- Excellent output capacitance (Coss) profile 

- 100% avalanche tested 

- Zener-protected 

## **Applications** 

- Switching applications 

## **Figure 1. Internal schematic diagram** 

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## **Description** 

This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. 

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**Table 1. Device summary** 

**Order codes Marking Package Packaging** STD16N65M2 16N65M2 DPAK Tape and reel ~~—p~~ 

_www.st.com_ 

October 2014 

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This is information on a product in full production. 

**Contents** 

**STD16N65M2** 

|**Contents**|**Contents**|
|---|---|
|**1**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3**|
|**2**|**Electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4**|
||2.1<br>Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**3**|**Test circuits     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8**|
|**4**|**Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9**|
|**5**|**Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13**|
|**6**|**Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2. Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VGS|Gate-source voltage|± 25|V|
|ID|Drain current (continuous) at TC= 25 °C|11|A|
|ID|Drain current (continuous) at TC= 100 °C|6.9|A|
|IDM<br>(1)|Drain current (pulsed)|44|A|
|PTOT|Total dissipation at TC= 25 °C|110|W|
|dv/dt(2)|Peak diode recovery voltage slope|15|V/ns|
|dv/dt(3)|MOSFET dv/dt ruggedness|50|V/ns|
|Tstg|Storage temperature|- 55 to 150|°C|
|Tj|Max. operating junction temperature|||



1. Pulse width limited by safe operating area. 

2. ISD ≤ 11 A, di/dt ≤ 400 A/µs; VDS peak < V(BR)DSS, VDD=400 V. 

3. VDS ≤ 520 V 

**Table 3. Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistance junction-case max|1.14|°C/W|
|Rthj-pcb|Thermal resistance junction-pcb max(1)|50|°C/W|



1. When mounted on 1 inch² FR-4, 2 Oz copper board 

**Table 4. Avalanche characteristics** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|IAR|Avalanche current, repetitive or not<br>repetitive (pulse width limited by Tjmax)|1.9|A|
|EAS|Single pulse avalanche energy (starting<br>Tj=25°C, ID= IAR; VDD=50)|360|mJ|



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**STD16N65M2** 

**Electrical characteristics** 

## **2 Electrical characteristics** 

(TC = 25 °C unless otherwise specified) 

**Table 5. On /off states** 

|||**Table 5. On /off states**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|V(BR)DSS|Drain-source<br>breakdown voltage|VGS= 0, ID= 1 mA|650|||V|
|IDSS|Zero gate voltage<br>drain current|VGS= 0, VDS= 650 V|||1|µA|
|||VGS= 0, VDS= 650 V,<br>TC=125 °C|||100|µA|
|IGSS|Gate-body leakage<br>current|VDS= 0, VGS= ± 25 V|||±10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 µA|2|3|4|V|
|RDS(on)|Static drain-source<br>on-resistance|VGS= 10 V, ID= 5.5 A||0.32|0.36|Ω|



**Table 6. Dynamic** 

|||**Table 6. Dynamic**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|Ciss|Input capacitance|VGS= 0, VDS= 100 V,<br>f = 1 MHz|-|718|-|pF|
|Coss|Output capacitance||-|32|-|pF|
|Crss|Reverse transfer<br>capacitance||-|1.1|-|pF|
|Coss eq.<br>(1)|Equivalent output<br>capacitance|VGS= 0, VDS= 0 to 520 V|-|189|-|pF|
|RG|Intrinsic gate<br>resistance|f = 1 MHz open drain|-|5.2|-|Ω|
|Qg|Total gate charge|VDD= 520 V, ID= 11 A,<br>VGS= 10 V (see_Figure 15_)|-|19.5|-|nC|
|Qgs|Gate-source charge||-|4|-|nC|
|Qgd|Gate-drain charge||-|8.3|-|nC|



1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 

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**STD16N65M2** 

**Electrical characteristics** 

**Table 7. Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD= 325 V, ID= 5.5 A,<br>RG= 4.7Ω,VGS= 10 V<br>(see_Figure 14_and_19_)|-|11.3|-|ns|
|tr|Rise time||-|8.2|-|ns|
|td(off)|Turn-off delay time||-|36|-|ns|
|tf|Fall time||-|11.3|-|ns|



**Table 8. Source drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||11|A|
|ISDM (1)|Source-drain current (pulsed)||-||44|A|
|VSD (2)|Forward on voltage|VGS= 0, ISD= 11 A|-||1.6|V|
|trr|Reverse recovery time|ISD= 11 A, di/dt = 100 A/µs<br>VDD= 60 V (see_Figure 16_)|-|342||ns|
|Qrr|Reverse recovery charge||-|3.5||µC|
|IRRM|Reverse recovery current||-|20.4||A|
|trr|Reverse recovery time|ISD= 11 A, di/dt = 100 A/µs<br>VDD= 60 V, Tj=150 °C<br>(see_Figure 16_)|-|458||ns|
|Qrr|Reverse recovery charge||-|4.6||µC|
|IRRM|Reverse recovery current||-|20.5||A|



1. Pulse width limited by safe operating area 

2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% 

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**STD16N65M2** 

**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2. Safe operating area** 

## **Figure 3. Thermal impedance** 

**Figure 4. Output characteristics** 

**Figure 5. Transfer characteristics** 

**Figure 6. Normalized gate threshold voltage vs. Figure 7. Normalized V(BR)DSS vs. temperature temperature** 

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GIPD180920141442FSR GIPD180920141448FSR<br>VGS(th) V(BR)DSS<br>(norm) (norm)<br>ID = 250 µA<br>1.1 1.08<br>ID= 1mA<br>1.0 1.04<br>0.9 1.00<br>0.8 0.96<br>0.7 0.92<br>0.6 0.88<br>-75 -25 25 75 125 Tj(°C) -75 -25 25 75 125 Tj(°C)<br>**----- End of picture text -----**<br>


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DocID027076 Rev 1<br>**----- End of picture text -----**<br>


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**STD16N65M2** 

**Electrical characteristics** 

**Figure 8. Static drain-source on-resistance** 

**Figure 9. Normalized on-resistance vs. temperature** 

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GIPD180920141459FSR<br>RDS(on)<br>(norm)<br>2.2<br>VGS= 10V<br>1.8<br>1.4<br>1<br>0.6<br>0.2<br>-75 -25 25 75 125 Tj(°C)<br>**----- End of picture text -----**<br>


**Figure 10. Gate charge vs. gate-source voltage** 

**Figure 12. Output capacitance stored energy** 

**Figure 11. Capacitance variations** 

**Figure 13. Source-drain diode forward characteristics** 

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**STD16N65M2** 

**Test circuits** 

## **3 Test circuits** 

**Figure 14. Switching times test circuit for resistive load** 

**Figure 15. Gate charge test circuit** 

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VDD<br>12V 47kΩ<br>1kΩ<br>100nF<br>RL 2200 3.3<br>μF μF<br>VDD IG=CONST<br>VD Vi=20V=VGMAX 100Ω D.U.T.<br>VGS<br>2200<br>RG D.U.T. μF 2.7kΩ VG<br>PW<br>47kΩ<br>1kΩ<br>PW<br>AM01468v1 AM01469v1<br>**----- End of picture text -----**<br>


**Figure 16. Test circuit for inductive load Figure 17. Unclamped inductive load test circuit switching and diode recovery times** 

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L<br>A A A<br>D<br>FAST L=100μH VD<br>G D.U.T. DIODE 2200 3.3<br>S B 3.3 1000 μF μF VDD<br>25 Ω B B D μF μF VDD ID<br>G<br>RG S<br>Vi D.U.T.<br>Pw<br>AM01470v1 AM01471v1<br>**----- End of picture text -----**<br>


## **Figure 18. Unclamped inductive waveform** 

## **Figure 19. Switching time waveform** 

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**Package mechanical data** 

## **4 Package mechanical data** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _www.st.com_ . ECOPACK[®] is an ST trademark. 

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**STD16N65M2** 

**Package mechanical data** 

## **Figure 20. DPAK (TO-252) type A drawing** 

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**Package mechanical data** 

**Table 9. DPAK (TO-252) type A mechanical data** 

||**Table 9. DPAK(TO-252) type A mechanical data**|**Table 9. DPAK(TO-252) type A mechanical data**|**Table 9. DPAK(TO-252) type A mechanical data**|
|---|---|---|---|
|**Dim.**|**mm**|||
||**Min.**|**Typ.**|**Max.**|
|A|2.20||2.40|
|A1|0.90||1.10|
|A2|0.03||0.23|
|b|0.64||0.90|
|b4|5.20||5.40|
|c|0.45||0.60|
|c2|0.48||0.60|
|D|6.00||6.20|
|D1||5.10||
|E|6.40||6.60|
|E1||4.70||
|e||2.28||
|e1|4.40||4.60|
|H|9.35||10.10|
|L|1.00||1.50|
|L1||2.80||
|L2||0.80||
|L4|0.60||1.00|
|R||0.20||
|V2|0°||8°|



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**STD16N65M2** 

**Package mechanical data** 

## **Figure 21. DPAK (TO-252) footprint[(a)]** 

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- a. All dimensions are in millimeters 

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**Packaging mechanical data** 

## **5 Packaging mechanical data** 

## **Figure 22. Tape** 

**==> picture [399 x 316] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 pitches cumulative<br>tolerance on tape +/- 0.2 mm<br>Top cover P0 D P2<br>T tape<br>E<br>F<br>K0 W<br>B1 B0<br>A) | Tl I R IGY Co<br>For machine ref. only A0 P1 D1<br>including draft and<br>radii concentric around B0<br>S$ User direction of feed ><br>R<br>ol eh tel al fa l ta a<br>|» Bending radius<br>User direction of feed<br>AM08852v1<br>**----- End of picture text -----**<br>


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**Packaging mechanical data** 

**==> picture [405 x 267] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 23. Reel<br>T<br>REEL DIMENSIONS<br>40mm min.<br>Access hole<br>At slot location<br>B<br>D<br>C<br>N<br>A<br>Full radius Tape slot  G measured at hub<br>in core for<br>tape start 25 mm min.<br>width<br>AM08851v2<br>**----- End of picture text -----**<br>


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**Packaging mechanical data** 

**Table 10. DPAK (TO-252) tape and reel mechanical data** 

||**Tape**|**Tape**||**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Dim.**|**mm**||**Dim.**|**mm**||
||**Min.**|**Max.**||**Min.**|**Max.**|
|A0|6.8|7|A||330|
|B0|10.4|10.6|B|1.5||
|B1||12.1|C|12.8|13.2|
|D|1.5|1.6|D|20.2||
|D1|1.5||G|16.4|18.4|
|E|1.65|1.85|N|50||
|F|7.4|7.6|T||22.4|
|K0|2.55|2.75||||
|P0|3.9|4.1||Base qty.|2500|
|P1|7.9|8.1||Bulk qty.|2500|
|P2|1.9|2.1||||
|R|40|||||
|T|0.25|0.35||||
|W|15.7|16.3||||



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**STD16N65M2** 

**Revision history** 

## **6 Revision history** 

**Table 11. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|24-Oct-2014|1|First release.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2014 STMicroelectronics – All rights reserved 

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