# Power MOSFET, N Channel, 500 V, 10 A, 0.336 ohm, TO-252 (DPAK), Surface Mount

![Product image](https://novapart.co/image/farnell:3132721/)

**URL**: https://novapart.co/products/STD15N50M2AG/power-mosfet-n-channel-500-v-10-a-0336-ohm-to-252
**SKU**: STD15N50M2AG
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.6820
**Stock**: 1000+
**Lead Time**: 2 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:10A; Drain Source Voltage Vds:500V; On Resistance Rds(on):0.336ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:3

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | MDmesh M2 |
| Qualification | AEC-Q101 |
| Power Dissipation | 85W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 500V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 10A |
| Drain Source On State Resistance | 0.336ohm |
| Gate Source Threshold Voltage Max | 3V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3132721/)

## **STD15N50M2AG** 

Automotive-grade N-channel 500 V, 0.336 Ω typ., 10 A MDmesh™ M2 Power MOSFET in a DPAK package 

Datasheet - production data 

## **Features** 

**Order code VDS RDS(on) ID PTOT max.** STD15N50M2AG 500 V 0.380 Ω 10 A 85 W ~~| | |~~ 

- Designed for automotive applications and AEC-Q101 qualified 

- Extremely low gate charge 

**Figure 1: Internal schematic diagram** 

- Excellent output capacitance (COSS) profile 

- 100% avalanche tested 

- Zener-protected 

## **Applications** 

- Switching applications 

## **Description** 

This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, 

rendering it suitable for the most demanding high efficiency converters. 

**Table 1: Device summary** 

|**Order code**|**Marking**|**Package**|**Packing**|
|---|---|---|---|
|STD15N50M2AG|15N50M2|DPAK|Tape and reel|



This is information on a product in full production. 

_www.st.com_ 

May 2016 

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|**Contents**<br>**STD15N50M2AG**|**Contents**<br>**STD15N50M2AG**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>DPAK (TO-252) type A2 package information................................. 10|
||4.2<br>DPAK (TO-252) packing information ............................................... 13|
|**5**|**Revision history ............................................................................ 15**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VGS|Gate-source voltage|±30|V|
|ID|Drain current (continuous) at Tcase= 25 °C|10|A|
||Drain current (continuous) at Tcase= 100 °C|7||
|IDM_(1)_|Drain current (pulsed)|40|A|
|PTOT|Total dissipation at Tcase= 25 °C|85|W|
|dv/dt_(2)_|Peak diode recoveryvoltage slope|10|V/ns|
|dv/dt_(3)_|MOSFET dv/dt ruggedness|25||
|Tstg|Storage temperature range|-55 to 150|°C|
|Tj|Operating junction temperature range|||



## **Notes:** 

- (1) Pulse width is limited by safe operating area. 

- (2) ISD ≤ 10 A, di/dt=800 A/μs; VDS peak < V(BR)DSS,VDD = 80% V(BR)DSS (3) VDS ≤ 400 V. 

||**Table 3: Thermal data**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|Rthj-case|Thermal resistancejunction-case max.|1.47|°C/W|
|Rthj-pcb_(1)_|Thermal resistancejunction-pcb max.|50||



## **Notes:** 

- (1)When mounted on a 1 inch² FR-4, 2 Oz copper board 

**Table 4: Avalanche characteristics** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|IAR_(1)_|Avalanche current, repetitive or not repetitive|3.5|A|
|EAS_(2)_|Singlepulse avalanche energy|200|mJ|



## **Notes:** 

- (1) pulse width limited by Tjmax 

- (2) starting Tj = 25 °C, ID = IAR, VDD = 50 V. 

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**Electrical characteristics** 

## **2 Electrical characteristics** 

(Tcase = 25 °C unless otherwise specified) 

**Table 5: Static** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|VGS= 0 V, ID= 1 mA|500|||V|
|IDSS|Zero gate voltage drain<br>current|VGS= 0 V, VDS= 500 V|||1|µA|
|||VGS= 0 V, VDS= 500 V,<br>Tcase= 125 °C|||100||
|IGSS|Gate-body leakage<br>current|VDS= 0 V, VGS= ±25 V|||±5|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250µA|2|3|4|V|
|RDS(on)|Static drain-source on-<br>resistance|VGS= 10 V, ID= 5 A||0.336|0.380|Ω|



**Table 6: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 100 V, f = 1 MHz,<br>VGS= 0 V|-|530|-|pF|
|Coss|Output capacitance||-|33|-||
|Crss|Reverse transfer<br>capacitance||-|0.8|-||
|Coss eq._(1)_|Equivalent output<br>capacitance|VDS= 0 to 400 V, VGS= 0 V|-|125|-|pF|
|RG|Intrinsicgate resistance|f = 1 MHz, ID= 0 A|-|6.9|-|Ω|
|Qg|Totalgate charge|VDD= 400 V, ID= 9 A,<br>VGS= 10 V (see_Figure 15:_<br>_"Test circuit for gate charge_<br>_behavior"_)|-|13|-|nC|
|Qgs|Gate-source charge||-|2.8|-||
|Qgd|Gate-drain charge||-|5.1|-||



## **Notes:** 

(1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 

**Table 7: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDD= 250 V, ID= 4.5 A<br>RG= 4.7 Ω, VGS= 10 V (see<br>_Figure 14: "Test circuit for_<br>_resistive load switching times"_<br>and_Figure 19: "Switching time_<br>_waveform"_)|-|10|-|ns|
|tr|Rise time||-|3.2|-||
|td(off)|Turn-off delaytime||-|84|-||
|tf|Fall time||-|8.8|-||



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**Electrical characteristics** 

**Table 8: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||10|A|
|ISDM_(1)_|Source-drain current<br>(pulsed)||-||40|A|
|VSD_(2)_|Forward on voltage|VGS= 0 V, ISD= 10 A|-||1.6|V|
|trr|Reverse recoverytime|ISD= 9 A, di/dt = 100 A/µs,<br>VDD= 100 V (see_Figure 16:_<br>_"Test circuit for inductive load_<br>_switching and diode recovery_<br>_times"_)|-|230||ns|
|Qrr|Reverse recoverycharge||-|2||µC|
|IRRM|Reverse recovery current||-|17.4||A|
|trr|Reverse recoverytime|ISD= 9 A, di/dt = 100 A/µs,<br>VDD= 100 V, Tj= 150 °C (see<br>_Figure 16: "Test circuit for_<br>_inductive load switching and_<br>_diode recovery times"_)|-|310||ns|
|Qrr|Reverse recoverycharge||-|2.7||µC|
|IRRM|Reverse recovery current||-|17.5||A|



## **Notes:** 

- (1) Pulse width is limited by safe operating area. 

- (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. 

## **Table 9: Gate-source Zener diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)GSO|Gate-source breakdown<br>voltage|IGS= ±250 µA, ID= 0 A|±30|-|-|V|



The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. 

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## **Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**==> picture [378 x 168] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 2: Safe operating area  Figure 3: Thermal impedance<br>**----- End of picture text -----**<br>


**==> picture [388 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 4: Output characteristics  Figure 5: Transfer characteristics<br>**----- End of picture text -----**<br>


**Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance** 

**==> picture [158 x 141] intentionally omitted <==**

**==> picture [161 x 144] intentionally omitted <==**

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**Electrical characteristics** 

**==> picture [416 x 376] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 9: Normalized gate threshold voltage<br>Figure 8: Capacitance variations<br>vs temperature<br>Figure 10: Normalized on-resistance vs  Figure 11: Normalized V(BR)DSS vs<br>temperature  temperature<br>**----- End of picture text -----**<br>


**Figure 13: Source-drain diode forward Figure 12: Output capacitance stored energy characteristics** 

**==> picture [162 x 145] intentionally omitted <==**

**==> picture [152 x 142] intentionally omitted <==**

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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 561] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 14: Test circuit for resistive load  Figure 15: Test circuit for gate charge<br>switching times  behavior<br>Figure 16: Test circuit for inductive load  Figure 17: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>Figure 18: Unclamped inductive waveform  Figure 19: Switching time waveform<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

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**Package information** 

## **4.1 DPAK (TO-252) type A2 package information** 

**==> picture [219 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 20: DPAK (TO-252) type A2 package outline<br>**----- End of picture text -----**<br>


**==> picture [406 x 561] intentionally omitted <==**

**----- Start of picture text -----**<br>
0068772_type-A2_rev21<br>**----- End of picture text -----**<br>


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**Package information** 

**Table 10: DPAK (TO-252) type A2 mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|2.20||2.40|
|A1|0.90||1.10|
|A2|0.03||0.23|
|b|0.64||0.90|
|b4|5.20||5.40|
|c|0.45||0.60|
|c2|0.48||0.60|
|D|6.00||6.20|
|D1|4.95|5.10|5.25|
|E|6.40||6.60|
|E1|5.10|5.20|5.30|
|e|2.16|2.28|2.40|
|e1|4.40||4.60|
|H|9.35||10.10|
|L|1.00||1.50|
|L1|2.60|2.80|3.00|
|L2|0.65|0.80|0.95|
|L4|0.60||1.00|
|R||0.20||
|V2|0°||8°|



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**Package information** 

**Figure 21: DPAK (TO-252) recommended footprint (dimensions are in mm)** 

**==> picture [407 x 273] intentionally omitted <==**

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**Package information** 

## **4.2 DPAK (TO-252) packing information** 

**Figure 22: DPAK (TO-252) tape outline** 

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**Package information** 

**Figure 23: DPAK (TO-252) reel outline** 

**Table 11: DPAK (TO-252) tape and reel mechanical data** 

|**Tape**|**Tape**|**Tape**|**Reel**|**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Dim.**|**mm**||**Dim.**|**mm**||
||**Min.**|**Max.**||**Min.**|**Max.**|
|A0|6.8|7|A||330|
|B0|10.4|10.6|B|1.5||
|B1||12.1|C|12.8|13.2|
|D|1.5|1.6|D|20.2||
|D1|1.5||G|16.4|18.4|
|E|1.65|1.85|N|50||
|F|7.4|7.6|T||22.4|
|K0|2.55|2.75||||
|P0|3.9|4.1|Baseqty.||2500|
|P1|7.9|8.1|Bulkqty.||2500|
|P2|1.9|2.1||||
|R|40|||||
|T|0.25|0.35||||
|W|15.7|16.3||||



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**Revision history** 

## **5 Revision history** 

**Table 12: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|13-Apr-2015|1|First release.|
|07-May-2016|2|Minor text edits<br>Document status promoted to production data<br>Updated_Section 1: "Electrical ratings"_<br>Updated_Section 2: "Electrical characteristics"_<br>Updated_Section 2.1: "Electrical characteristics (curves)"_<br>Updated_Section 4.1: "DPAK (TO-252) type A2 package information"_|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2016 STMicroelectronics – All rights reserved 

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- [Supplier page](https://es.farnell.com/stmicroelectronics/std15n50m2ag/mosfet-aec-q101-n-ch-500v-10a/dp/3132721)
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