# Power MOSFET, N Channel, 40 V, 80 A, 2500 µohm, TO-252 (DPAK), Surface Mount

![Product image](https://novapart.co/image/farnell:2767835RL/)

**URL**: https://novapart.co/products/STD134N4F7AG/power-mosfet-n-channel-40-v-80-a-2500-ohm-to-252
**SKU**: STD134N4F7AG
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.6070
**Stock**: 10+
**Lead Time**: 133 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:80A; Drain Source Voltage Vds:40V; On Resistance Rds(on):0.0025ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4V;

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | STripFET F7 |
| Qualification | AEC-Q101 |
| Power Dissipation | 134W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 40V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 80A |
| Drain Source On State Resistance | 2500µohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2767835RL/)

## **STD134N4F7AG** 

Automotive-grade N-channel 40 V, 2.5 mΩ typ., 80 A STripFET™ F7 Power MOSFET in a DPAK package 

Datasheet - production data 

## **Features** 

|**Order code**|**VDS**|**RDS(on)**<br>**max.**|**ID**|**PTOT**|
|---|---|---|---|---|
|STD134N4F7AG|40 V|3.5 mΩ|80 A|134 W|



- AEC-Q101 qualified 

- Among the lowest RDS(on) on the market 

- Excellent FoM (figure of merit) 

- Low Crss/Ciss ratio for EMI immunity 

**Figure 1: Internal schematic diagram** 

- High avalanche ruggedness 

## **Applications** 

D(2, TAB)  Switching applications **Description** This N-channel Power MOSFET utilizes G(1) STripFET™ F7 technology with an enhanced trench gate structure that results in very low on-state resistance, while also reducing internal capacitance and gate charge for faster and more S(3) efficient switching. AM01475v1_Tab **Table 1: Device summary Order code Marking Package Packing** ~~SeeaEnoae“S~~ STD134N4F7AG 134N4F7 DPAK Tape and reel 

This is information on a product in full production. 

December 2016 DocID030109 Rev 1 

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_www.st.com_ 

|**Contents**<br>**STD134N4F7AG**|**Contents**<br>**STD134N4F7AG**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>DPAK (TO-252) type A2 package information................................. 10|
||4.2<br>DPAK (TO-252) packing information ............................................... 13|
|**5**|**Revision history ............................................................................ 15**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|40|V|
|VGS|Gate-source voltage|±20|V|
|ID_(1)_|Drain current (continuous) at Tcase= 25 °C|80|A|
||Drain current (continuous) at Tcase= 100 °C|80||
|IDM_(2)_|Drain current (pulsed)|320|A|
|PTOT|Total dissipation at Tcase= 25 °C|134|W|
|EAS_(3)_|Singlepulse avalanche energy|325|mJ|
|Tstg|Storage temperature range|-55 to 175|°C|
|TJ|Operating junction temperature range|||



## **Notes:** 

(1)Current is limited by package 

(2)Pulse width is limited by safe operating area 

(3)Starting Tj = 25 °C, ID = 40 A, VDD = 20 V 

**Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case|1.12|°C/W|
|Rthj-pcb_(1)_|Thermal resistancejunction-pcb|50||



## **Notes:** 

(1)When mounted on a 1-inch² FR-4, 2 Oz copper board. 

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**STD134N4F7AG** 

**Electrical characteristics** 

## **2 Electrical characteristics** 

(Tcase = 25 °C unless otherwise specified) 

**Table 4: Static** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown voltage|VGS= 0 V, ID= 250µA|40|||V|
|IDSS|Zero gate voltage drain current|VGS= 0 V, VDS= 40 V|||1|µA|
|||VGS= 0 V, VDS= 40 V,<br>Tcase= 125 °C_(1)_|||100||
|IGSS|Gate-bodyleakage current|VDS= 0 V, VGS= ±20 V|||±100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250µA|2||4|V|
|RDS(on)|Static drain-source<br>on-resistance|VGS= 10 V, ID= 40 A||2.5|3.5|mΩ|



## **Notes:** 

(1)Defined by design, not subject to production test. 

**Table 5: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 25 V, f = 1 MHz,<br>VGS= 0 V|-|2790|-|pF|
|Coss|Output capacitance||-|890|-||
|Crss|Reverse transfer capacitance||-|60|-||
|Qg|Totalgate charge|VDD= 20 V, ID= 80 A,<br>VGS= 10 V<br>(see_Figure 14: "Test_<br>_circuit for gate charge_<br>_behavior"_)|-|41|-|nC|
|Qgs|Gate-source charge||-|15|-||
|Qgd|Gate-drain charge||-|11|-||



**Table 6: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDD= 20 V, ID= 40 A,<br>RG= 4.7 Ω, VGS= 10 V<br>(see_Figure 13: "Test circuit for_<br>_resistive load switching times"_<br>and_Figure 18: "Switching time_<br>_waveform"_)|-|18|-|ns|
|tr|Rise time||-|17.5|-||
|td(off)|Turn-off delaytime||-|26|-||
|tf|Fall time||-|13|-||



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**Electrical characteristics** 

**Table 7: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD_(1)_|Source-drain current||-||80|A|
|ISDM_(1)_|Source-drain current (pulsed)||-||320|A|
|VSD_(2)_|Forward on voltage|VGS= 0 V, ISD= 80 A|-||1.2|V|
|trr|Reverse recoverytime|ISD= 80 A, di/dt = 100 A/µs,<br>VDD= 32 V<br>(see_Figure 15: "Test circuit_<br>_for inductive load switching_<br>_and diode recovery times"_)|-|37||ns|
|Qrr|Reverse recoverycharge||-|28.5||nC|
|IRRM|Reverse recovery current||-|1.5||A|



## **Notes:** 

(1)Current is limited by package 

(2)Pulse test: pulse duration = 300 µs, duty cycle 1.5% 

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**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**==> picture [416 x 354] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 2: Safe operating area  Figure 3: Thermal impedance<br>Figure 4: Output characteristics  Figure 5: Transfer characteristics<br>**----- End of picture text -----**<br>


**==> picture [409 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 6: Gate charge vs gate-source voltage  Figure 7: Static drain-source on-resistance<br>**----- End of picture text -----**<br>


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**Electrical characteristics** 

**==> picture [416 x 375] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 8: Capacitance variations  Figure 9: Normalized gate threshold voltage<br>vs temperature<br>Figure 10: Normalized on-resistance vs  Figure 11: Normalized V(BR)DSS vs temperature<br>temperature<br>**----- End of picture text -----**<br>


**Figure 12: Source-drain diode forward characteristics** 

**==> picture [173 x 157] intentionally omitted <==**

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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 375] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 13: Test circuit for resistive load  Figure 14: Test circuit for gate charge<br>switching times  behavior<br>Figure 15: Test circuit for inductive load  Figure 16: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>**----- End of picture text -----**<br>


**==> picture [403 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 17: Unclamped inductive waveform  Figure 18: Switching time waveform<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

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**Package information** 

## **4.1 DPAK (TO-252) type A2 package information** 

**Figure 19: DPAK (TO-252) type A2 package outline** 

**==> picture [406 x 561] intentionally omitted <==**

**----- Start of picture text -----**<br>
0068772_type-A2_rev21<br>**----- End of picture text -----**<br>


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**Package information** 

**Table 8: DPAK (TO-252) type A2 mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|2.20||2.40|
|A1|0.90||1.10|
|A2|0.03||0.23|
|b|0.64||0.90|
|b4|5.20||5.40|
|c|0.45||0.60|
|c2|0.48||0.60|
|D|6.00||6.20|
|D1|4.95|5.10|5.25|
|E|6.40||6.60|
|E1|5.10|5.20|5.30|
|e|2.16|2.28|2.40|
|e1|4.40||4.60|
|H|9.35||10.10|
|L|1.00||1.50|
|L1|2.60|2.80|3.00|
|L2|0.65|0.80|0.95|
|L4|0.60||1.00|
|R||0.20||
|V2|0°||8°|



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**Package information** 

**Figure 20: DPAK (TO-252) type A2 recommended footprint (dimensions are in mm)** 

**==> picture [407 x 273] intentionally omitted <==**

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**Package information** 

## **4.2 DPAK (TO-252) packing information** 

**Figure 21: DPAK (TO-252) tape outline** 

~~S/n~~ DocID030109 Rev 1 13/16 

**STD134N4F7AG** 

**Package information** 

**Figure 22: DPAK (TO-252) reel outline** 

**Table 9: DPAK (TO-252) tape and reel mechanical data** 

|**Tape**|**Tape**|**Tape**|**Reel**|**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Dim.**|**mm**||**Dim.**|**mm**||
||**Min.**|**Max.**||**Min.**|**Max.**|
|A0|6.8|7|A||330|
|B0|10.4|10.6|B|1.5||
|B1||12.1|C|12.8|13.2|
|D|1.5|1.6|D|20.2||
|D1|1.5||G|16.4|18.4|
|E|1.65|1.85|N|50||
|F|7.4|7.6|T||22.4|
|K0|2.55|2.75||||
|P0|3.9|4.1|Baseqty.||2500|
|P1|7.9|8.1|Bulkqty.||2500|
|P2|1.9|2.1||||
|R|40|||||
|T|0.25|0.35||||
|W|15.7|16.3||||



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**Revision history** 

## **5 Revision history** 

## **Table 10: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|05-Dec-2016|1|First release|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2016 STMicroelectronics – All rights reserved 

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## Links

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- [Supplier page](https://es.farnell.com/stmicroelectronics/std134n4f7ag/mosfet-aec-q101-n-ch-40v-to-252/dp/2767835RL)
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