# Power MOSFET, N Channel, 60 V, 80 A, 4200 µohm, TO-252 (DPAK), Surface Mount

![Product image](https://novapart.co/image/farnell:2729691RL/)

**URL**: https://novapart.co/products/STD130N6F7/power-mosfet-n-channel-60-v-80-a-4200-ohm-to-252
**SKU**: STD130N6F7
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.4850
**Stock**: 10+

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:80A; Drain Source Voltage Vds:60V; On Resistance Rds(on):0.0042ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 134W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 60V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 80A |
| Drain Source On State Resistance | 4200µohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2729691RL/)

## **STD130N6F7** 

N-channel 60 V, 4.2 mΩ typ., 80 A STripFET™ F7 Power MOSFET in a DPAK package 

Datasheet - production data 

## **Features** 

|**Order code**|**VDS**|**RDS(on) max.**|**ID**|**PTOT**|
|---|---|---|---|---|
|STD130N6F7|60 V|5.0 mΩ|80 A|134 W|



- Among the lowest RDS(on) on the market 

- Excellent FoM (figure of merit) 

- Low Crss/Ciss ratio for EMI immunity 

- High avalanche ruggedness 

**Figure 1: Internal schematic diagram** 

## **Applications** 

- Switching applications 

**==> picture [60 x 114] intentionally omitted <==**

**----- Start of picture text -----**<br>
D(2, TAB)<br>G(1)<br>S(3)<br>**----- End of picture text -----**<br>


## **Description** 

This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low onstate resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. 

AM01475v1_Tab **Table 1: Device summary Order code Marking Package Packing** ~~ee~~ STD130N6F7 130N6F7 DPAK Tape and reel 

This is information on a product in full production. 

_www.st.com_ 

October 2016 

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|**Contents**<br>**STD130N6F7**|**Contents**<br>**STD130N6F7**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 5|
|**3**|**Test circuits ..................................................................................... 7**|
|**4**|**Package information ....................................................................... 8**|
||4.1<br>DPAK package information ............................................................... 9|
|**5**|**Revision history ............................................................................ 12**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|60|V|
|VGS|Gate-source voltage|±20|V|
|ID_(1)_|Drain current (continuous) at Tcase= 25 °C|80|A|
||Drain current (continuous) at Tcase= 100 °C|80||
|IDM_(2)_|Drain current (pulsed)|320|A|
|PTOT|Total dissipation at Tcase= 25 °C|134|W|
|EAS_(3)_|Singlepulse avalanche energy|200|mJ|
|dV/dt_(4)_|Drain-bodydiode dynamic dV/dt ruggedness|5.0|V/ns|
|Tstg|Storage temperature range|-55 to 175|°C|
|Tj|Operating junction temperature range|||



## **Notes:** 

- (1) Current is limited by package. 

- (2) Pulse width is limited by safe operating area. 

- (3) starting Tj = 25 °C, ID = 20 A, VDD = 30 V. 

- (4)ISD= 80 A; di/dt = 600 A/μs; VDD = 48 V; Tj < Tjmax 

**Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-pcb_(1)_|Thermal resistancejunction-pcb|50|°C/W|
|Rthj-amb|Thermal resistancejunction-ambient|1.12||



## **Notes:** 

(1)When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 sec 

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**STD130N6F7** 

**Electrical characteristics** 

## **2 Electrical characteristics** 

(Tcase = 25 °C unless otherwise specified) 

## **Table 4: Static** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown voltage|VGS= 0 V, ID= 1 mA|60|||V|
|IDSS|Zerogate voltage drain current|VGS= 0 V, VDS= 60 V|||1|µA|
|IGSS|Gate-bodyleakage current|VDS= 0 V, VGS= 20 V|||100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250µA|2||4|V|
|RDS(on)|Static drain-source on-resistance|VGS= 10 V, ID= 40 A||4.2|5.0|mΩ|



**Table 5: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 30 V, f = 1 MHz,<br>VGS= 0 V|-|2600|-|pF|
|Coss|Output capacitance||-|1200|-||
|Crss|Reverse transfer capacitance||-|115|-||
|Qg|Totalgate charge|VDD= 30 V, ID= 80 A,<br>VGS= 10 V (see_Figure_<br>_14: "Test circuit for gate_<br>_charge behavior"_)|-|42|-|nC|
|Qgs|Gate-source charge||-|13.6|-||
|Qgd|Gate-drain charge||-|13|-||



**Table 6: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD= 30 V, ID= 40 A,<br>RG= 4.7 Ω, VGS= 10 V<br>(see_Figure 13: "Test circuit_<br>_for resistive load switching_<br>_times"_and_Figure 18:_<br>_"Switching time waveform"_)|-|24|-|ns|
|tr|Rise time||-|44|-||
|td(off)|Turn-off delaytime||-|62|-||
|tf|Fall time||-|24|-||



**Table 7: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VSD_(1)_|Forward on voltage|VGS= 0 V, ISD= 80 A|-||1.2|V|
|trr|Reverse recoverytime|ISD= 80 A, di/dt = 100 A/µs,<br>VDD= 48 V (see_Figure 15:_<br>_"Test circuit for inductive_<br>_load switching and diode_<br>_recovery times"_)|-|50||ns|
|Qrr|Reverse recoverycharge||-|56||nC|
|IRRM|Reverse recovery current||-|2.2||A|



## **Notes:** 

(1) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. 

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**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2: Safe operating area** 

**==> picture [195 x 163] intentionally omitted <==**

**==> picture [128 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 3: Thermal impedance<br>**----- End of picture text -----**<br>


**==> picture [170 x 164] intentionally omitted <==**

**==> picture [439 x 190] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 4: Output characteristics  Figure 5: Transfer characteristics<br>**----- End of picture text -----**<br>


**==> picture [451 x 190] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 6: Gate charge vs gate-source voltage  Figure 7: Static drain-source on-resistance<br>**----- End of picture text -----**<br>


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**Electrical characteristics** 

**Figure 8: Capacitance variations** 

**==> picture [160 x 145] intentionally omitted <==**

**Figure 9: Normalized gate threshold voltage vs temperature** 

**==> picture [171 x 147] intentionally omitted <==**

**Figure 10: Normalized on-resistance vs temperature** 

**==> picture [196 x 168] intentionally omitted <==**

**Figure 11: Normalized V(BR)DSS vs temperature** 

**==> picture [186 x 157] intentionally omitted <==**

**Figure 12: Source-drain diode forward characteristics** 

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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 587] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 13: Test circuit for resistive load  Figure 14: Test circuit for gate charge<br>switching times  behavior<br>Figure 15: Test circuit for inductive load<br>Figure 16: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>Figure 18: Switching time waveform<br>Figure 17: Unclamped inductive waveform<br>**----- End of picture text -----**<br>


**==> picture [21 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
7/13<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

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**Package information** 

## **4.1 DPAK package information** 

**==> picture [219 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 19: DPAK (TO-252) type A2 package outline<br>**----- End of picture text -----**<br>


**==> picture [406 x 561] intentionally omitted <==**

**----- Start of picture text -----**<br>
0068772_type-A2_rev21<br>**----- End of picture text -----**<br>


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**Package information** 

**Table 8: DPAK (TO-252) type A2 mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|2.20||2.40|
|A1|0.90||1.10|
|A2|0.03||0.23|
|b|0.64||0.90|
|b4|5.20||5.40|
|c|0.45||0.60|
|c2|0.48||0.60|
|D|6.00||6.20|
|D1|4.95|5.10|5.25|
|E|6.40||6.60|
|E1|5.10|5.20|5.30|
|e|2.16|2.28|2.40|
|e1|4.40||4.60|
|H|9.35||10.10|
|L|1.00||1.50|
|L1|2.60|2.80|3.00|
|L2|0.65|0.80|0.95|
|L4|0.60||1.00|
|R||0.20||
|V2|0°||8°|



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**Package information** 

**Figure 20: DPAK (TO-252) type A2 recommended footprint (dimensions are in mm)** 

**==> picture [407 x 273] intentionally omitted <==**

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**STD130N6F7** 

**Revision history** 

## **5 Revision history** 

**Table 9: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|17-Dec-2015|1|First release.|
|10-Oct-2016|2|Document status changed from preliminary to production data.<br>Minor text changes.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2016 STMicroelectronics – All rights reserved 

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## Links

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