# Power MOSFET, N Channel, 24 V, 110 A, 4600 µohm, TO-252 (DPAK), Surface Mount ![Product image](https://novapart.co/image/farnell:3616833/) **URL**: https://novapart.co/products/STD110N02RT4G-VF01/power-mosfet-n-channel-24-v-110-a-4600-ohm-to-252 **SKU**: STD110N02RT4G-VF01 **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.5220 **Stock**: 10+ ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | No SVHC (15-Jan-2018) | | No. Of Pins | 3Pins | | Channel Type | N Channel | | Product Range | - | | Qualification | AEC-Q101 | | Power Dissipation | 110W | | Transistor Mounting | Surface Mount | | Rds(On) Test Voltage | 10V | | Transistor Case Style | TO-252 (DPAK) | | Drain Source Voltage Vds | 24V | | Operating Temperature Max | 175°C | | Continuous Drain Current Id | 110A | | Drain Source On State Resistance | 4600µohm | | Gate Source Threshold Voltage Max | 2V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:3616833/) ## NTD110N02R, STD110N02R MOSFET – Power, N-Channel, DPAK ~~———~~ 24 V, 110 A ## **Features** ## **http://onsemi.com** - Planar HD3e Process for Fast Switching Performance - Low R to Minimize Conduction Loss DS(on) - Low Ciss to Minimize Driver Loss - Low Gate Charge - Optimized for High Side Switching Requirements in High−Efficiency DC−DC Converters - S Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable - These Devices are Pb−Free and are RoHS Compliant ## **MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) |**MAXIMUM RATINGS**(TJ = 25J = 25= 25°C unless otherwise noted)
~~ee~~|C unless otherwise noted)
~~ee~~|C unless otherwise noted)
~~ee~~|| |---|---|---|---| |**Rating**
~~ee~~|**Symbol**
~~ee~~|**Value**
~~ee~~|**Unit**| |Drain−to−Source Voltage
~~ee ~~|VDSS
~~ee ~~|24
~~ee~~|V| |Gate−to−Source Voltage − Continuous|VGS|±20|V| |Thermal Resistance − Junction−to−Case
Total Power Dissipation @ TC= 25°C
Drain Current
− Continuous @ TC= 25°C, Chip
− Continuous @ TC= 25°C
Limited by Package
− Continuous @ TA= 25°C
Limited by Wires
− Single Pulse (tp= 10 s)
~~eT~~|R JC
PD
ID
ID
ID
ID
~~eT~~|1.35
110
110
110
32
110
~~eT~~|°C/W
W
A
A
A
A
~~eT~~| |Thermal Resistance
− Junction−to−Ambient (Note 1)
− Total Power Dissipation @ TA= 25°C
− Drain Current − Continuous @ TA= 25°C
~~eT~~|R JA
PD
ID
~~eT~~|52
2.88
17.5
~~eT~~|°C/W
W
A
~~eT~~| |Thermal Resistance
− Junction−to−Ambient (Note 2)
− Total Power Dissipation @ TA= 25°C
− Drain Current − Continuous @ TA= 25°C
~~eT~~
~~ee~~|R JA
PD
ID
~~eT~~
~~ee~~
~~ee~~|100
1.5
12.5
~~eT~~
~~ee~~
~~eee~~|°C/W
W
A
~~eT~~
~~ee~~
~~eee~~| |Operating and Storage Temperature Range
~~ee~~|TJ, Tstg
~~ee~~
~~ee~~|−55 to
175
~~ee~~
~~eee~~|°C
~~ee~~
~~eee~~| |Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ= 25°C
(VDD= 50 Vdc, VGS= 10 Vdc,
IL= 15.5 Apk, L = 1.0 mH, RG= 25 )
~~dT~~
~~ee ee~~|EAS
~~ee ~~
~~dT~~
~~ee~~|120
~~eee~~
~~dT~~
~~ee~~|mJ
~~eee~~
~~dT~~
~~ee~~| |Maximum Lead Temperature for Soldering
Purposes, (1/8″from case for 10 s)
~~ee ee~~|TL
~~ee~~|260
~~ee~~|°C
~~ee~~| 1. When surface mounted to an FR4 board using 0.5 sq in drain pad size. 2. When surface mounted to an FR4 board using the minimum recommended pad size. **==> picture [165 x 250] intentionally omitted <==** **----- Start of picture text -----**
V(BR)DSS RDS(on) TYP ID MAX
24 V 4.1 m @ 10 V 110 A
D
N−Channel
G
S
4
2
1 >
3
DPAK
CASE 369AA
(Surface Mount)
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
**----- End of picture text -----**
**==> picture [114 x 153] intentionally omitted <==** **----- Start of picture text -----**
4
Drain
OL 2
1 3
Drain
Gate Source
A = Assembly Location*
Y = Year
WW = Work Week
T110N2 = Device Code
G = Pb−Free Package
T
AYWW 110N2G
**----- End of picture text -----**
* The Assembly Location code (A) is front side optional. In cases where the Assembly Location is stamped in the package, the front side assembly code may be blank. ## **ORDERING INFORMATION** See detailed ordering and shipping information on page 5 of this data sheet. Publication Order Number: **1** © Semiconductor Components Industries, LLC, 2014 **May, 2019 − Rev. 11** **NTD110N02R/D** **NTD110N02R, STD110N02R** ## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) |**ELECTRICAL CHARACTERISTICS **(TJ= 25°C unless otherwise noted)|**ELECTRICAL CHARACTERISTICS **(TJ= 25°C unless otherwise noted)|||||| |---|---|---|---|---|---|---| |**Characteristic**||**Symbol**|**Min**|**Typ**|**Max**|**Unit**| |**OFF CHARACTERISTICS**||||||| |Drain−to−Source Breakdown Voltage (Note 3)
(VGS= 0 V, ID= 250�A)
Positive Temperature Coefficient||V(BR)DSS|24|28
15||V
mV/°C| |Zero Gate Voltage Drain Current
(VDS= 20 V, VGS= 0 V)
(VDS= 20 V, VGS= 0 V, TJ= 125°C)||IDSS|||1.5
10|�A| |Gate−Body Leakage Current (VGS=±20 V, VDS= 0 V)||IGSS|||±100|nA| |**ON CHARACTERISTICS**(Note 3)||||||| |Gate Threshold Voltage (Note 3)
(VDS= VGS, ID= 250�A)
Negative Threshold Temperature Coefficient||VGS(th)|1.0|1.5
5.0|2.0|V
mV/°C| |Static Drain−to−Source On−Resistance (Note 3)
(VGS= 10 V, ID= 110 A)
(VGS= 4.5 V, ID= 55 A)
(VGS= 10 V, ID= 20 A)
(VGS= 4.5 V, ID= 20 A)||RDS(on)||4.1
5.5
3.9
5.5|4.6
6.2|m�| |Forward Transconductance (VDS= 10 V, ID= 15 A) (Note 3)||gFS||44||Mhos| |**DYNAMIC CHARACTERISTICS**||||||| |Input Capacitance|(VDS= 20 V, VGS= 0 V, f = 1.0 MHz)|Ciss||2710|3440|pF| |Output Capacitance||Coss||1105|1670|| |Transfer Capacitance||Crss||450|640|| |**SWITCHING CHARACTERISTICS**(Note 4)||||||| |Turn−On Delay Time|(VGS= 10 V, VDD= 10 V,
ID= 40 A, RG= 3.0�)|td(on)||11|22|ns| |Rise Time||tr||39|80|| |Turn−Off Delay Time||td(off)||27|40|| |Fall Time||tf||21|40|| |Gate Charge|(VGS= 4.5 V, ID= 40 A,
VDS= 10 V) (Note 3)|QT||23.6|28|nC| |||QGS||5.1||| |||QGD||11||| |**SOURCE−DRAIN DIODE CHARACTERISTICS**||||||| |Forward On−Voltage|(IS= 20 A, VGS= 0 V) (Note 3)
(IS= 55 A, VGS= 0 V)
(IS= 20 A, VGS= 0 V, TJ= 125°C)|VSD||0.82
0.99
0.65|1.2|V| |Reverse Recovery Time|(IS= 30 A, VGS= 0 V,
dIS/dt = 100 A/�s) (Note 3)|trr||36.5||ns| |||ta||30||| |||tb||25||| |Reverse Recovery Stored Charge||Qrr||0.048||�C| Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. **http://onsemi.com** **2** **NTD110N02R, STD110N02R** **==> picture [489 x 645] intentionally omitted <==** **----- Start of picture text -----**
175 210
10 V 5 V TJ = 25 ° C VDS ≥ 10 V
8 V
150 180
6 V 4.5 V
125 150
4.2 V
100 4 V 120
3.8 V
75 3.6 V 90
3.4 V TJ = 175 ° C
50 3.2 V 3 V 60 TJ = 25 ° C
2.8 V
25 30
2.6 V
0 2.4 V 0 TJ = −55 ° C
0 2 4 6 8 10 0 2 4 6 8
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
0.03 0.014
ID = 110 A TJ = 25 ° C
T J = 25 ° C 0.012
0.01
0.02
0.008
VGS = 4.5 V
0.006
0.01
0.004
VGS = 10 V
0.002
0 0
2 4 6 8 10 20 40 60 80 100 120 140 160 180 200 220 240
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Figure 4. On−Resistance versus Drain Current
Gate−to−Source Voltage and Gate Voltage
2.0 100,000
ID = 55 A VGS = 0 V
1.8 VGS = 10 V 10,000 TJ = 175 ° C
1.6
1.4
1000
1.2
1.0
100
0.8 TJ = 100 ° C
0.6 10
−50 −25 0 25 50 75 100 125 150 175 0 5.0 10 15 20 25
TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current
Temperature versus Voltage
, DRAIN CURRENT (AMPS) , DRAIN CURRENT (AMPS)
ID ID
) � ) �
, DRAIN−TO−SOURCE RESISTANCE ( , DRAIN−TO−SOURCE RESISTANCE (
DS(on) DS(on)
R R
, LEAKAGE (nA)
(NORMALIZED) IDSS
, DRAIN−TO−SOURCE RESISTANCE
DS(on)
R
**----- End of picture text -----**
**http://onsemi.com** **3** **NTD110N02R, STD110N02R** **==> picture [492 x 627] intentionally omitted <==** **----- Start of picture text -----**
5000 5 20
VDS = 0 V VGS = 0 V TJ = 25 ° C QT
4000 Ciss 4 16
VGS
3000 3 QGS QDS 12
Ciss VDS
2000 2 8
C rss
1000 Coss 1 4
ID = 40 A
0 Crss 0 TJ = 25 ° C 0
10 5 0 5 10 15 20 0 5 10 15 20 25
VGS VDS Qg, TOTAL GATE CHARGE (nC)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
1000 120
VDS = 10 V VGS = 0 V
ID = 55 A td(off) 100 TJ = 25 ° C
VGS = 10 V
tf
100 80
tr
60
10 td(on) 40
20
1 0
1 10 100 0.4 0.6 0.8 1.0 1.2
RG, GATE RESISTANCE ( � ) VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Variation Figure 10. Diode Forward Voltage versus
versus Gate Resistance Current
1000
VGS = 20 V
SINGLE PULSE
TC = 25 ° C
100
1 ms
10 ms
10
RDS(on) Limit dc
Thermal Limit
Package Limit
1.0
0.1 1.0 10 100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
DS
C, CAPACITANCE (pF)
, GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
V , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
t, TIME (ns)
, SOURCE CURRENT (AMPS)
IS
, DRAIN CURRENT (AMPS)
ID
**----- End of picture text -----**
**Figure 11. Maximum Rated Forward Biased Safe Operating Area** **http://onsemi.com** **4** **NTD110N02R, STD110N02R** **==> picture [490 x 175] intentionally omitted <==** **----- Start of picture text -----**
1.0
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01 Single Pulse
0.00001 0.0001 0.001 0.01 0.1 1.0 10
t, TIME (s)
RESISTANCE (NORMALIZED)
r(t), EFFECTIVE TRANSIENT THERMAL
**----- End of picture text -----**
**Figure 12. Thermal Response** ## **ORDERING INFORMATION** |**ORDERING INFORMATION**||| |---|---|---| |**Device**|**Package**|**Shipping**†| |NTD110N02RT4G|DPAK
(Pb−Free)|2500 / Tape & Reel| |STD110N02RT4G*|DPAK
(Pb−Free)|2500 / Tape & Reel| - †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. - *S Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable. **http://onsemi.com** **5** MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 4 1[2] 3 ## **DPAK−3 6.10x6.54x2.28, 2.29P** CASE 369AA ISSUE C DATE 14 MAY 2026 ## **SCALE 1:1** ## **GENERIC MARKING DIAGRAM*** **==> picture [493 x 118] intentionally omitted <==** **----- Start of picture text -----**
XXXXXXG YWW
XXXXXX = Device Code
ALYWW XXX
A = Assembly Location
XXXXXG *This information is generic. Please refer to
L = Wafer Lot device data sheet for actual part marking.
Y = Year Pb−Free indicator, “G” or microdot “ � ”, may
WW = Work Week or may not be present. Some products may
IC Discrete G = Pb−Free Package not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON13126D Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: DPAK−3 6.10x6.54x2.28, 2.29P PAGE 1 OF 1
**----- End of picture text -----**
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