# Power MOSFET, N Channel, 100 V, 13 A, 0.13 ohm, TO-252 (DPAK), Surface Mount

![Product image](https://novapart.co/image/farnell:1175682/)

**URL**: https://novapart.co/products/STD10NF10T4/power-mosfet-n-channel-100-v-13-a-013-ohm-to-252
**SKU**: STD10NF10T4
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.4900
**Stock**: 1000+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:13A; Drain Source Voltage Vds:100V; On Resistance Rds(on):0.13ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:3V; Power D

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 50W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 100V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 13A |
| Drain Source On State Resistance | 0.13ohm |
| Gate Source Threshold Voltage Max | 3V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:1175682/)

## **STD10NF10T4** 

## N-channel 100 V, 0.115 Ω typ., 13 A STripFET™ II Power MOSFET in a DPAK package 

Datasheet - production data 

## **Features** 

|**Order code**|**VDS**|**RDS(on) max.**|**ID**|
|---|---|---|---|
|STD10NF10T4|100 V|0.130 Ω|13 A|



- Exceptional dv/dt capability 

- Application oriented characterization 

## **Applications** 

**Figure 1: Internal schematic diagram** 

- Switching applications 

## **Description** 

**==> picture [60 x 114] intentionally omitted <==**

**----- Start of picture text -----**<br>
D(2, TAB)<br>G(1)<br>S(3)<br>**----- End of picture text -----**<br>


This Power MOSFET series realized with STMicroelectronics unique STripFET™ process is specifically designed to minimize input capacitance and gate charge. It is therefore ideal as a primary switch in advanced high-efficiency isolated DC-DC converters for Telecom and Computer applications. It is also suitable for any application with low gate charge drive requirements. 

AM01475v1_Tab **Table 1: Device summary Order code Marking Package Packing** ~~[SS~~ STD10NF10T4 D10NF10 DPAK Tape and reel 

This is information on a product in full production. 

_www.st.com_ 

April 2016 

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|**Contents**<br>**STD10NF10T4**|**Contents**<br>**STD10NF10T4**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.2<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>DPAK (TO-252) type A package information..................................... 9|
||4.2<br>DPAK (TO-252) type C package information .................................. 11|
||4.3<br>Packing information ......................................................................... 14|
|**5**|**Revision history ............................................................................ 16**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|100|V|
|VDGR|Drain-gate voltage (RGS= 20 kΩ)|100|V|
|VGS|Gate-source voltage|±20|V|
|ID|Drain current (continuous) at TC= 25 °C|13|A|
|ID|Drain current (continuous) at TC= 100 °C|9|A|
|IDM<br>_(1)_|Drain current (pulsed)|52|A|
|PTOT|Total dissipation at TC= 25 °C|50|W|
|EAS<br>_(2)_|Singlepulse avalanche energy|70|mJ|
|dv/dt_(3)_|Peak diode recoveryvoltage slope|9|V/ns|
|Tj|Operating junction temperature range|- 55 to 175|°C|
|Tstg|Storage temperature range|||



## **Notes:** 

- (1) Pulse width limited by safe operating area. 

(2) Starting TJ = 25 °C, ID = 13 A, VDD = 50 V 

(3) ISD ≤ 13 A, di/dt ≤ 300 A/µs; VDS peak < V(BR)DSS, TJ ≤ TJMAX 

**Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case|3|°C/W|
|Rthj-pcb<br>_(1)_|Thermal resistancejunction-pcb|50|°C/W|



## **Notes:** 

(1)When mounted on 1 inch² FR-4, 2 Oz copper board 

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**STD10NF10T4** 

**Electrical characteristics** 

## **2 Electrical characteristics** 

TC = 25 ° C unless otherwise specified 

**Table 4: On/off-state** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown voltage|VGS= 0 V, ID= 250µA|100|||V|
|IDSS|Zero gate voltage drain current|VGS= 0 V, VDS= 100 V|||1|µA|
|||VGS= 0 V, VDS= 100 V<br>TC= 125 °C_(1)_|||10|µA|
|IGSS|Gate bodyleakage current|VDS=0 V, VGS±20 V|||± 100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250µA|2|3|4|V|
|RDS(on)|Static drain-source on-resistance|VGS= 10 V, ID= 5 A||0.115|0.130|Ω|



## **Notes:** 

(1) Defined by design, not subject to production test. 

**Table 5: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 25 V, f = 1 MHz,<br>VGS= 0 V|-|460||pF|
|Coss|Output capacitance||-|70||pF|
|Crss|Reverse transfer<br>capacitance||-|30||pF|
|Qg|Totalgate charge|VDD= 80 V, ID= 10 A<br>VGS= 10 V<br>(see_Figure 14: "Test circuit_<br>_for gate charge behavior")_|-|15.3|21_(1)_|nC|
|Qgs|Gate-source charge||-|3.7||nC|
|Qgd|Gate-drain charge||-|4.7||nC|



## **Notes:** 

(1) Defined by design, not subject to production test. 

**Table 6: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDD= 50 V, ID= 5 A, RG= 4.7 Ω<br>VGS= 10 V<br>(see_Figure 13: "Test circuit for_<br>_resistive load switching times")_|-|16|-|ns|
|tr|Rise time||-|25|-|ns|
|td(off)|Turn-off delaytime||-|32|-|ns|
|tf|Fall time||-|8|-|ns|



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**Electrical characteristics** 

## **Table 7: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain<br>current||-||13|A|
|ISDM<br>_(1)_|Source-drain<br>current (pulsed)||-||52|A|
|VSD<br>_(2)_|Forward on<br>voltage|ISD= 10 A, VGS= 0 V|-||1.5|V|
|trr|Reverse recovery<br>time|ISD= 10 A, di/dt = 100 A/µs,<br>VDD= 50 V, Tj= 150 °C<br>(see_Figure 15: "Test circuit for_<br>_inductive load switching and diode_<br>_recovery times")_|-|90||ns|
|Qrr|Reverse recovery<br>charge||-|230||nC|
|IRRM|Reverse recovery<br>current||-|5||A|



## **Notes:** 

(1) Pulse width limited by safe operating area 

(2) Pulsed: pulse duration = 300 µ s, duty cycle 1.5% 

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**Electrical characteristics** 

## **2.2 Electrical characteristics (curves)** 

**Figure 2: Safe operating area** 

**Figure 3: Thermal impedance** 

**==> picture [404 x 159] intentionally omitted <==**

**Figure 4: Output characteristics** 

**==> picture [198 x 159] intentionally omitted <==**

**Figure 5: Transfer characteristics** 

**==> picture [177 x 148] intentionally omitted <==**

**----- Start of picture text -----**<br>
9<br>**----- End of picture text -----**<br>


**Figure 6: Gate charge vs gate-source voltage** 

**Figure 7: Static drain-source on-resistance** 

**==> picture [406 x 159] intentionally omitted <==**

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**Electrical characteristics** 

**Figure 8: Capacitance variations** 

**Figure 9: Normalized gate threshold voltage vs temperature** 

**==> picture [406 x 173] intentionally omitted <==**

**Figure 10: Normalized on-resistance vs Figure 11: Normalized V(BR)DSS vs temperature temperature** 

**==> picture [405 x 159] intentionally omitted <==**

**Figure 12: Source-drain diode forward characteristics** 

**==> picture [198 x 151] intentionally omitted <==**

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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 376] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 13: Test circuit for resistive load  Figure 14: Test circuit for gate charge<br>switching times  behavior<br>Figure 15: Test circuit for inductive load  Figure 16: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>**----- End of picture text -----**<br>


**==> picture [403 x 170] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 17: Unclamped inductive waveform  Figure 18: Switching time waveform<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

## **4.1 DPAK (TO-252) type A package information** 

**Figure 19: DPAK (TO-252) type A package outline** 

**==> picture [406 x 440] intentionally omitted <==**

**----- Start of picture text -----**<br>
0068772_A_21<br>**----- End of picture text -----**<br>


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**Package information** 

|**formation**|**STD10NF10T4**|**STD10NF10T4**|**STD10NF10T4**|
|---|---|---|---|
||**Table 8: DPAK(TO-252) type A mechanical data**|||
|**Dim.**||**mm**||
||**Min.**|**Typ.**|**Max.**|
|A|2.20||2.40|
|A1|0.90||1.10|
|A2|0.03||0.23|
|b|0.64||0.90|
|b4|5.20||5.40|
|c|0.45||0.60|
|c2|0.48||0.60|
|D|6.00||6.20|
|D1|4.95|5.10|5.25|
|E|6.40||6.60|
|E1|4.60|4.70|4.80|
|e|2.16|2.28|2.40|
|e1|4.40||4.60|
|H|9.35||10.10|
|L|1.00||1.50|
|(L1)|2.60|2.80|3.00|
|L2|0.65|0.80|0.95|
|L4|0.60||1.00|
|R||0.20||
|V2|0°||8°|



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**Package information** 

## **4.2 DPAK (TO-252) type C package information** 

**Figure 20: DPAK (TO-252) type C package outline** 

**==> picture [406 x 475] intentionally omitted <==**

**----- Start of picture text -----**<br>
0068772_C_21<br>**----- End of picture text -----**<br>


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**Package information** 

## **Table 9: DPAK (TO-252) type C mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|2.20|2.30|2.38|
|A1|0.90|1.01|1.10|
|A2|0.00||0.10|
|b|0.72||0.85|
|b4|5.13|5.33|5.46|
|c|0.47||0.60|
|c2|0.47||0.60|
|D|6.00|6.10|6.20|
|D1|5.25|||
|E|6.50|6.60|6.70|
|E1|4.70|||
|e|2.186|2.286|2.386|
|H|9.80|10.10|10.40|
|L|1.40|1.50|1.70|
|L1||2.90 REF||
|L2|0.90||1.25|
|L3||0.51 BSC||
|L4|0.60|0.80|1.00|
|L6||1.80 BSC||
|θ1|5°|7°|9°|
|θ2|5°|7°|9°|
|V2|0°||8°|



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**Package information** 

**Figure 21: DPAK (TO-252) recommended footprint (dimensions are in mm)** 

**==> picture [406 x 275] intentionally omitted <==**

**----- Start of picture text -----**<br>
FP_0068772_21<br>**----- End of picture text -----**<br>


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**Package information** 

## **4.3 Packing information** 

**Figure 22: DPAK (TO-252) tape outline** 

~~©~~ 14/17 DocID029150 Rev 1 

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**Package information** 

**Figure 23: DPAK (TO-252) reel outline** 

**Table 10: DPAK (TO-252) tape and reel mechanical data** 

|**Tape**|**Tape**|**Tape**|**Reel**|**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Dim.**|**mm**||**Dim.**|**mm**||
||**Min.**|**Max.**||**Min.**|**Max.**|
|A0|6.8|7|A||330|
|B0|10.4|10.6|B|1.5||
|B1||12.1|C|12.8|13.2|
|D|1.5|1.6|D|20.2||
|D1|1.5||G|16.4|18.4|
|E|1.65|1.85|N|50||
|F|7.4|7.6|T||22.4|
|K0|2.55|2.75||||
|P0|3.9|4.1|Baseqty.||2500|
|P1|7.9|8.1|Bulkqty.||2500|
|P2|1.9|2.1||||
|R|40|||||
|T|0.25|0.35||||
|W|15.7|16.3||||



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**Revision history** 

## **5 Revision history** 

**Table 11: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|06-Apr-2016|1|First release.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2016 STMicroelectronics – All rights reserved 

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- [Supplier page](https://es.farnell.com/stmicroelectronics/std10nf10t4/mosfet-n-ch-100v-13a-dpak/dp/1175682)
---

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