# Power MOSFET, N Channel, 800 V, 8 A, 0.55 ohm, TO-252 (DPAK), Surface Mount

![Product image](https://novapart.co/image/farnell:4036290RL/)

**URL**: https://novapart.co/products/STD10LN80K5/power-mosfet-n-channel-800-v-8-a-055-ohm-to-252
**SKU**: STD10LN80K5
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.1300
**Stock**: 1000+
**Lead Time**: 2 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | MDmesh K5 Series |
| Qualification | - |
| Power Dissipation | 110W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 800V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 8A |
| Drain Source On State Resistance | 0.55ohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:4036290RL/)

## **STD10LN80K5** 

## N-channel 800 V, 0.55 Ω typ., 8 A MDmesh™ K5 Power MOSFET in a DPAK package 

Datasheet - production data 

## **Features** 

|**Order code**|**VDS**|**RDS(on) max.**|**ID**|
|---|---|---|---|
|STD10LN80K5|800 V|0.63 Ω|8 A|



- Industry’s lowest RDS(on) x area 

- Industry’s best FoM (figure of merit) 

- Ultra-low gate charge  100% avalanche tested 

- Zener-protected 

**Figure 1: Internal schematic diagram** 

## **Applications** 

- Switching applications 

## **Description** 

This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. 

**Table 1: Device summary** 

|**Order code**|**Marking**|**Package**|**Packing**|
|---|---|---|---|
|STD10LN80K5|10LN80K5|DPAK|Tape and reel|



March 2016 

DocID029039 Rev 1 

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This is information on a product in full production. 

_www.st.com_ 

|**Contents**<br>**STD10LN80K5**|**Contents**<br>**STD10LN80K5**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 9**|
|**4**|**Package information ..................................................................... 10**|
||4.1<br>DPAK (TO-252) type A2 package information................................. 11|
||4.2<br>Packing information ......................................................................... 14|
|**5**|**Revision history ............................................................................ 16**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VGS|Gate-source voltage|± 30|V|
|ID|Drain current (continuous) at TC= 25 °C|8|A|
|ID|Drain current (continuous) at TC= 100 °C|5|A|
|ID<br>_(1)_|Drain current (pulsed)|32|A|
|PTOT|Total dissipation at TC= 25 °C|110|W|
|dv/dt_(2)_|Peak diode recoveryvoltage slope|4.5|V/ns|
|dv/dt_(3)_|MOSFET dv/dt ruggedness|50||
|Tj|Operating junction temperature range|- 55 to 150|°C|
|Tstg|Storage temperature range|||



## **Notes:** 

(1) Pulse width limited by safe operating area. 

(2) ISD ≤ 8 A, di/dt ≤ 100 A/µs; VDS peak < V(BR)DSS, VDD=640 V 

(3) VDS ≤ 640 V 

**Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case|1.14|°C/W|
|Rthj-pcb<br>_(1)_|Thermal resistance junction-pcb|50|°C/W|



## **Notes:** 

(1)When mounted on FR-4 board of 1 inch² , 2 oz Cu 

**Table 4: Avalanche characteristics** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|IAR|Avalanche current, repetitive or not repetitive<br>(pulse width limited by Tjmax)|2.7|A|
|EAS|Single pulse avalanche energy (starting Tj= 25 ° C,<br>ID= IAR, VDD= 50 V)|240|mJ|



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**Electrical characteristics** 

## **2 Electrical characteristics** 

TC = 25 ° C unless otherwise specified 

**Table 5: On/off-state** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown voltage|VGS= 0 V, ID= 1 mA|800|||V|
|IDSS|Zero gate voltage drain current|VGS= 0 V, VDS= 800 V|||1|µA|
|||VGS= 0 V, VDS= 800 V<br>TC= 125 °C_(1)_|||50|µA|
|IGSS|Gate bodyleakage current|VDS= 0 V, VGS= ± 20 V|||± 10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 100µA|3|4|5|V|
|RDS(on)|Static drain-source on-resistance|VGS= 10 V, ID= 4 A||0.55|0.63|Ω|



## **Notes:** 

(1) Defined by design, not subject to production test. 

**Table 6: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 100 V, f = 1 MHz,<br>VGS= 0 V|-|427|-|pF|
|Coss|Output capacitance||-|43|-|pF|
|Crss|Reverse transfer capacitance||-|0.25|-|pF|
|Co(tr)<br>_(1)_|Equivalent capacitance time<br>related|VDS= 0 to 640 V, VGS= 0 V|-|72|-|pF|
|Co(er)<br>_(2)_|Equivalent capacitance<br>energyrelated|||27|-|pF|
|Rg|Intrinsicgate resistance|f = 1 MHz , ID= 0 A|-|7|-|Ω|
|Qg|Totalgate charge|VDD= 640 V, ID= 8 A<br>VGS= 10 V<br>See_Figure 16: "Test circuit_<br>_for gate charge behavior"_|-|15|-|nC|
|Qgs|Gate-source charge||-|4.2|-|nC|
|Qgd|Gate-drain charge||-|9|-|nC|



## **Notes:** 

(1) Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 

(2)Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 

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**Electrical characteristics** 

## **Table 7: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDD= 400 V, ID= 4 A, RG= 4.7 Ω<br>VGS= 10 V<br>See_Figure 15: "Test circuit for_<br>_resistive load switching times"_and<br>_Figure 20: "Switching time_<br>_waveform"_|-|11.8|-|ns|
|tr|Rise time||-|10|-|ns|
|td(off)|Turn-off delaytime||-|28|-|ns|
|tf|Fall time||-|13|-|ns|



## **Table 8: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||8|A|
|ISDM<br>_(1)_|Source-drain current<br>(pulsed)||-||32|A|
|VSD<br>_(2)_|Forward on voltage|ISD= 8 A, VGS= 0 V|-||1.5|V|
|trr|Reverse recoverytime|ISD= 8 A, di/dt = 100 A/µs,<br>VDD= 60 V<br>See_Figure 17: "Test circuit for_<br>_inductive load switching and diode_<br>_recovery times"_|-|350||ns|
|Qrr|Reverse recovery<br>charge||-|3.9||µC|
|IRRM|Reverse recovery<br>current||-|22.5||A|
|trr|Reverse recoverytime|ISD= 8 A, di/dt = 100 A/µs,<br>VDD= 60 V, Tj= 150 °C<br>See_Figure 17: "Test circuit for_<br>_inductive load switching and diode_<br>_recovery times"_|-|505||ns|
|Qrr|Reverse recovery<br>charge||-|5||µC|
|IRRM|Reverse recovery<br>current||-|20||A|



## **Notes:** 

(1) Pulse width limited by safe operating area 

(2) Pulsed: pulse duration = 300 µ s, duty cycle 1.5% 

**Table 9: Gate-source Zener diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)GSO|Gate-source breakdown voltage|IGS= ± 1mA, ID= 0 A|30|-|-|V|



The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry. 

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**Electrical characteristics** 

## **2.2 Electrical characteristics (curves)** 

**==> picture [416 x 354] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 2: Safe operating area  Figure 3: Thermal impedance<br>Figure 4: Output characteristics  Figure 5: Transfer characteristics<br>**----- End of picture text -----**<br>


**==> picture [403 x 180] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 6: Gate charge vs gate-source voltage  Figure 7: Static drain-source on-resistance<br>**----- End of picture text -----**<br>


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**Electrical characteristics** 

**Figure 8: Capacitance variations** 

**==> picture [159 x 144] intentionally omitted <==**

**==> picture [191 x 20] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 9: Normalized gate threshold voltage<br>vs temperature<br>**----- End of picture text -----**<br>


**==> picture [166 x 142] intentionally omitted <==**

**==> picture [416 x 375] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 10: Normalized on-resistance vs  Figure 11: Normalized V(BR)DSS vs temperature<br>temperature<br>Figure 12: Output capacitance stored energy  Figure 13: Source-drain diode forward<br>characteristics<br>**----- End of picture text -----**<br>


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## **Electrical characteristics** 

**Figure 14: Maximum avalanche energy vs starting TJ** 

**==> picture [157 x 142] intentionally omitted <==**

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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 377] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 15: Test circuit for resistive load  Figure 16: Test circuit for gate charge<br>switching times  behavior<br>Figure 17: Test circuit for inductive load  Figure 18: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>**----- End of picture text -----**<br>


**Figure 19: Unclamped inductive waveform Figure 20: Switching time waveform** 

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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

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**Package information** 

## **4.1 DPAK (TO-252) type A2 package information** 

**==> picture [219 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 21: DPAK (TO-252) type A2 package outline<br>**----- End of picture text -----**<br>


**==> picture [406 x 561] intentionally omitted <==**

**----- Start of picture text -----**<br>
0068772_type-A2_rev21<br>**----- End of picture text -----**<br>


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**Package information** 

**Table 10: DPAK (TO-252) type A2 mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|2.20||2.40|
|A1|0.90||1.10|
|A2|0.03||0.23|
|b|0.64||0.90|
|b4|5.20||5.40|
|c|0.45||0.60|
|c2|0.48||0.60|
|D|6.00||6.20|
|D1|4.95|5.10|5.25|
|E|6.40||6.60|
|E1|5.10|5.20|5.30|
|e|2.16|2.28|2.40|
|e1|4.40||4.60|
|H|9.35||10.10|
|L|1.00||1.50|
|L1|2.60|2.80|3.00|
|L2|0.65|0.80|0.95|
|L4|0.60||1.00|
|R||0.20||
|V2|0°||8°|



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**Package information** 

**Figure 22: DPAK (TO-252) recommended footprint (dimensions are in mm)** 

**==> picture [329 x 281] intentionally omitted <==**

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## **Package information** 

## **4.2 Packing information** 

**Figure 23: DPAK (TO-252) tape outline** 

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**Package information** 

**Figure 24: DPAK (TO-252) reel outline** 

**Table 11: DPAK (TO-252) tape and reel mechanical data** 

|**Tape**|**Tape**|**Tape**|**Reel**|**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Dim.**|**mm**||**Dim.**|**mm**||
||**Min.**|**Max.**||**Min.**|**Max.**|
|A0|6.8|7|A||330|
|B0|10.4|10.6|B|1.5||
|B1||12.1|C|12.8|13.2|
|D|1.5|1.6|D|20.2||
|D1|1.5||G|16.4|18.4|
|E|1.65|1.85|N|50||
|F|7.4|7.6|T||22.4|
|K0|2.55|2.75||||
|P0|3.9|4.1|Baseqty.||2500|
|P1|7.9|8.1|Bulkqty.||2500|
|P2|1.9|2.1||||
|R|40|||||
|T|0.25|0.35||||
|W|15.7|16.3||||



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**Revision history** 

## **5 Revision history** 

**Table 12: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|09-Mar-2016|1|First release.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2016 STMicroelectronics – All rights reserved 

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