# Power MOSFET, N Channel, 100 V, 80 A, 6800 µohm, TO-252 (DPAK), Surface Mount

![Product image](https://novapart.co/image/farnell:3132716/)

**URL**: https://novapart.co/products/STD105N10F7AG/power-mosfet-n-channel-100-v-80-a-6800-ohm-to-252
**SKU**: STD105N10F7AG
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.9220
**Stock**: 1000+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:80A; Drain Source Voltage Vds:100V; On Resistance Rds(on):0.0068ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | STripFET F7 |
| Qualification | AEC-Q101 |
| Power Dissipation | 120W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 100V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 80A |
| Drain Source On State Resistance | 6800µohm |
| Gate Source Threshold Voltage Max | 4.5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3132716/)

## **STD105N10F7AG** 

Automotive-grade N-channel 100 V, 6.8 mΩ typ., 80 A, STripFET™ F7 Power MOSFET in a DPAK package 

Datasheet - production data 

## **Features** 

|**Order code**|**VDS**|**RDS(on) max.**|ID|PTOT|
|---|---|---|---|---|
|STD105N10F7AG 100 V|STD105N10F7AG 100 V|8 mΩ|80 A 120 W|80 A 120 W|



- Designed for automotive applications and AEC-Q101 qualified 

- Among the lowest RDS(on) on the market 

- Excellent FoM (figure of merit) 

- Low Crss/Ciss ratio for EMI immunity 

**Figure 1: Internal schematic diagram** 

- High avalanche ruggedness 

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D(2, TAB)<br>G(1)<br>S(3)<br>AM01475v1_Tab<br>**----- End of picture text -----**<br>


## **Applications** 

- Switching applications 

## **Description** 

This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low onstate resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. 

**Table 1: Device summary Order code Marking Package Packing** STD105N10F7AG 105N10F7 DPAK Tape and reel ~~——[SS]~~ June 2016 DocID027071 Rev 4 1/14 

This is information on a product in full production. 

_www.st.com_ 

**Contents** 

**STD105N10F7AG** 

## **Contents** 

|**1**|**Electrical ratings ............................................................................. 3**|
|---|---|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>DPAK (TO-252) type A2 package information................................. 10|
|**5**|**Revision history ............................................................................ 13**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage|100|V|
|VGS|Gate-source voltage|± 20|V|
|ID|Drain current (continuous) at TC= 25 °C|80|A|
|ID|Drain current (continuous) at TC= 100 °C|62|A|
|IDM_(1)_|Drain current (pulsed)|320|A|
|PTOT|Total dissipation at TC= 25 °C|120|W|
|Tstg|Storage temperature range|-55 to 175|°C|
|TJ|Operationjunction temperature range|||



**Notes:** 

- (1)Pulse width limited by safe operating area. 

## **Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case|1.25|°C/W|
|Rthj-pcb_(1)_|Thermal resistancejunction-pcb|50||



## **Notes:** 

- (1)When mounted on FR-4 board of 1 inch², 2oz Cu. 

**Table 4: Avalanche characteristics** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|EAS|Single pulse avalanche energy<br>TJ= 25 °C, L = 3.5 mH, IAS= 15 A, VDD= 50 V, VGS= 10 V|400|mJ|



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**Electrical characteristics** 

## **2 Electrical characteristics** 

(TCASE = 25 °C unless otherwise specified) 

**Table 5: On/Off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage (VGS= 0)|ID= 250 μA|100|||V|
|IDSS|Zero gate voltage<br>drain current (VGS= 0)|VDS= 100 V|||1|µA|
|||VDS= 100 V, TC= 125 °C_(1)_|||100|µA|
|IGSS|Gate body leakage<br>current (VDS= 0)|VGS= ± 20 V|||± 100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 μA|2.5||4.5|V|
|RDS(on)|Static drain-source<br>on-resistance|VGS= 10 V, ID= 40 A||6.8|8|mΩ|



## **Notes:** 

(1)Defined by design, not subject to production test. 

**Table 6: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 50 V, f = 1 MHz,<br>VGS= 0 V|-|4369|-|pF|
|Coss|Output capacitance||-|823|-|pF|
|Crss|Reverse transfer<br>capacitance||-|36|-|pF|
|Qg|Totalgate charge|VDD= 50 V, ID= 80 A,<br>VGS= 10 V<br>(see_Figure 14: "Test circuit for_<br>_gate charge behavior"_)|-|61|-|nC|
|Qgs|Gate-source charge||-|26|-|nC|
|Qgd|Gate-drain charge||-|13|-|nC|



**Table 7: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD= 50 V, ID= 40 A,<br>RG= 4.7 Ω, VGS= 10 V<br>(see_Figure 13: "Test circuit for_<br>_resistive load switching times"_<br>and_Figure 18: "Switching time_<br>_waveform"_)|-|27|-|ns|
|tr|Rise time||-|40|-|ns|
|td(off)|Turn-off delay time||-|46|-|ns|
|tf|Fall time||-|15|-|ns|



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**Electrical characteristics** 

**Table 8: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||80|A|
|ISDM_(1)_|Source-drain current (pulsed)||-||320|A|
|VSD_(2)_|Forward on voltage|ISD= 80 A, VGS= 0 V|-||1.2|V|
|trr|Reverse recoverytime|ISD= 80 A, di/dt = 100 A/µs<br>VDD= 80 V, Tj= 150 °C|-|77||ns|
|Qrr|Reverse recovery charge||-|146||nC|
|IRRM|Reverse recovery current||-|4||A|



## **Notes:** 

(1)Pulse width limited by safe operating area. 

(2)Pulsed: pulse duration = 300 µs, duty cycle 1.5 %. 

DocID027071 Rev 4 

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**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2: Safe operating area** 

**==> picture [157 x 139] intentionally omitted <==**

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Figure 3: Thermal impedance<br>**----- End of picture text -----**<br>


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**Figure 4: Output characteristics** 

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**Figure 5: Transfer characteristics** 

**==> picture [150 x 141] intentionally omitted <==**

**Figure 6: Normalized V(BR)DSS vs temperature** 

**==> picture [159 x 141] intentionally omitted <==**

**Figure 7: Static drain-source on-resistance** 

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**Electrical characteristics** 

**Figure 8: Gate charge vs gate-source voltage Figure 9: Capacitance variations** 

**Figure 10: Normalized gate threshold voltage Figure 11: Normalized on-resistance vs vs temperature temperature** 

**Figure 12: Source-drain diode forward characteristics** 

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**Test circuits** 

## **3 Test circuits** 

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**----- Start of picture text -----**<br>
Figure 13: Test circuit for resistive load  Figure 14: Test circuit for gate charge<br>switching times  behavior<br>Figure 15: Test circuit for inductive load  Figure 16: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>Figure 18: Switching time waveform<br>Figure 17: Unclamped inductive waveform<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

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**Package information** 

## **4.1 DPAK (TO-252) type A2 package information** 

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Figure 19: DPAK (TO-252) type A2 package outline<br>**----- End of picture text -----**<br>


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0068772_type-A2_rev21<br>**----- End of picture text -----**<br>


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**Package information** 

**Table 9: DPAK (TO-252) type A2 mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|2.20||2.40|
|A1|0.90||1.10|
|A2|0.03||0.23|
|b|0.64||0.90|
|b4|5.20||5.40|
|c|0.45||0.60|
|c2|0.48||0.60|
|D|6.00||6.20|
|D1|4.95|5.10|5.25|
|E|6.40||6.60|
|E1|5.10|5.20|5.30|
|e|2.16|2.28|2.40|
|e1|4.40||4.60|
|H|9.35||10.10|
|L|1.00||1.50|
|L1|2.60|2.80|3.00|
|L2|0.65|0.80|0.95|
|L4|0.60||1.00|
|R||0.20||
|V2|0°||8°|



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**Package information** 

**Figure 20: DPAK (TO-252) recommended footprint (dimensions are in mm)** 

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**Revision history** 

## **5 Revision history** 

**Table 10: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|23-Oct-2014|1|First release.|
|30-Oct-2014|2|Document statuspromoted frompreliminarytoproduction data.|
|20-May-2016|3|Updated Section 4.1: "DPAK (TO-252) type A2 package information".<br>Minor text changes.|
|03-Jun-2016|4|Updated title and features in cover page.<br>Updated_Table 5: "On/Off states"_.<br>Minor text changes.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2016 STMicroelectronics – All rights reserved 

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## Links

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- [Supplier page](https://es.farnell.com/stmicroelectronics/std105n10f7ag/mosfet-aec-q101-n-ch-100v-80a/dp/3132716)
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