# Power MOSFET, N Channel, 900 V, 8 A, 0.6 ohm, TO-263 (D2PAK), Surface Mount

![Product image](https://novapart.co/image/farnell:2729653/)

**URL**: https://novapart.co/products/STB8N90K5/power-mosfet-n-channel-900-v-8-a-06-ohm-to-263
**SKU**: STB8N90K5
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.2100
**Stock**: 10+

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:8A; Drain Source Voltage Vds:900V; On Resistance Rds(on):0.6ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4V; P

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 130W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-263 (D2PAK) |
| Drain Source Voltage Vds | 900V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 8A |
| Drain Source On State Resistance | 0.6ohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2729653/)

## **STB8N90K5** 

## N-channel 900 V, 0.60 Ω typ., 8 A MDmesh™ K5 Power MOSFET in a D[2] PAK package 

Datasheet - production data 

## **Features** 

**==> picture [79 x 100] intentionally omitted <==**

**----- Start of picture text -----**<br>
TAB<br>2<br>3<br>1<br>D²PAK<br>**----- End of picture text -----**<br>


|**Order code**|**VDS**|**RDS(on) max.**|**ID**|
|---|---|---|---|
|STB8N90K5|900 V|0.68 Ω|8 A|



- Industry’s lowest RDS(on) x area 

- Industry’s best FoM (figure of merit) 

- Ultra-low gate charge 

- 100% avalanche tested 

- Zener-protected 

## **Applications** 

**Figure 1: Internal schematic diagram** 

- Switching applications 

## **Description** 

This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. 

|**Order code**|**Marking**|**Package**|**Packing**|
|---|---|---|---|
|STB8N90K5|8N90K5|D2PAK|Tape and reel|



November 2016 

DocID030104 Rev 1 

1/15 

This is information on a product in full production. 

_www.st.com_ 

|**Contents**<br>**STB8N90K5**|**Contents**<br>**STB8N90K5**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>D²PAK (TO-263) type A package information ................................... 9|
||4.2<br>D²PAK packing information ............................................................. 12|
|**5**|**Revision history ............................................................................ 14**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VGS|Gate-source voltage|±30|V|
|ID_(1)_|Drain current (continuous) at TC= 25 °C|8|A|
|ID_(1)_|Drain current (continuous) at TC= 100 °C|5|A|
|ID_(2)_|Drain currentpulsed|32|A|
|PTOT|Total dissipation at TC= 25 °C|130|W|
|dv/dt_(3)_|Peak diode recoveryvoltage slope|4.5|V/ns|
|dv/dt_(4)_|MOSFET dv/dt ruggedness|50||
|TJ|Operating junction temperature range|-55 to 150|°C|
|Tstg|Storage temperature range|||



## **Notes:** 

(1)Limited by maximum junction temperature 

(2)Pulse width limited by safe operating area 

(3)ISD ≤ 8 A, di/dt ≤ 100 A/μs; VDS peak ≤ V(BR)DSS 

(4)VDS ≤ 720 V 

**Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case|0.96|°C/W|
|Rthj-pcb_(1)_|Thermal resistancejunction-pcb|30|°C/W|



## **Notes:** 

(1)When mounted on FR-4 board of 1 inch², 2 oz Cu 

**Table 4: Avalanche characteristics** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|IAR|Avalanche current, repetitive or not repetitive<br>(pulse width limited byTJmax)|2.7|A|
|EAS|Single pulse avalanche energy<br>(starting TJ= 25 °C, ID= IAR, VDD= 50 V)|250|mJ|



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**Electrical characteristics** 

## **2 Electrical characteristics** 

TC = 25 °C unless otherwise specified 

**Table 5: On/off-state** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown voltage|VGS= 0 V, ID= 1 mA|900|||V|
|IDSS|Zero gate voltage drain current|VGS= 0 V, VDS= 900 V|||1|µA|
|||VGS= 0 V, VDS= 900 V,<br>TC= 125 °C_(1)_|||50|µA|
|IGSS|Gate bodyleakage current|VDS= 0 V, VGS= ±20 V|||±10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 100µA|3|4|5|V|
|RDS(on)|Static drain-source on-resistance|VGS= 10 V, ID= 4 A||0.60|0.68|Ω|



## **Notes:** 

(1)Defined by design, not subject to production test. 

**Table 6: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 100 V, f = 1 MHz,<br>VGS= 0 V|-|426|-|pF|
|Coss|Output capacitance||-|41|-|pF|
|Crss|Reverse transfer capacitance||-|1.2|-|pF|
|Co(tr)_(1)_|Equivalent capacitance time<br>related|VDS= 0 to 720 V,<br>VGS= 0 V|-|75|-|pF|
|Co(er)_(2)_|Equivalent capacitance energy<br>related||-|28|-|pF|
|Rg|Intrinsicgate resistance|f = 1 MHz , ID= 0 A|-|7|-|Ω|
|Qg|Totalgate charge|VDD= 720 V, ID= 8 A,<br>VGS= 10 V<br>(see_Figure 15: "Test_<br>_circuit for gate charge_<br>_behavior"_)|-|11|-|nC|
|Qgs|Gate-source charge||-|3.5|-|nC|
|Qgd|Gate-drain charge||-|4.8|-|nC|



## **Notes:** 

(1)Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 

(2)Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS 

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**Electrical characteristics** 

## **Table 7: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDD= 450 V, ID= 4 A,<br>RG= 4.7 Ω, VGS= 10 V<br>(see_Figure 14: "Test circuit for_<br>_resistive load switching times"_<br>and_Figure 19: "Switching time_<br>_waveform"_)|-|14.7|-|ns|
|tr|Rise time||-|13.2|-|ns|
|td(off)|Turn-off delaytime||-|36.4|-|ns|
|tf|Fall time||-|13.5|-|ns|



## **Table 8: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||8|A|
|ISDM_(1)_|Source-drain current<br>(pulsed)||-||32|A|
|VSD_(2)_|Forward on voltage|ISD= 8 A, VGS= 0 V|-||1.5|V|
|trr|Reverse recoverytime|ISD= 8 A, di/dt = 100 A/µs,<br>VDD= 60 V<br>(see_Figure 16: "Test circuit for_<br>_inductive load switching and_<br>_diode recovery times"_)|-|371||ns|
|Qrr|Reverse recoverycharge||-|4.27||µC|
|IRRM|Reverse recovery current||-|23||A|
|trr|Reverse recoverytime|ISD= 8 A, di/dt = 100 A/µs,<br>VDD= 60 V, Tj= 150 °C<br>(see_Figure 16: "Test circuit for_<br>_inductive load switching and_<br>_diode recovery times"_)|-|582||ns|
|Qrr|Reverse recoverycharge||-|5.73||µC|
|IRRM|Reverse recovery current||-|19.7||A|



## **Notes:** 

(1)Pulse width limited by safe operating area 

(2)Pulsed: pulse duration = 300 µs, duty cycle 1.5% 

**Table 9: Gate-source Zener diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min**|**Typ.**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)GSO|Gate-source breakdown voltage|IGS= ± 1mA, ID= 0A|30|-|-|V|



The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry. 

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## **Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2: Safe operating area** 

**==> picture [197 x 163] intentionally omitted <==**

**Figure 3: Thermal impedance** 

**==> picture [173 x 167] intentionally omitted <==**

**Figure 4: Output characteristics** 

**==> picture [173 x 158] intentionally omitted <==**

**Figure 5: Transfer characteristics** 

**==> picture [174 x 160] intentionally omitted <==**

**Figure 6: Gate charge vs gate-source voltage** 

**==> picture [178 x 158] intentionally omitted <==**

**Figure 7: Static drain-source on-resistance** 

**==> picture [178 x 157] intentionally omitted <==**

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**Electrical characteristics** 

**==> picture [438 x 200] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 8: Capacitance variations  Figure 9: Normalized gate threshold voltage vs<br>temperature<br>**----- End of picture text -----**<br>


**Figure 10: Normalized on-resistance vs temperature** 

**==> picture [188 x 163] intentionally omitted <==**

**Figure 11: Normalized V(BR)DSS vs temperature** 

**==> picture [193 x 163] intentionally omitted <==**

**==> picture [439 x 201] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 12: Source-drain diode forward  Figure 13: Maximum avalanche energy vs starting TJ<br>characteristics<br>**----- End of picture text -----**<br>


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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 586] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 14: Test circuit for resistive load  Figure 15: Test circuit for gate charge<br>switching times  behavior<br>VDD<br>RL<br>VGS IG= CONST 100 Ω D.U.T.<br>pulse width + 2.7 kΩ<br>2200 VG<br>μF<br>47 kΩ<br>1 kΩ<br>AM01469v10<br>Figure 16: Test circuit for inductive load  Figure 17: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>Figure 18: Unclamped inductive waveform  Figure 19: Switching time waveform<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

## **4.1 D²PAK (TO-263) type A package information** 

**Figure 20: D²PAK (TO-263) type A package outline** 

**==> picture [407 x 497] intentionally omitted <==**

**----- Start of picture text -----**<br>
0079457_A_rev22<br>**----- End of picture text -----**<br>


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**Package information** 

## **Table 10: D²PAK (TO-263) type A package mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|4.40||4.60|
|A1|0.03||0.23|
|b|0.70||0.93|
|b2|1.14||1.70|
|c|0.45||0.60|
|c2|1.23||1.36|
|D|8.95||9.35|
|D1|7.50|7.75|8.00|
|D2|1.10|1.30|1.50|
|E|10||10.40|
|E1|8.50|8.70|8.90|
|E2|6.85|7.05|7.25|
|e||2.54||
|e1|4.88||5.28|
|H|15||15.85|
|J1|2.49||2.69|
|L|2.29||2.79|
|L1|1.27||1.40|
|L2|1.30||1.75|
|R||0.4||
|V2|0°||8°|



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**Package information** 

**Figure 21: D²PAK (TO-263) recommended footprint (dimensions are in mm)** 

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**Package information** 

## **4.2 D²PAK packing information** 

**Figure 22: Tape outline** 

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**Package information** 

**Figure 23: Reel outline** 

**Table 11: D²PAK tape and reel mechanical data** 

|**Tape**|**Tape**|**Tape**|**Reel**|**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Dim.**|**mm**||**Dim.**|**mm**||
||**Min.**|**Max.**||**Min.**|**Max.**|
|A0|10.5|10.7|A||330|
|B0|15.7|15.9|B|1.5||
|D|1.5|1.6|C|12.8|13.2|
|D1|1.59|1.61|D|20.2||
|E|1.65|1.85|G|24.4|26.4|
|F|11.4|11.6|N|100||
|K0|4.8|5.0|T||30.4|
|P0|3.9|4.1||||
|P1|11.9|12.1|Basequantity||1000|
|P2|1.9|2.1|Bulkquantity||1000|
|R|50|||||
|T|0.25|0.35||||
|W|23.7|24.3||||



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**Revision history** 

## **5 Revision history** 

## **Table 12: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|28-Nov-2016|1|First release|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2016 STMicroelectronics – All rights reserved 

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