# Power MOSFET, N Channel, 60 V, 60 A, 0.014 ohm, TO-263 (D2PAK), Surface Mount

![Product image](https://novapart.co/image/farnell:1175644/)

**URL**: https://novapart.co/products/STB60NF06LT4/power-mosfet-n-channel-60-v-a-0014-ohm-to-263
**SKU**: STB60NF06LT4
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.7530
**Stock**: 1000+
**Lead Time**: 127 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:60A; Drain Source Voltage Vds:60V; On Resistance Rds(on):0.016ohm; Rds(on) Test Voltage Vgs:5V; Threshold Voltage Vgs:1V; Power Dissipation Pd

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | Lead (21-Jan-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | AEC-Q101 |
| Power Dissipation | 110W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 5V |
| Transistor Case Style | TO-263 (D2PAK) |
| Drain Source Voltage Vds | 60V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 60A |
| Drain Source On State Resistance | 0.014ohm |
| Gate Source Threshold Voltage Max | 1V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:1175644/)

## **STB60NF06LT4** 

Automotive-grade N-channel 60 V, 0.012 Ω typ., 60 A STripFET™ II Power MOSFET in a D²PAK package 

Datasheet - production data 

## **Features** 

**==> picture [77 x 99] intentionally omitted <==**

**----- Start of picture text -----**<br>
TAB<br>3<br>1<br>D [2] PAK<br>**----- End of picture text -----**<br>


|**Order code**|**VDS**|**RDS(on)**<br>**max.**|**ID**|**PTOT**|
|---|---|---|---|---|
|STB60NF06LT4|60 V|0.014 Ω|60 A|110 W|



- Designed for automotive applications and AEC-Q101 qualified 

- Exceptional dv/dt capability 

- 100% avalanche tested 

- Application-oriented characterization 

- 175°C operating range 

- Low threshold drive 

**Figure 1: Internal schematic diagram** 

## **Applications** 

- Switching applications 

D(2, TAB)  **Description** This Power MOSFET series realized with STMicroelectronics unique STripFET™ process G(1) is specifically designed to minimize input capacitance and gate charge. It is therefore ideal as a primary switch in advanced high-efficiency isolated DC-DC converters for Telecom and S(3) Computer applications. It is also suitable for any application with low gate charge drive AM01475v1_Tab requirements. **Table 1: Device summary Order code Marking Package Packing** ~~_~~ STB60NF06LT4 B60NF06L D²PAK Tape and reel 

This is information on a product in full production. 

_www.st.com_ 

June 2015 DocID028008 Rev 1 

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|**Contents**<br>**STB60NF06LT4**|**Contents**<br>**STB60NF06LT4**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>D²PAK (TO-263) type A package information ................................... 9|
||4.2<br>D²PAK packing information ............................................................. 12|
|**5**|**Revision history ............................................................................ 14**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDSS|Drain-source voltage (VGS= 0 V)|60|V|
|VDGR|Drain-gate voltage (RGS= 20 kΩ)|60|V|
|VGS|Gate-source voltage|±15|V|
|ID|Drain current (continuous) at Tcase= 25 °C|60|A|
||Drain current (continuous) at Tcase= 100 °C|42||
|IDM<br>_(1)_|Drain current (pulsed)|240|A|
|PTOT|Total dissipation at Tcase= 25 °C|110|W|
|dv/dt_(2)_|Peak diode recoveryvoltage slope|20|V/ns|
|Tstg|Storage temperature|-65 to 175|°C|
|Tj|Operating junction temperature|||



## **Notes:** 

- (1) Pulse width is limited by safe operating area. 

- (2) ISD ≤ 60 A, di/dt ≤ 600 A/μs; Tj ≤ Tjmax, VDD = 80% V(BR)DSS. 

**Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case|1.36|°C/W|
|Rthj-PCB<br>_(1)_|Thermal resistancejunction-PCB|35||



## **Notes:** 

- (1) When mounted on a 1-inch² FR-4, 2 Oz copper board. 

**Table 4: Avalanche characteristics** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|EAS<br>_(1)_|Singlepulse avalanche energy|320|mJ|



## **Notes:** 

- (1) starting Tj = 25 °C, ID = 30 A, VDD = 30 V. 

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**Electrical characteristics** 

## **2 Electrical characteristics** 

(Tcase = 25 °C unless otherwise specified) 

**Table 5: Static** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source<br>breakdown voltage|VGS= 0 V, ID= 250 µA|60|||V|
|IDSS|Zero gate voltage drain<br>current|VGS= 0 V, VDS= 60 V|||1|µA|
|||VGS= 0 V, VDS= 60 V,<br>Tcase= 125 °C|||10||
|IGSS|Gate-body leakage<br>current|VDS= 0 V, VGS= ±15 V|||±100|nA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250µA|1||2.5|V|
|RDS(on)|Static drain-source on-<br>resistance|VGS= 5 V, ID= 30 A||0.014|0.016|Ω|
|||VGS= 10 V, ID= 30 A||0.012|0.014||



**Table 6: Dynamic** 

|**Symbo**<br>**l**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 25 V, f = 1 MHz,<br>VGS= 0 V|-|2000|-|pF|
|Coss|Output capacitance||-|360|-||
|Crss|Reverse transfer<br>capacitance||-|125|-||
|Qg|Totalgate charge|VDD= 48 V, ID= 60 A,<br>VGS= 4.5 V, RG= 4.7 Ω (see<br>_Figure 14: "Gate charge test_<br>_circuit"_)|-|35|66|nC|
|Qgs|Gate-source charge||-|10|-||
|Qgd|Gate-drain charge||-|20|-||



**Table 7: Switching times** 

|**Symbo**<br>**l**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDD= 30 V, ID= 30 A,<br>RG= 4.7 Ω, VGS= 4.5 V (see<br>_Figure 13: "Switching times_<br>_test circuit for resistive load"_<br>and_Figure 18: "Switching time_<br>_waveform"_)|-|35|-|ns|
|tr|Rise time||-|220|-||
|td(off)|Turn-off delaytime||-|55|-||
|tf|Fall time||-|30|-||



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**Electrical characteristics** 

|||**Table 8: Source-drain diode**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|ISD|Source-drain current||-||60|A|
|ISDM<br>_(1)_|Source-drain current<br>(pulsed)||-||240|A|
|VSD<br>_(2)_|Forward on voltage|VGS= 0 V, ISD= 60 A|-||1.3|V|
|trr|Reverse recoverytime|ISD= 60 A, di/dt = 100 A/µs,<br>VDD= 30 V, Tj= 150 °C (see<br>_Figure 15: "Test circuit for_<br>_inductive load switching and_<br>_diode recovery times"_)|-|110||ns|
|Qrr|Reverse recovery<br>charge||-|250||nC|
|IRRM|Reverse recovery<br>current||-|4.5||A|



## **Notes:** 

(1) Pulse width is limited by safe operating area. 

(2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. 

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**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2: Safe operating area** 

**==> picture [157 x 144] intentionally omitted <==**

**Figure 3: Thermal impedance** 

**==> picture [145 x 145] intentionally omitted <==**

**Figure 4: Output characteristics** 

**==> picture [154 x 142] intentionally omitted <==**

**Figure 5: Transfer characteristics** 

**==> picture [155 x 143] intentionally omitted <==**

**Figure 6: Gate charge vs gate-source voltage** 

**==> picture [148 x 142] intentionally omitted <==**

**Figure 7: Static drain-source on-resistance** 

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**Electrical characteristics** 

**==> picture [385 x 179] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 9: Normalized gate threshold voltage<br>Figure 8: Capacitance variations<br>vs temperature<br>**----- End of picture text -----**<br>


**==> picture [398 x 180] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 10: Normalized on-resistance vs  Figure 11: Normalized V(BR)DSS vs<br>temperature  temperature<br>**----- End of picture text -----**<br>


**Figure 12: Source-drain diode forward characteristics** 

**==> picture [152 x 143] intentionally omitted <==**

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**Test circuits** 

## **3 Test circuits** 

**Figure 13: Switching times test circuit for resistive load** 

**Figure 15: Test circuit for inductive load switching and diode recovery times** 

**Figure 17: Unclamped inductive waveform** 

**==> picture [62 x 33] intentionally omitted <==**

**Figure 14: Gate charge test circuit** 

**Figure 16: Unclamped inductive load test circuit** 

**Figure 18: Switching time waveform** 

**==> picture [87 x 119] intentionally omitted <==**

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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

## **4.1 D²PAK (TO-263) type A package information** 

**Figure 19: D²PAK (TO-263) type A package outline** 

**==> picture [406 x 497] intentionally omitted <==**

**----- Start of picture text -----**<br>
0079457_A_rev22<br>**----- End of picture text -----**<br>


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**Package information** 

## **Table 9: D²PAK (TO-263) type A package mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|4.40||4.60|
|A1|0.03||0.23|
|b|0.70||0.93|
|b2|1.14||1.70|
|c|0.45||0.60|
|c2|1.23||1.36|
|D|8.95||9.35|
|D1|7.50|7.75|8.00|
|D2|1.10|1.30|1.50|
|E|10||10.40|
|E1|8.50|8.70|8.90|
|E2|6.85|7.05|7.25|
|e||2.54||
|e1|4.88||5.28|
|H|15||15.85|
|J1|2.49||2.69|
|L|2.29||2.79|
|L1|1.27||1.40|
|L2|1.30||1.75|
|R||0.4||
|V2|0°||8°|



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**Package information** 

**Figure 20: D²PAK (TO-263) recommended footprint (dimensions are in mm)** 

**==> picture [407 x 344] intentionally omitted <==**

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## **Package information** 

## **4.2 D²PAK packing information** 

**==> picture [70 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 21: Tape<br>**----- End of picture text -----**<br>


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**Package information** 

**Figure 22: Reel** 

**==> picture [361 x 207] intentionally omitted <==**

**----- Start of picture text -----**<br>
T<br>40mm min.<br>access hole<br>at slot location<br>B<br>D<br>C<br>N<br>A<br>Tape slot G measured<br>in core for at hub<br>Full radius tape start<br>2.5mm min.width<br>**----- End of picture text -----**<br>


**==> picture [43 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
AM06038v1<br>**----- End of picture text -----**<br>


**Table 10: D²PAK tape and reel mechanical data** 

||**Tape**|||**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Dim.**|**m**|**m**|**Dim.**|**mm**||
||**Min.**|**Max.**||**Min.**|**Max.**|
|A0|10.5|10.7|A||330|
|B0|15.7|15.9|B|1.5||
|D|1.5|1.6|C|12.8|13.2|
|D1|1.59|1.61|D|20.2||
|E|1.65|1.85|G|24.4|26.4|
|F|11.4|11.6|N|100||
|K0|4.8|5.0|T||30.4|
|P0|3.9|4.1||||
|P1|11.9|12.1|Baseqty||1000|
|P2|1.9|2.1|Bulkqty||1000|
|R|50|||||
|T|0.25|0.35||||
|W|23.7|24.3||||



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**Revision history** 

## **5 Revision history** 

**Table 11: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|24-Jun-2015|1|First release.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2015 STMicroelectronics – All rights reserved 

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## Links

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- [Supplier page](https://es.farnell.com/stmicroelectronics/stb60nf06lt4/mosfet-n-d2-pak/dp/1175644)
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