# Power MOSFET, N Channel, 800 V, 16 A, 0.23 ohm, TO-263 (D2PAK), Surface Mount

![Product image](https://novapart.co/image/farnell:3367001/)

**URL**: https://novapart.co/products/STB23N80K5/power-mosfet-n-channel-800-v-16-a-023-ohm-to-263
**SKU**: STB23N80K5
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €2.0800
**Stock**: 1000+
**Lead Time**: 2 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | MDmesh K5 |
| Qualification | - |
| Power Dissipation | 190W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-263 (D2PAK) |
| Drain Source Voltage Vds | 800V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 16A |
| Drain Source On State Resistance | 0.23ohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3367001/)

## **STB23N80K5** 

## N-channel 800 V, 0.23 Ω typ., 16 A MDmesh™ K5 Power MOSFET in a D²PAK package 

Datasheet - production data 

## **Features** 

**==> picture [77 x 99] intentionally omitted <==**

**----- Start of picture text -----**<br>
TAB<br>3<br>1<br>D [2] PAK<br>**----- End of picture text -----**<br>


|**Order code**|**VDS**|**RDS(on) max.**|**ID**|**PTOT**|
|---|---|---|---|---|
|STB23N80K5|800 V|0.28 Ω|16 A|190 W|



- Industry’s lowest RDS(on) x area 

- Industry’s best figure of merit (FoM) 

- Ultra low gate charge 

- 100% avalanche tested 

- Zener-protected 

## **Applications** 

**Figure 1: Internal schematic diagram** 

- Switching applications 

## **Description** 

This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. 

**Table 1: Device summary** 

|**Order code**|**Marking**|**Package**|**Packing**|
|---|---|---|---|
|STB23N80K5|23N80K5|D²PAK|Tape and reel|



This is information on a product in full production. 

August 2015 

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_www.st.com_ 

|**Contents**<br>**STB23N80K5**|**Contents**<br>**STB23N80K5**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>D²PAK (TO-263) type A package information ................................... 9|
||4.2<br>D²PAK packing information ............................................................. 12|
|**5**|**Revision history ............................................................................ 14**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VGS|Gate-source voltage|±30|V|
|ID|Drain current (continuous) at Tcase= 25 °C|16|A|
||Drain current (continuous) at Tcase= 100 °C|10||
|IDM_(1)_|Drain current (pulsed)|64|A|
|PTOT|Total dissipation at Tcase= 25 °C|190|W|
|dv/dt_(2)_|Peak diode recoveryvoltage slope|4.5|V/ns|
|dv/dt_(3)_|MOSFET dv/dt ruggedness|50||
|Tstg|Storage temperature|-55 to 150|°C|
|Tj|Operating junction temperature|||



## **Notes:** 

- (1) Pulse width is limited by safe operating area. 

- (2) ISD ≤ 16 A, di/dt=100 A/μs; VDS peak < V(BR)DSS, VDD = 80% V(BR)DSS. (3) VDS ≤ 640 V 

**Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case|0.66|°C/W|
|Rthj-pcb_(1)_|Thermal resistancejunction-ambient|30||



## **Notes:** 

- (1) When mounted on a 1-inch² FR-4, 2 Oz copper board. 

**Table 4: Avalanche characteristics** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|IAR_(1)_|Avalanche current, repetitive or not repetitive|5|A|
|EAS_(2)_|Singlepulse avalanche energy|400|mJ|



## **Notes:** 

- (1) Pulse width limited by Tjmax. 

- (2) starting Tj = 25 °C, ID = IAR, VDD = 50 V. 

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**Electrical characteristics** 

## **2 Electrical characteristics** 

(Tcase = 25 °C unless otherwise specified) 

**Table 5: Static** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|VGS= 0 V, ID= 1 mA|800|||V|
|IDSS|Zero gate voltage drain<br>current|VGS= 0 V, VDS= 800 V|||1|µA|
|||VGS= 0 V, VDS= 800 V,<br>Tcase= 125 °C|||50||
|IGSS|Gate-bodyleakage current|VDS= 0 V, VGS= ±20 V|||±10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 100µA|3|4|5|V|
|RDS(on)|Static drain-source on-<br>resistance|VGS= 10 V, ID= 8 A||0.23|0.28|Ω|



**Table 6: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 100 V, f = 1 MHz,<br>VGS= 0 V|-|1000|-|pF|
|Coss|Output capacitance||-|65|-||
|Crss|Reverse transfer<br>capacitance||-|1.5|-||
|CO(tr)_(1)_|Equivalent output<br>capacitance|VDS= 0 to 640 V, VGS= 0 V|-|165|-|pF|
|CO(er)_(2)_|Equivalent output<br>capacitance|VDS= 0 to 640 V, VGS= 0 V|-|59|-||
|RG|Intrinsicgate resistance|f = 1 MHz, ID= 0 A|-|4.7|-|Ω|
|Qg|Totalgate charge|VDD= 640 V, ID= 16 A,<br>VGS= 10 V (see_Figure 14:_<br>_"Test circuit for gate charge_<br>_behavior"_)|-|33|-|nC|
|Qgs|Gate-source charge||-|6|-||
|Qgd|Gate-drain charge||-|25|-||



## **Notes:** 

(1) Time related is defined as a constant equivalent capacitance giving the same charging time as COSS when VDS increases from 0 to 80% VDSS. 

(2) Energy related is defined as a constant equivalent capacitance giving the same stored energy as COSS when VDS increases from 0 to 80% VDSS 

**Table 7: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDD= 400 V, ID= 8 A<br>RG= 4.7 Ω, VGS= 10 V (see<br>_Figure 13: "Test circuit for_<br>_resistive load switching times"_<br>and_Figure 18: "Switching time_<br>_waveform"_)|-|14|-|ns|
|tr|Rise time||-|9|-||
|td(off)|Turn-off delaytime||-|48|-||
|tf|Fall time||-|9|-||



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**Electrical characteristics** 

**Table 8: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||16|A|
|ISDM_(1)_|Source-drain current<br>(pulsed)||-||64|A|
|VSD_(2)_|Forward on voltage|VGS= 0 V, ISD= 16 A|-||1.5|V|
|trr|Reverse recoverytime|ISD= 16 A, di/dt = 100 A/µs,<br>VDD= 60 V (see_Figure 15:_<br>_"Test circuit for inductive load_<br>_switching and diode recovery_<br>_times"_)|-|410||ns|
|Qrr|Reverse recoverycharge||-|7||µC|
|IRRM|Reverse recovery current||-|34||A|
|trr|Reverse recoverytime|ISD= 16 A, di/dt = 100 A/µs,<br>VDD= 60 V, Tj= 150 °C (see<br>_Figure 15: "Test circuit for_<br>_inductive load switching and_<br>_diode recovery times"_)|-|650||ns|
|Qrr|Reverse recoverycharge||-|10||µC|
|IRRM|Reverse recovery current||-|32||A|



## **Notes:** 

- (1) Pulse width is limited by safe operating area. 

- (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. 

**Table 9: Gate-source Zener diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)GSO|Gate-source breakdown voltage|IGS= ±1 mA, ID= 0 A|±30|-|-|V|



The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. 

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**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**==> picture [342 x 158] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 2: Safe operating area  Figure 3: Thermal impedance<br>GIPG280815VK86BSOA K GC20540<br>δ=0.5<br>Operation in this area is<br>limited by Rogion) 10 us 0.2<br>100 us 0.1<br>1ms 10 [-1] 0.05<br>0.02<br>10 ms Z th = K*R thj-c<br>δ= tp/ Ƭ<br>0.01<br>T;= 150 °C L<br>Single pulse<br>T,= 25 °C tp  Ƭ<br>single pulse 10 [-2]<br>10° 10! 10? Vos (V) 10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] tP(s)<br>**----- End of picture text -----**<br>


**==> picture [350 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 4: Output characteristics  Figure 5: Transfer characteristics<br>**----- End of picture text -----**<br>


**Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance** 

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**Electrical characteristics** 

**==> picture [385 x 179] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 9: Normalized gate threshold voltage<br>Figure 8: Capacitance variations<br>vs temperature<br>**----- End of picture text -----**<br>


**==> picture [398 x 179] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 10: Normalized on-resistance vs  Figure 11: Normalized V(BR)DSS vs<br>temperature  temperature<br>**----- End of picture text -----**<br>


**Figure 12: Maximum avalanche energy vs temperature** 

**==> picture [159 x 142] intentionally omitted <==**

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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 375] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 13: Test circuit for resistive load  Figure 14: Test circuit for gate charge<br>switching times  behavior<br>Figure 15: Test circuit for inductive load  Figure 16: Unclamped inductive load test<br>switching and diode recovery times  circuit<br>**----- End of picture text -----**<br>


**==> picture [403 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 17: Unclamped inductive waveform  Figure 18: Switching time waveform<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

## **4.1 D²PAK (TO-263) type A package information** 

**Figure 19: D²PAK (TO-263) type A package outline** 

**==> picture [407 x 497] intentionally omitted <==**

**----- Start of picture text -----**<br>
0079457_A_rev22<br>**----- End of picture text -----**<br>


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**Package information** 

## **Table 10: D²PAK (TO-263) type A package mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|4.40||4.60|
|A1|0.03||0.23|
|b|0.70||0.93|
|b2|1.14||1.70|
|c|0.45||0.60|
|c2|1.23||1.36|
|D|8.95||9.35|
|D1|7.50|7.75|8.00|
|D2|1.10|1.30|1.50|
|E|10||10.40|
|E1|8.50|8.70|8.90|
|E2|6.85|7.05|7.25|
|e||2.54||
|e1|4.88||5.28|
|H|15||15.85|
|J1|2.49||2.69|
|L|2.29||2.79|
|L1|1.27||1.40|
|L2|1.30||1.75|
|R||0.4||
|V2|0°||8°|



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**Package information** 

**Figure 20: D²PAK (TO-263) recommended footprint (dimensions are in mm)** 

**==> picture [407 x 344] intentionally omitted <==**

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**Package information** 

## **4.2 D²PAK packing information** 

**Figure 21: Tape** 

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**Package information** 

**Figure 22: Reel** 

**Table 11: D²PAK tape and reel mechanical data** 

|**Tape**|**Tape**|**Tape**|**Reel**|**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Dim.**|**mm**||**Dim.**|**mm**||
||**Min.**|**Max.**||**Min.**|**Max.**|
|A0|10.5|10.7|A||330|
|B0|15.7|15.9|B|1.5||
|D|1.5|1.6|C|12.8|13.2|
|D1|1.59|1.61|D|20.2||
|E|1.65|1.85|G|24.4|26.4|
|F|11.4|11.6|N|100||
|K0|4.8|5.0|T||30.4|
|P0|3.9|4.1||||
|P1|11.9|12.1|Baseqty||1000|
|P2|1.9|2.1|Bulkqty||1000|
|R|50|||||
|T|0.25|0.35||||
|W|23.7|24.3||||



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**Revision history** 

## **5 Revision history** 

**Table 12: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|28-Aug-2015|1|First release.|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2015 STMicroelectronics – All rights reserved 

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- [Supplier page](https://es.farnell.com/stmicroelectronics/stb23n80k5/mosfet-n-ch-800v-16a-150deg-c/dp/3367001)
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