# Power MOSFET, N Channel, 500 V, 17 A, 0.23 ohm, TO-263 (D2PAK), Surface Mount

![Product image](https://novapart.co/image/farnell:2344095/)

**URL**: https://novapart.co/products/STB21NK50Z/power-mosfet-n-channel-500-v-17-a-023-ohm-to-263
**SKU**: STB21NK50Z
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.8020
**Stock**: 10+

## Specifications

| Parameter | Value |
|---|---|
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Power Dissipation | 190W |
| Transistor Mounting | Surface Mount |
| Transistor Polarity | N Channel |
| Power Dissipation Pd | 190W |
| Rds(On) Test Voltage | 10V |
| On Resistance Rds(On) | 0.23ohm |
| Transistor Case Style | TO-263 (D2PAK) |
| Drain Source Voltage Vds | 500V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 17A |
| Drain Source On State Resistance | 0.23ohm |
| Gate Source Threshold Voltage Max | 3.75V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2344095/)

## **STB21NK50Z** 

Automotive grade N-channel 500 V, 0.23 Ω , 17 A, Zener-protected SuperMESH™ Power MOSFET in a D[2] PAK  package 

**Datasheet** - **production data** 

## **Features** 

**==> picture [72 x 78] intentionally omitted <==**

**----- Start of picture text -----**<br>
TAB<br>3<br>1<br>D²PAK<br>**----- End of picture text -----**<br>


**Order code VDS RDS(on) max ID PW** STB21NK50Z 500 V 0.27 Ω 17 A 190 W ~~————~~ 

- Designed for automotive applications and AEC-Q101 qualified 

- Extremely high dv/dt capability 

- 100% avalanche tested 

- Gate charge minimized 

- Very low intrinsic capacitances 

- Very good manufacturing repeatability 

## **Figure 1.  Internal schematic diagram** 

**==> picture [173 x 157] intentionally omitted <==**

**----- Start of picture text -----**<br>
D(2)<br>G(1)<br>S(3)<br>AM16160v1<br>**----- End of picture text -----**<br>


## **Applications** 

- Switching applications 

## **Description** 

This device is an N-channel Zener-protected Power MOSFET developed using STMicroelectronics' SuperMESH™ technology, achieved through optimization of ST's well established strip-based PowerMESH™ layout. In addition to a significant reduction in onresistance, this device is designed to ensure a high level of dv/dt capability for the most demanding applications. 

**Table 1. Device summary** 

**Order code Marking Packages Packaging** STB21NK50Z 21NK50Z D²PAK Tape and reel ~~—p~~ 

_www.st.com_ 

September 2014 

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This is information on a product in full production. 

**Contents** 

**STB21NK50Z** 

|**Contents**|**Contents**|
|---|---|
|**1**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3**|
|**2**|**Electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4**|
||2.1<br>Electrical characteristics (curves)       . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**3**|**Test circuits     . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8**|
|**4**|**Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9**|
|**5**|**Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11**|
|**6**|**Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2. Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VDS|Drain-source voltage (VGS= 0)|500|V|
|VGS|Gate-source voltage|± 30|V|
|ID|Drain current (continuous) at TC= 25 °C|17|A|
|ID|Drain current (continuous) at TC=100 °C|10.71|A|
|IDM<br>(1)|Drain current (pulsed)|68|A|
|PTOT|Total dissipation at TC= 25 °C|190|W|
||Derating Factor|1.51|W/°C|
|Vesd(G-S)|G-S ESD (HBM C=100 pF, R=1.5 kΩ)|6000|V|
|dv/dt(2)|Peak diode recovery voltage slope|4.5|V/ns|
|Tstg|Storage temperature|-55 to 150|°C|
|TJ|Max operating junction temperature|150|°C|



1. Pulse width limited by safe operating area 

2. ISD ≤ 17 A, di/dt ≤ 200 A/µs,VDD ≤ V(BR)DSS, TJ ≤ TJMAX 

**Table 3. Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistance junction-case max|0.66|°C/W|
|Rthj-amb|Thermal resistance junction-ambient max|62.5|°C/W|
|Tl|Maximum lead temperature for soldering<br>purpose|300|°C|



**Table 4. Avalanche characteristics** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|IAR|Avalanche current, repetitive or not-repetitive<br>(pulse width limited by Tj max)|17|A|
|EAS|Single pulse avalanche energy<br>(starting TJ=25 °C, ID=IAR, VDD=50 V)|850|mJ|



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**Electrical characteristics** 

## **2 Electrical characteristics** 

(TCASE = 25 °C unless otherwise specified) 

**Table 5. On/off states** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|ID= 1mA, VGS= 0|500|||V|
|IDSS|Zero gate voltage drain<br>current (VGS= 0)|VDS= 500 V|||1|µA|
|||VDS= 500 V, TC=125 °C|||50|µA|
|IGSS|Gate body leakage current<br>(VDS= 0)|VGS= ±20 V|||±10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 100 µA|3|3.75|4.5|V|
|RDS(on)|Static drain-source on-<br>resistance|VGS= 10 V, ID= 8.5 A||0.23|0.27|Ω|



**Table 6. Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 25 V, f=1 MHz, VGS=0|-|2600||pF|
|Coss|Output capacitance||-|328||pF|
|Crss|Reverse transfer<br>capacitance||-|72||pF|
|Coss eq<br>(1)<br>.|Equivalent output<br>capacitance|VGS=0, VDS=0 to 400 V|-|187||pF|
|Qg|Total gate charge|VDD=400 V, ID= 17 A<br>VGS=10 V<br>(see Figure 15)|-|85|119|nC|
|Qgs|Gate-source charge||-|15.5||nC|
|Qgd|Gate-drain charge||-|42||nC|



1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 

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**Electrical characteristics** 

**Table 7. Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD= 250 V, ID= 8.5 A,<br>RG= 4.7Ω,VGS= 10 V<br>(see Figure 16)||-|28|-|ns|
|tr|Rise time|||-|20|-|ns|
|td(off)|Turn-off delay time|VDD= 250 V, ID= 8.5 A,<br>RG= 4.7Ω,VGS=10 V<br>(see Figure 16)||-|70|-|ns|
|tf|Fall time|||-|15|-|ns|
|**Table 8. Gate-source Zener diode**||||||||
|**Symbol**|**Parameter**||**Test conditions**|**Min**|**Typ.**|**Max.**|**Unit**|
|V(BR)GSO|Gate-source breakdown voltage||IGS= ± 1mA, ID=0|30|-|-|V|



The built-in back-to-back Zener diodes have been specifically designed to enhance the ESD capability of the device. The Zener voltage is appropriate for efficient and cost-effective intervention to protect the device integrity. These integrated Zener diodes thus eliminate the need for external components. 

**Table 9. Source drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min**|**Typ.**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||17|A|
|ISDM<br>(1)|Source-drain current (pulsed)||-||68|A|
|VSD<br>(2)|Forward on voltage|ISD= 17 A, VGS=0|-||1.6|V|
|trr|Reverse recovery time|ISD= 17 A,<br>di/dt = 100 A/µs,<br>VR= 100 V<br>(see Figure 16)|-|355||ns|
|Qrr|Reverse recovery charge||-|3.90||µC|
|IRRM|Reverse recovery current||-|22||A|
|trr|Reverse recovery time|ISD= 17 A,<br>di/dt = 100 A/µs,<br>VR= 100 V, Tj=150 °C<br>(see Figure 16)|-|440||ns|
|Qrr|Reverse recovery charge||-|5.72||µC|
|IRRM|Reverse recovery current||-|25||A|



1. Pulse width limited by safe operating area 

2. Pulsed: pulse duration=300µs, duty cycle 1.5% 

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**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**Figure 2. Safe operating area** 

**==> picture [157 x 154] intentionally omitted <==**

## **Figure 3. Thermal impedance** 

**==> picture [160 x 155] intentionally omitted <==**

**Figure 4. Output characteristics** 

**==> picture [162 x 155] intentionally omitted <==**

## **Figure 5. Transfer characteristics** 

**==> picture [155 x 153] intentionally omitted <==**

**Figure 6. Normalized BVDSS vs temperature** 

**==> picture [172 x 154] intentionally omitted <==**

**Figure 7. Static drain-source on-resistance** 

**==> picture [169 x 154] intentionally omitted <==**

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**Electrical characteristics** 

**Figure 8. Gate charge vs gate-source voltage** 

**==> picture [168 x 153] intentionally omitted <==**

**Figure 10. Normalized gate threshold voltage vs temperature** 

**==> picture [168 x 153] intentionally omitted <==**

**Figure 12. Source-drain diode forward characteristics** 

**==> picture [167 x 155] intentionally omitted <==**

**Figure 9. Capacitance variations** 

**==> picture [165 x 153] intentionally omitted <==**

**Figure 11. Normalized on-resistance vs temperature** 

**==> picture [169 x 155] intentionally omitted <==**

**Figure 13. Maximum avalanche energy vs temperature** 

**==> picture [167 x 154] intentionally omitted <==**

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**Test circuits** 

## **3 Test circuits** 

**Figure 14. Switching times test circuit for resistive load** 

**Figure 15. Gate charge test circuit** 

**==> picture [462 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>12V 47kΩ<br>1kΩ<br>100nF<br>RL 2200 3.3<br>μF μF<br>VDD IG=CONST<br>VD Vi=20V=VGMAX 100Ω D.U.T.<br>VGS<br>2200<br>RG D.U.T. μF 2.7kΩ VG<br>PW<br>47kΩ<br>1kΩ<br>PW<br>AM01468v1 AM01469v1<br>**----- End of picture text -----**<br>


**Figure 16. Test circuit for inductive load Figure 17. Unclamped inductive load test circuit switching and diode recovery times** 

**==> picture [462 x 346] intentionally omitted <==**

**----- Start of picture text -----**<br>
L<br>A A A<br>D<br>FAST L=100μH VD<br>G D.U.T. DIODE 2200 3.3<br>S B 3.3 1000 μF μF VDD<br>25 Ω B B D μF μF VDD ID<br>G<br>RG S<br>Vi D.U.T.<br>Pw<br>AM01470v1 AM01471v1<br>Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform<br>V(BR)DSS ton toff<br>VD tdon tr tdoff tf<br>90% 90%<br>IDM<br>10%<br>ID 0 10% VDS<br>VDD VDD 90%<br>VGS<br>AM01472v1 0 10% AM01473v1<br>**----- End of picture text -----**<br>


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**Package mechanical data** 

## **4 Package mechanical data** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _www.st.com_ . ECOPACK[®] is an ST trademark. 

**Figure 20. D²PAK (TO-263) drawing** 

**==> picture [405 x 320] intentionally omitted <==**

**----- Start of picture text -----**<br>
0079457_T<br>**----- End of picture text -----**<br>


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**Package mechanical data** 

**Table 10. D²PAK (TO-263) mechanical data** 

||**Table 10. D²PAK(TO-263) mechanical data**|**Table 10. D²PAK(TO-263) mechanical data**|**Table 10. D²PAK(TO-263) mechanical data**|
|---|---|---|---|
|**Dim.**|**mm**|||
||**Min.**|**Typ.**|**Max.**|
|A|4.40||4.60|
|A1|0.03||0.23|
|b|0.70||0.93|
|b2|1.14||1.70|
|c|0.45||0.60|
|c2|1.23||1.36|
|D|8.95||9.35|
|D1|7.50|||
|E|10||10.40|
|E1|8.50|||
|e||2.54||
|e1|4.88||5.28|
|H|15||15.85|
|J1|2.49||2.69|
|L|2.29||2.79|
|L1|1.27||1.40|
|L2|1.30||1.75|
|R||0.4||
|V2|0°||8°|



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**Package mechanical data** 

**==> picture [405 x 245] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 21. D²PAK footprint [(a)]<br>16.90<br>12.20 5.08<br>1.60<br>3.50<br>9.75<br>Footprint<br>**----- End of picture text -----**<br>


- a. All dimension are in millimeters 

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**Packaging mechanical data** 

## **5 Packaging mechanical data** 

## **Figure 22. Tape** 

**==> picture [399 x 317] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 pitches cumulative<br>tolerance on tape +/- 0.2 mm<br>Top cover P0 D P2<br>T tape<br>E<br>{7 co0 00 00 a e ome<br>F<br>K0 W<br>B1 B0<br>A E I RI RI B IE,<br>For machine ref. only A0 P1 D1<br>including draft and<br>radii concentric around B0 ——<br>User direction of feed<br>R<br>sogtees<br>[Se EEE EE<br>—— Bending radius<br>User direction of feed<br>AM08852v1<br>**----- End of picture text -----**<br>


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**Packaging mechanical data** 

**==> picture [75 x 11] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 23. Reel<br>**----- End of picture text -----**<br>


**==> picture [405 x 256] intentionally omitted <==**

**----- Start of picture text -----**<br>
T<br>REEL DIMENSIONS<br>40mm min.<br>Access hole<br>At slot location<br>B<br>D<br>C<br>N<br>A<br>Full radius Tape slot  G measured at hub<br>in core for<br>tape start 25 mm min.<br>width<br>AM08851v2<br>**----- End of picture text -----**<br>


**Table 11. D²PAK (TO-263) tape and reel mechanical data** 

||**Tape**|**Tape**||**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Dim.**|**mm**<br>**Min.**<br>**Max.**||**Dim.**|**mm**||
||**Min.**|||**Min.**|**Max.**|
|A0|10.5|10.7|A||330|
|B0|15.7|15.9|B|1.5||
|D|1.5|1.6|C|12.8|13.2|
|D1|1.59|1.61|D|20.2||
|E|1.65|1.85|G|24.4|26.4|
|F|11.4|11.6|N|100||
|K0|4.8|5.0|T||30.4|
|P0|3.9|4.1||||
|P1|11.9|12.1||Base qty|1000|
|P2|1.9|2.1||Bulk qty|1000|
|R|50|0.35<br>24.3||||
|T|0.25|||||
|W|23.7|||||



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**Revision history** 

## **6 Revision history** 

**Table 12. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|16-Sep-2008|1|First issue|
|19-Sep-2014|2|– Updated: title and features in cover page<br>– Updated:_Section 4: Package mechanical data_and_Section 5:_<br>_Packaging mechanical data_<br>– Minor text changes|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

© 2014 STMicroelectronics – All rights reserved 

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- [Supplier page](https://es.farnell.com/en-ES/stmicroelectronics/stb21nk50z/mosfet-n-ch-500v-17a-d2pak/dp/2344095)
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