# Power MOSFET, Mdmesh DM2, N Channel, 600 V, 12 A, 0.26 ohm, TO-263 (D2PAK), Surface Mount

![Product image](https://novapart.co/image/farnell:2531102/)

**URL**: https://novapart.co/products/STB18N60DM2/power-mosfet-mdmesh-dm2-n-channel-600-v-12-a-026
**SKU**: STB18N60DM2
**Manufacturer**: STMICROELECTRONICS
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.8290
**Stock**: 10+
**Lead Time**: 259 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:12A; Drain Source Voltage Vds:600V; On Resistance Rds(on):0.26ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4V; Power

## Specifications

| Parameter | Value |
|---|---|
| Msl | - |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 90W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-263 (D2PAK) |
| Drain Source Voltage Vds | 600V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 12A |
| Drain Source On State Resistance | 0.26ohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2531102/)

## **STB18N60DM2** 

## N-channel 600 V, 0.260 Ω typ., 12 A MDMesh™ DM2 Power MOSFET in a D²PAK package 

Datasheet - production data 

## **Features** 

**==> picture [79 x 100] intentionally omitted <==**

**----- Start of picture text -----**<br>
TAB<br>2<br>3<br>1<br>D²PAK<br>**----- End of picture text -----**<br>


|**Order code**|**VDS**|**RDS(on) max.**|**ID**|
|---|---|---|---|
|STB18N60DM2|600 V|0.295 Ω|12 A|



- Fast-recovery body diode 

- Extremely low gate charge and input capacitance 

- Low on-resistance 

- 100% avalanche tested 

- Extremely high dv/dt ruggedness 

- Zener-protected 

**Figure 1: Internal schematic diagram** 

## **Applications** 

D(2, TAB)  Switching applications **Description** This high voltage N-channel Power MOSFET is part of the MDmesh™ DM2 fast recovery diode G(1) series. It offers very low recovery charge (Qrr) and time (trr) combined with low RDS(on), rendering it suitable for the most demanding high efficiency converters and ideal for bridge topologies and ZVS phase-shift converters. S(3) AM15572v1_tab **Table 1: Device summary Order code Marking Package Packing** ~~_—~~ STB18N60DM2 18N60DM2 D²PAK Tape and Reel 

This is information on a product in full production. 

_www.st.com_ 

January 2016 

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|**Contents**<br>**STB18N60DM2**|**Contents**<br>**STB18N60DM2**|
|---|---|
|**Contents**||
|**1**|**Electrical ratings ............................................................................. 3**|
|**2**|**Electrical characteristics ................................................................ 4**|
||2.1<br>Electrical characteristics (curves) ...................................................... 6|
|**3**|**Test circuits ..................................................................................... 8**|
|**4**|**Package information ....................................................................... 9**|
||4.1<br>D²PAK (TO-263) type A package information ................................... 9|
||4.2<br>D²PAK packing information ............................................................. 12|
|**5**|**Revision history ............................................................................ 14**|



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**Electrical ratings** 

## **1 Electrical ratings** 

**Table 2: Absolute maximum ratings** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VGS|Gate-source voltage|± 25|V|
|ID|Drain current (continuous) at Tcase= 25 °C|12|A|
||Drain current (continuous) at Tcase= 100 °C|7.6||
|IDM_(1)_|Drain current (pulsed)|48|A|
|PTOT|Total dissipation at Tcase= 25 °C|90|W|
|dv/dt_(2)_|Peak diode recoveryvoltage slope|40|V/ns|
|dv/dt_(3)_|MOSFET dv/dt ruggedness|50||
|Tstg|Storage temperature range|–55 to 150|°C|
|Tj|Operating junction temperature range|||



## **Notes:** 

(1) Pulse width is limited by safe operating area. 

- (2) ISD ≤ 12 A, di/dt ≤ 400 A/µS, VDS(peak) < V(BR)DSS, VDD = 80% V(BR)DSS. (3) VDS ≤ 480 V. 

**Table 3: Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rthj-case|Thermal resistancejunction-case|1.39|°C/W|
|Rthj-pcb_(1)_|Thermal resistancejunction-pcb|30||



## **Notes:** 

- (1) When mounted on 1 a inch² FR-4, 2 Oz copper board 

**Table 4: Avalanche characteristics** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|IAR_(1)_|Avalanche current, repetitive or not repetitive|2.5|A|
|EAR_(2)_|Singlepulse avalanche energy|380|mJ|



## **Notes:** 

- (1) Pulse width is limited by Tjmax. 

- (2) starting Tj = 25 °C, ID = IAR, VDD = 50 V. 

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**Electrical characteristics** 

## **2 Electrical characteristics** 

(Tcase= 25 °C unless otherwise specified) 

**Table 5: Static** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown<br>voltage|VGS= 0 V, ID= 1 mA|600|||V|
|IDSS|Zero gate voltage drain<br>current|VGS= 0 V, VDS= 600 V|||1.5|µA|
|||VGS= 0 V, VDS= 600 V,<br>Tcase= 125 °C|||100|µA|
|IGSS|Gate-body leakage<br>current|VDS= 0 V, VGS= ±25 V|||±10|µA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250µA|3|4|5|V|
|RDS(on)|Static drain-source on-<br>resistance|VGS= 10 V, ID= 6 A||0.260|0.295|Ω|



**Table 6: Dynamic** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 100 V, f = 1 MHz,<br>VGS= 0 V|-|800|-|pF|
|Coss|Output capacitance||-|40|-||
|Crss|Reverse transfer<br>capacitance||-|1.33|-||
|Coss eq._(1)_|Equivalent output<br>capacitance|VDS= 0 to 480 V, f = 1 MHz,<br>VGS= 0 V|-|80|-|pF|
|RG|Intrinsic gate resistance|f = 1 MHz, ID= 0 A|-|5.6|-|Ω|
|Qg|Totalgate charge|VDD= 480 V, ID= 12 A,<br>VGS= 10 V (see_Figure 15: "Test_<br>_circuit for gate charge behavior"_)|-|20|-|nC|
|Qgs|Gate-source charge||-|5.2|-||
|Qgd|Gate-drain charge||-|8.5|-||



## **Notes:** 

(1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 

**Table 7: Switching times** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delaytime|VDD= 300 V, ID= 6 A RG= 4.7 Ω,<br>VGS= 10 V (see_Figure 14: "Test_<br>_circuit for resistive load switching_<br>_times"_and_Figure 19: "Switching time_<br>_waveform"_)|-|13.5|-|ns|
|tr|Rise time||-|8|-||
|td(off)|Turn-off-delaytime||-|9.5|-||
|tf|Fall time||-|32.5|-||



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**Electrical characteristics** 

**Table 8: Source-drain diode** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||12|A|
|ISDM_(1)_|Source-drain current<br>(pulsed)||-||48|A|
|VSD_(2)_|Forward on voltage|VGS= 0 V, ISD= 12 A|-||1.6|V|
|trr|Reverse recoverytime|ISD= 12 A, di/dt = 100 A/µs,<br>VDD= 60 V (see_Figure 16:_<br>_"Test circuit for inductive load_<br>_switching and diode recovery_<br>_times"_)|-|125||ns|
|Qrr|Reverse recoverycharge||-|0.675||nC|
|IRRM|Reverse recovery current||-|11||A|
|trr|Reverse recoverytime|ISD= 12 A, di/dt = 100 A/µs,<br>VDD= 60 V, Tj= 150 °C (see<br>_Figure 16: "Test circuit for_<br>_inductive load switching and_<br>_diode recovery times"_)|-|190||ns|
|Qrr|Reverse recoverycharge||-|1225||nC|
|IRRM|Reverse recovery current||-|13||A|



## **Notes:** 

(1) Pulse width is limited by safe operating area. 

(2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. 

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**Electrical characteristics** 

## **2.1 Electrical characteristics (curves)** 

**==> picture [381 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 2: Safe operating area  Figure 3: Thermal impedance<br>**----- End of picture text -----**<br>


**==> picture [386 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 4: Output characteristics  Figure 5: Transfer characteristics<br>**----- End of picture text -----**<br>


## **Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance** 

**==> picture [161 x 143] intentionally omitted <==**

**==> picture [162 x 142] intentionally omitted <==**

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**Electrical characteristics** 

**==> picture [385 x 179] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 9: Normalized gate threshold voltage<br>Figure 8: Capacitance variations<br>vs temperature<br>**----- End of picture text -----**<br>


**==> picture [398 x 179] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 10: Normalized on-resistance vs  Figure 11: Normalized V(BR)DSS vs<br>temperature  temperature<br>**----- End of picture text -----**<br>


**Figure 12: Source-drain diode forward Figure 13: Output capacitance stored energy characteristics** 

**==> picture [157 x 143] intentionally omitted <==**

**==> picture [157 x 139] intentionally omitted <==**

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**Test circuits** 

## **3 Test circuits** 

**==> picture [416 x 580] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 14: Test circuit for resistive load  Figure 15: Test circuit for gate charge<br>switching times  behavior<br>Figure 16: Test circuit for inductive load<br>switching and diode recovery times  Figure 17: Unclamped inductive load test<br>circuit<br>Figure 19: Switching time waveform<br>Figure 18: Unclamped inductive waveform<br>**----- End of picture text -----**<br>


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**Package information** 

## **4 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark. 

## **4.1 D²PAK (TO-263) type A package information** 

**Figure 20: D²PAK (TO-263) type A package outline** 

**==> picture [407 x 497] intentionally omitted <==**

**----- Start of picture text -----**<br>
0079457_A_rev22<br>**----- End of picture text -----**<br>


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**Package information** 

## **Table 9: D²PAK (TO-263) type A package mechanical data** 

|**Dim.**||**mm**||
|---|---|---|---|
||**Min.**|**Typ.**|**Max.**|
|A|4.40||4.60|
|A1|0.03||0.23|
|b|0.70||0.93|
|b2|1.14||1.70|
|c|0.45||0.60|
|c2|1.23||1.36|
|D|8.95||9.35|
|D1|7.50|7.75|8.00|
|D2|1.10|1.30|1.50|
|E|10||10.40|
|E1|8.50|8.70|8.90|
|E2|6.85|7.05|7.25|
|e||2.54||
|e1|4.88||5.28|
|H|15||15.85|
|J1|2.49||2.69|
|L|2.29||2.79|
|L1|1.27||1.40|
|L2|1.30||1.75|
|R||0.4||
|V2|0°||8°|



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**Package information** 

**Figure 21: D²PAK (TO-263) recommended footprint (dimensions are in mm)** 

**==> picture [407 x 344] intentionally omitted <==**

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**Package information** 

## **4.2 D²PAK packing information** 

**Figure 22: Tape outline** 

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**Package information** 

**Figure 23: Reel outline** 

**Table 10: D²PAK tape and reel mechanical data** 

|**Tape**|**Tape**|**Tape**|**Reel**|**Reel**|**Reel**|
|---|---|---|---|---|---|
|**Dim.**|**mm**||**Dim.**|**mm**||
||**Min.**|**Max.**||**Min.**|**Max.**|
|A0|10.5|10.7|A||330|
|B0|15.7|15.9|B|1.5||
|D|1.5|1.6|C|12.8|13.2|
|D1|1.59|1.61|D|20.2||
|E|1.65|1.85|G|24.4|26.4|
|F|11.4|11.6|N|100||
|K0|4.8|5.0|T||30.4|
|P0|3.9|4.1||||
|P1|11.9|12.1|Basequantity||1000|
|P2|1.9|2.1|Bulkquantity||1000|
|R|50|||||
|T|0.25|0.35||||
|W|23.7|24.3||||



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**Revision history** 

## **5 Revision history** 

**Table 11: Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|01-Apr-2015|1|First release.|
|20-May-2015|2|Text edits and formatting changes throughout document<br>In Section 2.1 Electrical characteristics (curves):<br>- updated Figure 4: Output characteristics<br>- updated Figure 5: Transfer characteristics|
|28-Jan-2016|3|Updated_Figure 13: "Output capacitance storaged energy"_|



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## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** 

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. 

No license, express or implied, to any intellectual property right is granted by ST herein. 

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. 

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. 

Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 

- © 2016 STMicroelectronics – All rights reserved 

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