# Power MOSFET, N Channel, 30 V, 9 A, 0.0195 ohm, SOT-1220, Surface Mount ![Product image](https://novapart.co/image/farnell:4415936/) **URL**: https://novapart.co/products/SSM6K504NU,LF(T/power-mosfet-n-channel-30-v-9-a-00195-ohm-sot-1220 **SKU**: SSM6K504NU,LF(T **Manufacturer**: TOSHIBA **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.0900 **Stock**: 1000+ **Lead Time**: 106 days (indicative) ## Specifications | Parameter | Value | |---|---| | Svhc | To Be Advised | | No. Of Pins | 6Pins | | Channel Type | N Channel | | Product Range | U-MOSVII-H Series | | Qualification | - | | Power Dissipation | 1.25W | | Transistor Mounting | Surface Mount | | Rds(On) Test Voltage | 10V | | Transistor Case Style | SOT-1220 | | Drain Source Voltage Vds | 30V | | Operating Temperature Max | 150°C | | Continuous Drain Current Id | 9A | | Drain Source On State Resistance | 0.0195ohm | | Gate Source Threshold Voltage Max | 2.5V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:4415936/) SSM6K504NU MOSFETs Silicon N-Channel MOS (U-MOS VI -H) ## SSM6K504NU ## 1. Applications - High-Speed Switching ## 2. Features - (1) AEC-Q101 qualified (Note 1) - (2) 4.5 V gate drive voltage. - (3) Low drain-source on-resistance - : RDS(ON) = 26 mΩ (max) (@VGS = 4.5 V) - RDS(ON) = 19.5 mΩ (max) (@VGS = 10 V) Note 1: For detail information, please contact our sales. ## 3. Packaging and Pin Assignment **==> picture [352 x 78] intentionally omitted <==** **----- Start of picture text -----**
1.2.5.6 Drain
3. Gate
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4. Source
1 2 3
<
UDFN6B
**----- End of picture text -----**
Start of commercial production 2012-07 ©2022-2023 Toshiba Electronic Devices & Storage Corporation 2023-01-18 Rev.3.0 1 SSM6K504NU ) ## 4. Absolute Maximum Ratings (Note) (Unless otherwise specified, Ta = 25 |Characteristics
~~ee~~|Symbol
~~ee~~
~~ee~~|Rating
~~ee~~|Unit
~~ee~~| |---|---|---|---| |Drain-source voltage
~~ee~~|VDSS
~~ee~~
~~ee~~
~~ee~~|30
~~ee~~
~~ee~~|V
~~ee~~
~~ie~~
~~ae~~| |Gate-source voltage
~~ee~~
~~a~~|VGSS
~~ee~~
~~ee~~
~~a~~
~~ee~~|±20
~~ee~~
~~ee~~
~~a~~
~~eee~~|| |Drain current (DC)
(Note 1)
~~ee~~|ID
~~ee ~~
~~ee~~
~~ee~~|9
~~ee ~~
~~ee~~
~~eee~~|A
~~ie~~
~~ee~~
~~ae~~
~~a~~| |Drain current (pulsed)
(Note 1,2)
~~ee~~
~~a~~|IDP
~~ee~~
~~ee~~
~~a~~|18
~~ee~~
~~eee~~
~~a~~|| |Power dissipation
(Note 3)
~~a~~|PD
~~ee ~~
~~a~~|1.25
~~eee ~~
~~a~~|W
~~ae~~
~~a~~| |Power dissipation
t≤10 s
(Note 3)
~~a~~|PD
~~a~~
~~ee~~|2.5
~~a~~
~~eee~~|W
~~a~~
Ml| |Channel temperature
~~ee~~|Tch
~~ee~~
~~ee~~|150
~~ee~~
~~eee~~|~~ee~~
Ml| |Storage temperature
~~ee~~
~~a~~|Tstg
~~ee~~
~~ee~~
~~a~~|-55 to 150
~~ee~~
~~eee~~
~~a~~|| Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 1: Ensure that the channel temperature does not exceed 150 . Note 2: Pulse width (PW) ≤ 10 ms, duty ≤ 1% Note 3: Device mounted on a FR4 board. - (25.4 mm × 25.4 mm × 1.6 mm, Cu Pad : 645 mm[2] ) Note: The MOSFETs in this device are sensitive to electrostatic discharge. When handling this device, the worktables, operators, soldering irons and other objects should be protected against anti-static discharge. Note: The channel-to-ambient thermal resistance, Rth(ch-a), and the drain power dissipation, PD, vary according to the board material, board area, board thickness and pad area. When using this device, be sure to take heat dissipation fully into account. ©2022-2023 Toshiba Electronic Devices & Storage Corporation 2023-01-18 Rev.3.0 2 SSM6K504NU ## 5. Electrical Characteristics ## 5.1. Static Characteristics (Ta = 25 °C unless otherwise specified) Characteristics Symbol Test Condition Min Typ. Max Unit Gate leakage current IGSS VGS = ±20 V, VDS = 0 V ±10 µA ~~=a~~ Drain cut-off current ~~SS$$S$ a~~ IDSS VDS = 30 V, VGS = 0 V ~~tr~~ 1 Drain-source breakdown voltage V(BR)DSS ID = 10 mA, VGS = 0 V 30 V ~~pO = GG~~ Drain-source breakdown voltage (Note 1) V(BR)DSX ID = 10 mA, VGS = -20 V 15 ~~GG~~ Gate threshold voltage (Note 2) Vth VDS = 10 V, ID = 0.1 mA 1.3 2.5 Drain-source on-resistance (Note 3) RDS(ON) ID = 4.0 A, VGS = 4.5 V 19 26 mΩ ~~aee~~ ID = 4.0 A, VGS = 10 V ~~ee ee~~ 14 19.5 ~~Gn~~ Forward transfer admittance (Note 3) |Yfs| VDS = 10 V, ID = 2.0 A 20 S Note 1: If a reverse bias is applied between gate and source, this device enters V(BR)DSX mode. Note that the drainsource breakdown voltage is lowered in this mode. Note 2: Let Vth be the voltage applied between gate and source that causes the drain current (ID) to below (0.1 mA for this device). Then, for normal switching operation, VGS(ON) must be higher than Vth, and VGS(OFF) must be lower than Vth. This relationship can be expressed as: VGS(OFF) < Vth < VGS(ON). Take this into consideration when using the device. Note 3: Pulse measurement. ## 5.2. Dynamic Characteristics (Ta = 25 °C unless otherwise specified) |Characteristics|Symbol|Test Condition|Min|Typ.|Max|Unit| |---|---|---|---|---|---|---| |Input capacitance
~~ee~~
~~ee~~|Ciss
~~ee~~|VDS= 15 V, VGS= 0 V,
f = 1 MHz
~~|-~~
~~p-~~
~~|~~
~~p-~~|~~|-[|~~
~~p-|~~|620
~~[|~~
~~|~~
~~|~~
~~|~~|~~-|~~
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~~-|~~
~~|~~
~~|~~
~~|~~| |Reverse transfer capacitance
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~~ee~~
~~ee~~|Crss
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~~p-|~~
~~|~~
~~|~~|42
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~~|~~|~~-|~~
~~-|~~
~~—-|~~|| |Output capacitance
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~~ee~~
~~ee~~||~~p- |~~
~~|~~
~~|~~
~~p-|~~|110
~~|~~
~~| ~~
~~|~~
~~|~~|~~- |~~
~~—-|~~
|| |Gate resistance
~~ee ~~
~~ee~~|rg
~~ee~~||~~|~~
~~|~~
~~p-|~~|8
~~|~~
~~||-|~~|~~—- |~~
~~|-|~~|Ω
~~|~~
~~|-||~~| |Switching time (turn-on time)
~~ee~~|ton|VDD= 15 V, ID= 1.0 A
VGS= 0 to 4.5 V, RG= 10Ω,
Duty≤1%, Input: tr, tf< 5 ns
Ground source, See Chapter 5.3
~~p-~~|~~p- |~~|26.0
~~|~~||ns
~~|~~| |Switching time (turn-off time)|toff|||16.4||| ## 5.3. Switching Time Test Circuit Fig. 5.3.1 Test Circuit of Switching Time Fig. 5.3.2 Input Waveform/Output Waveform ## 5.4. Gate Charge Characteristics (Ta = 25 ## unless otherwise specified) |Characteristics
~~Pi‘~~|Symbol
~~Pi‘~~|Test Condition
~~|~~|Min
~~|~~
~~|~~|Typ.
~~|~~|Max
~~-|~~|Unit
~~-|~~| |---|---|---|---|---|---|---| |Total gate charge (gate-source plus gate-drain)
~~Pi‘~~
~~ee~~|Qg
~~Pi‘~~
~~ee~~|VDD= 15 V, VGS= 4.5 V,
ID= 9.0 A
~~|~~
~~ee~~
~~|-~~
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~~|~~
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~~|~~
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~~|-|~~| |Gate-source charge 1
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~~|~~
~~|-|~~
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~~| ~~
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~~|-|~~|| |Gate-drain charge
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~~|~~
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~~|-|~~|~~—- |~~
~~|-|~~|| ©2022-2023 Toshiba Electronic Devices & Storage Corporation 2023-01-18 3 Rev.3.0 SSM6K504NU ## 5.5. Source-Drain Characteristics (Ta = 25 ## unless otherwise specified) |Characteristics|Symbol|Test Condition|Min|Typ.|Max|Unit| |---|---|---|---|---|---|---| |Diode forward voltage
(Note 1)|VDSF|ID= -4.0 A, VGS= 0 V||-0.85|-1.2|V| Note 1: Pulse measurement. ## 6. Marking ## 7. Internal Circuit ©2022-2023 Toshiba Electronic Devices & Storage Corporation 2023-01-18 4 Rev.3.0 SSM6K504NU ## 8. Characteristics Curves (Note) Fig. 8.1 ID - VDS **==> picture [110 x 11] intentionally omitted <==** **----- Start of picture text -----**
Fig. 8.3 RDS(ON) - VGS
**----- End of picture text -----**
**==> picture [102 x 11] intentionally omitted <==** **----- Start of picture text -----**
Fig. 8.5 RDS(ON) - ID
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**==> picture [83 x 10] intentionally omitted <==** **----- Start of picture text -----**
Fig. 8.2 ID - VGS
**----- End of picture text -----**
**==> picture [110 x 11] intentionally omitted <==** **----- Start of picture text -----**
Fig. 8.4 RDS(ON) - VGS
**----- End of picture text -----**
**==> picture [103 x 11] intentionally omitted <==** **----- Start of picture text -----**
Fig. 8.6 RDS(ON) - Ta
**----- End of picture text -----**
©2022-2023 Toshiba Electronic Devices & Storage Corporation 2023-01-18 5 Rev.3.0 SSM6K504NU Fig. 8.7 Vth - Ta Fig. 8.9 IDR - VDS Fig. 8.11 t - ID **==> picture [84 x 10] intentionally omitted <==** **----- Start of picture text -----**
Fig. 8.8 |Yfs| - ID
**----- End of picture text -----**
**==> picture [86 x 10] intentionally omitted <==** **----- Start of picture text -----**
Fig. 8.10 C - VDS
**----- End of picture text -----**
Fig. 8.12 Dynamic Input Characteristics ©2022-2023 Toshiba Electronic Devices & Storage Corporation 2023-01-18 6 Rev.3.0 SSM6K504NU Fig. 8.13 rth - tw Fig. 8.14 PD - Ta **==> picture [146 x 10] intentionally omitted <==** **----- Start of picture text -----**
Fig. 8.15 Safe Operating Area
**----- End of picture text -----**
Note: The above characteristics curves are presented for reference only and not guaranteed by production test, unless otherwise noted. ©2022-2023 Toshiba Electronic Devices & Storage Corporation 2023-01-18 7 Rev.3.0 SSM6K504NU ## Package Dimensions **==> picture [37 x 7] intentionally omitted <==** **----- Start of picture text -----**
Unit: mm
**----- End of picture text -----**
Weight: 8.5 mg (typ.) Package Name(s) TOSHIBA: 2-2AA1A Nickname: UDFN6B ©2022-2023 Toshiba Electronic Devices & Storage Corporation 2023-01-18 8 Rev.3.0 SSM6K504NU ## RESTRICTIONS ON PRODUCT USE Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as "TOSHIBA". Hardware, software and systems described in this document are collectively referred to as "Product". - TOSHIBA reserves the right to make changes to the information in this document and related Product without notice. - This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission. - Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. 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