# Power MOSFET, P Channel, 30 V, 4 A, 0.071 ohm, SOT-23F, Surface Mount ![Product image](https://novapart.co/image/farnell:3872273RL/) **URL**: https://novapart.co/products/SSM3J334R,LF(T/power-mosfet-p-channel-30-v-4-a-0071-ohm-sot-23f **SKU**: SSM3J334R,LF(T **Manufacturer**: TOSHIBA **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.3460 **Stock**: 1000+ **Lead Time**: 106 days (indicative) ## Specifications | Parameter | Value | |---|---| | Svhc | To Be Advised | | No. Of Pins | 3Pins | | Channel Type | P Channel | | Product Range | - | | Qualification | - | | Power Dissipation | 1W | | Transistor Mounting | Surface Mount | | Transistor Polarity | P Channel | | Power Dissipation Pd | 1W | | Rds(On) Test Voltage | 10V | | On Resistance Rds(On) | 0.054ohm | | Transistor Case Style | SOT-23F | | Drain Source Voltage Vds | 30V | | Operating Temperature Max | 150°C | | Continuous Drain Current Id | 4A | | Drain Source On State Resistance | 0.071ohm | | Automotive Qualification Standard | - | | Gate Source Threshold Voltage Max | 2V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:3872273RL/) SSM3J334R TOSHIBA Field-Effect Transistor Silicon P-Channel MOS Type (U-MOSVI) ## **SSM3J334R** ## ○Power Management Switch Applications Unit: mm - Low ON-resistance: RDS(ON) = 71 mΩ (max) (@VGS = -10 V) RDS(ON) = 105 mΩ (max) (@VGS = -4.5 V) RDS(ON) = 136 mΩ (max) (@VGS = -4.0 V) ## **Absolute Maximum Ratings (Ta = 25°C)** |Characteristic|Characteristic|Symbol|Symbol|Rating|Unit| |---|---|---|---|---|---| |Drain-Source voltage||VDSS||-30|V| |Gate-Source voltage||VGSS||±20|V| |Drain current|DC|ID (Note 1)||-4|A| ||Pulse|IDP(Note 1,2)||-16|| |Power dissipation||PD(Note 3)
t < 10s||1|W| ||||t < 10s|2|| |Channel temperature||Tch||150|°C| |Storage temperature range||Tstg||−55 to 150|°C| - Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). |SOT-23F|1: Gate| |---|---| ||2: Source| ||3: Drain| |JEDEC|―| |JEITA|―| |TOSHIBA|2-3Z1S| Weight: 11 mg (typ.) Note 1: The channel temperature should not exceed 150°C during use. Note 2: PW ≤ 1ms, Duty ≤ 1％ Note 3: Mounted on a FR4 board. - (25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 645 mm[2] ) ## **Marking Equivalent Circuit (Top View)** **==> picture [246 x 91] intentionally omitted <==** **----- Start of picture text -----**
3 3
KFL
1 2 1 2
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Start of commercial production 2010-08 1 2018-10-04 © 2010 - 2018 Toshiba Electronic Devices & Storage Corporation SSM3J334R ## **Electrical Characteristics (Ta = 25°C)** |Characteristic|Characteristic|Symbol|Test Conditions|Min|Typ.|Max|Unit| |---|---|---|---|---|---|---|---| |Drain-Source breakdown voltage||V(BR)DSS|ID= -10 mA, VGS= 0 V|-30|||V| |||V(BR) DSX|ID= -10 mA, VGS= 10 V.(Note 5)|-21|||V| |Drain cut-off current||IDSS|VDS= -30 V, VGS= 0 V|||-1|µA| |Gate leakage current||IGSS|VGS=±16 V, VDS= 0 V|||±10|µA| |Gate threshold voltage||Vth|VDS= -10 V, ID= -100µA|-0.8||-2.0|V| |Forward transfer admittance||Yfs|VDS= -10 V, ID= -1.0 A
(Note 4)|2.3|4.6||S| |Drain–source ON-resistance||RDS (ON)|ID= -3.0 A, VGS= -10 V
(Note 4)||54|71|mΩ| ||||ID= -2.0 A, VGS= -4.5 V
(Note 4)||80|105|| ||||ID= -1.0 A, VGS= -4.0 V
(Note 4)||89|136|| |Input capacitance||Ciss|VDS= -15 V, VGS= 0 V
f = 1 MHz||280||pF| |Output capacitance||Coss|||55||| |Reverse transfer capacitance||Crss|||40||| |Switching time|Turn-on time|ton|VDD= -15 V, ID= -1.0 A
VGS= 0 to -4.5 V, RG= 10Ω||13||ns| ||Turn-off time|toff|||22||| |Total Gate Charge||Qg|VDD= -15 V, ID= -4.0 A,
VGS= -10 V||5.9||nC| |Gate-Source Charge||Qgs1|||0.8||| |Gate-Drain Charge||Qgd|||1.2||| |Drain-Source forward voltage||VDSF|ID= 4.0 A, VGS= 0 V
(Note 4)||0.9|1.2|V| Note4: Pulse test Note5: If a forward bias is applied between gate and source, this device enters V(BR)DSX mode. Note that the drain-source breakdown voltage is lowered in this mode. ## **Switching Time Test Circuit** ## **(a) Test Circuit** **==> picture [409 x 152] intentionally omitted <==** **----- Start of picture text -----**
(b) VIN 0 V 90%
OUT
0
IN 10%
−4.5 V
−4.5V
RL (c) VOUT VDS (ON)
90%
10 µs VDD
VDD = -15 V
10%
RG = 10 Ω VDD
Duty ≤ 1% tr tf
VIN: tr, tf < 5 ns
Common Source ton toff
Ta = 25°C
G
R
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## **Notice on Usage** Let Vth be the voltage applied between gate and source that causes the drain current (ID) to be low (-100μA for the SSM3J334R). Then, for normal switching operation, VGS(on) must be higher than Vth, and VGS(off) must be lower than Vth. This relationship can be expressed as: VGS(off) < Vth < VGS(on). Take this into consideration when using the device. ## **Handling Precaution** When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that come into direct contact with devices should be made of antistatic materials. Thermal resistance Rth (ch-a) and power dissipation PD vary depending on board material, board area, board thickness and pad area. When using this device, please take heat dissipation into consideration 2 2018-10-04 © 2010 - 2018 Toshiba Electronic Devices & Storage Corporation SSM3J334R **==> picture [212 x 698] intentionally omitted <==** **----- Start of picture text -----**
ID – VDS
-10
-10 V -4.5 V
VGS = -4.0 V
-8
-6
-4
-2
Common Source
Ta = 25 °C
Pulse test
0
0 -0.5 -1.0 -1.5 -2.0
Drain–source voltage VDS (V)
RDS (ON) – VGS
200
ID = -1.0 A
Common Source
Pulse test
150
100
Ta = 100 °C
25 °C
50
− 25 °C
0
0 -4 -8 -12 -16 -20
Gate–source voltage VGS (V)
RDS (ON) – ID
200
Common Source
Ta = 25 °C
Pulse test
150
-4.0 V
100
-4.5 V
50
VGS = -10 V
0
0 -2.0 -4.0 -6.0 -8.0 -10.0
Drain current ID (A)
(A)
D
Drain current I
(mΩ)
DS (ON)
R
Drain–source ON-resistance
(mΩ)
DS (ON)
R
Drain–source ON-resistance
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ID – VGS
-100
Common Source
VDS = -10 V
-10
Pulse test
-1
-0.1
-0.01 Ta = 100 ° C
−25 °C
-0.001
25 °C
-0.0001
0 -1.0 -2.0 -3.0 -4.0
Gate–source voltage VGS (V)
(A)
D
Drain current I
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**==> picture [200 x 205] intentionally omitted <==** **----- Start of picture text -----**
RDS (ON) – VGS
200
ID = -2.0 A
Common Source
Pulse test
150
100
Ta = 100 °C
25 °C
50
− 25 °C
0
0 -4 -8 -12 -16 -20
Gate–source voltage VGS (V)
(mΩ)
DS (ON)
R
Drain–source ON-resistance
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RDS (ON) – Ta
200
Common Source
Pulse test
150 ID = -1.0 A / VGS = -4.0 V
100 -2.0 A / -4.5 V
-3.0 A / -10 V
50
0
−50 0 50 100 150
Ambient temperature Ta (°C)
(mΩ)
DS (ON)
R
Drain–source ON-resistance
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3 2018-10-04 © 2010 - 2018 Toshiba Electronic Devices & Storage Corporation SSM3J334R **==> picture [200 x 209] intentionally omitted <==** **----- Start of picture text -----**
Vth – Ta
-2.0
Common Source
VDS = -10 V
ID = -100 μA
-1.6
-1.2
-0.8
-0.4
0
−50 0 50 100 150
Ambient temperature Ta (°C)
(V)
th
Gate threshold voltage V
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|Yfs| – ID
100
Common Source
VDS = -10 V
30 Ta = 25 °C
Pulse test
10
3.0
1.0
0.3
0.1
-0.01 -0.1 -1 -10 -100
Drain current ID (A)
(S)

fs
Y

Forward transfer admittance
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**==> picture [444 x 207] intentionally omitted <==** **----- Start of picture text -----**
C – VDS Dynamic Input Characteristic
1000 -10
500
300
-8
Ciss VDD = -15 V
100
50 Coss -6 VDD = -24 V
30
Crss
-4
10
5 Common Source -2
3 Ta = 25 °C Common Source
f = 1 MHz ID = -4.0 A
VGS = 0 V Ta = 25 °C
1 -0.1 -1 -10 -100 0 0 2 4 6 8
Drain–source voltage VDS (V) Total Gate Charge Qg (nC)
(V)
GS
Capacitance C (pF)
Gate–source voltage V
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t – ID
10000
Common Source
VDD = -15 V
V GS = 0 to -4.5 V
Ta = 25 °C
1000 RG = 10Ω
toff
100 tf
ton
10
tr
1
- -0.001 -0.01 -0.1 -1 -10
Drain current ID (A)
Switching time t (ns)
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**==> picture [203 x 197] intentionally omitted <==** **----- Start of picture text -----**
IDR – VDS
100
Common Source
VGS = 0 V
Pulse test
D
10
IDR
G
S
1
0.1
0.01 25 °C
100 °C
−25 ° C
0.001
0 0.2 0.4 0.6 0.8 1.0 1.2
Drain–source voltage VDS (V)
(A)
DR
Drain reverse current I
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4 2018-10-04 © 2010 - 2018 Toshiba Electronic Devices & Storage Corporation SSM3J334R **==> picture [216 x 215] intentionally omitted <==** **----- Start of picture text -----**
rth – tw
1000
b
a
100
10
Single pulse
a. Mounted on FR4 board
(25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 645 mm [2] )
b. Mounted on FR4 board
(25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 0.72 mm [2 ] ×3)
1
0.001 0.01 0.1 1 10 100 1000
Pulse width tw (s)
(°C/W )
th
Transient thermal impedance r
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PD – Ta
1600 a: Mounted on FR4 board
(25.4mm × 25.4mm × 1.6mm , Cu Pad: 645 mm [2] )
b: Mounted on FR4 board
(25.4mm × 25.4mm × 1.6mm , Cu Pad: 0.72 mm [2] ×3)
1200
a
800
b
400
0
-40 -20 0 20 40 60 80 100 120 140 160
Ambient temperature Ta (°C)
(mW)
D
Power dissipation P
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2018-10-04 5 © 2010 - 2018 Toshiba Electronic Devices & Storage Corporation SSM3J334R ## **RESTRICTIONS ON PRODUCT USE** Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as “TOSHIBA”. Hardware, software and systems described in this document are collectively referred to as “Product”. - TOSHIBA reserves the right to make changes to the information in this document and related Product without notice. - This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission. - Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for. 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