# Power MOSFET, N Channel, 80 V, 18 A, 0.015 ohm, PowerPAK 1212, Surface Mount
**URL**: https://novapart.co/products/SQSA80ENW-T1_GE3/power-mosfet-n-channel-80-v-18-a-0015-ohm-powerpak
**SKU**: SQSA80ENW-T1_GE3
**Manufacturer**: VISHAY
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.4450
**Stock**: 1000+
**Lead Time**: 2 days (indicative)
## Description
Transistor Polarity:N Channel; Continuous Drain Current Id:18A; Drain Source Voltage Vds:80V; On Resistance Rds(on):0.015ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:2
## Specifications
| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Product Range | TrenchFET |
| Qualification | AEC-Q101 |
| Power Dissipation | 62.5W |
| Transistor Mounting | Surface Mount |
| Transistor Polarity | N Channel |
| Power Dissipation Pd | 62.5W |
| Rds(On) Test Voltage | 10V |
| On Resistance Rds(On) | 0.015ohm |
| Transistor Case Style | PowerPAK 1212 |
| Drain Source Voltage Vds | 80V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 18A |
| Drain Source On State Resistance | 0.015ohm |
| Automotive Qualification Standard | AEC-Q101 |
| Gate Source Threshold Voltage Max | 2V |
## Datasheet
📄 [Download PDF](https://novapart.co/datasheet/farnell:2771839RL/)
**SQSA80ENW**
Vishay Siliconix
www.vishay.com
## **Automotive N-Channel 80 V (D-S) 175 °C MOSFET**
## **FEATURES**
**PowerPAK[®] 1212-8W Single** D • TrenchFET[®] power MOSFET **D** D **7** 8 • AEC-Q101 qualified **D 6 5** • 100 % Rg and UIS tested • for definitions of compliance please see Material categorization: pies www.vishay.com/doc?99912 **1 2 S 3 S** D 1 **4 S** G Top View Bottom View **Marking code:** Q029 **PRODUCT SUMMARY** G VDS (V) 80 RDS(on) ( ) at VGS = 10 V 0.021 RDS(on) ( ) at VGS = 4.5 V 0.027 S ID (A) 18 Configuration Single N-Channel MOSFET Package PowerPAK 1212-8W ~~=== “ Ce~~ **ABSOLUTE MAXIMUM RATINGS** (TC = 25 °C, unless otherwise noted) ~~es~~ **PARAMETER SYMBOL LIMIT UNIT** Drain-source voltage V ~~ec~~ DS 80 V ~~ee~~ Gate-source voltage VGS ± 20 TC = 25 °C 18 Continuous drain current[a] ID TC = 125 °C 18 ~~ee~~ Continuous source current (diode conduction)[ a] IS 18 A Pulsed drain current[b] IDM 72 ~~————~~ Single pulse avalanche current L = 0.1 mH IAS ~~ee~~ 22 ~~=~~ Single pulse avalanche energy ~~—>s ee~~ EAS 24.2 mJ TC = 25 °C 62.5 Maximum power dissipation[b] PD W ~~a~~ TC = 125 °C ~~SO~~ 20 ~~a~~ Operating junction and storage temperature range TJ, Tstg -55 to +175 °C ~~ee~~ Soldering recommendations (peak temperature)[ e, f] 260 **THERMAL RESISTANCE RATINGS PARAMETER SYMBOL LIMIT UNIT** Junction-to-ambient PCB mount[ c] RthJA 81 °C/W Junction-to-case (drain) RthJC 2.4
## **Notes**
a. Package limited
- b. Pulse test; pulse width 300 μs, duty cycle 2 %
- c. When mounted on 1" square PCB (FR4 material)
- d. Parametric verification ongoing
- e. See solder profile (www.vishay.com/doc?73257). The PowerPAK 1212-8W is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection
- f. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components
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Document Number: 66501
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**SQSA80ENW**
Vishay Siliconix
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|**SPECIFICATIONS**(TC= 25 °C,unless otherwise noted)|**SPECIFICATIONS**(TC= 25 °C,unless otherwise noted)|**SPECIFICATIONS**(TC= 25 °C,unless otherwise noted)|**SPECIFICATIONS**(TC= 25 °C,unless otherwise noted)|||||
|---|---|---|---|---|---|---|---|
|**PARAMETER**|**SYMBOL**|**TEST CONDITIONS**||**MIN.**|**TYP.**|**MAX.**|**UNIT**|
|**Static**||||||||
|Drain-source breakdown voltage|VDS|VGS= 0, ID= 250 μA||80|-|-|V|
|Gate-source threshold voltage|VGS(th)|VDS= VGS, ID= 250 μA||1.5|2.0|2.5||
|Gate-source leakage|IGSS|VDS= 0 V, VGS= ± 20 V||-|-|± 100|nA|
|Zero gate voltage drain current|IDSS|VGS= 0 V|VDS= 80 V|-|-|1|μA|
|||VGS= 0 V|VDS= 80 V, TJ= 125 °C|-|-|50||
|||VGS= 0 V|VDS= 80 V, TJ= 175 °C|-|-|150||
|On-state drain currenta|ID(on)|VGS= 10 V|VDS 5 V|20|-|-|A|
|Drain-source on-state resistancea|RDS(on)|VGS= 10 V|ID= 10 A|-|0.015|0.021||
|||VGS= 10 V|ID= 10 A, TJ= 125 °C|-|-|0.034||
|||VGS= 10 V|ID= 10 A, TJ= 175 °C|-|-|0.044||
|||VGS= 4.5 V|ID= 10 A|-|0.018|0.027||
|Forward transconductanceb|gfs|VDS= 15 V, ID= 10 A||-|35|-|S|
|**Dynamicb**||||||||
|Input capacitance|Ciss|VGS= 0 V|VDS= 40 V, f = 1 MHz|-|1086|1358|pF|
|Output capacitance|Coss|||-|422|527||
|Reverse transfer capacitance|Crss|||-|15|19||
|Totalgate chargec|Qg|VGS= 10 V|VDS= 40 V, ID= 4 A|-|17|21|nC|
|Gate-source chargec|Qgs|||-|3|-||
|Gate-drain chargec|Qgd|||-|2|-||
|Gate resistance|Rg|f = 1 MHz||0.27|0.45|0.73||
|Turn-on delay timec|td(on)|VDD= 40 V, RL= 10
ID 4 A, VGEN= 10 V, Rg= 1||-|9|12|ns|
|Rise timec|tr|||-|2|3||
|Turn-off delay timec|td(off)|||-|19|24||
|Fall timec|tf|||-|5|7||
|**Source-Drain Diode Ratings and Characteristicb**||||||||
|Pulsed currenta|ISM|||-|-|72|A|
|Forward voltage|VSD|IF= 10 A, VGS= 0 V||-|0.82|1.1|V|
|Body diode reverse recovery time|trr|IF= 5 A, dI/dt = 100 A/μs||-|36|45|ns|
|Body diode reverse recovery charge|Qrr|||-|38|48|nC|
|Reverse recovery fall time|ta|||-|19|-|ns|
|Reverse recovery rise time|tb|||-|18|-||
|Body diode peak reverse recovery current|IRM(REC)|||-|-1.9|-4|A|
## **Notes**
a. Pulse test; pulse width 300 μs, duty cycle 2 %
b. Guaranteed by design, not subject to production testing
c. Independent of operating temperature
_Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability._
S18-1115-Rev. B, 05-Nov-2018
Document Number: 66501
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**SQSA80ENW**
Vishay Siliconix
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## **TYPICAL CHARACTERISTICS** (TA = 25 °C, unless otherwise noted)
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Axis Title
90 10000
VGS = 10 V thru 5 V
72
VGS = 4 V 1000
54
36
100
18 VGS = 3 V
0 10
0 2 4 6 8 10
VDS - Drain-to-Source Voltage (V)
2nd line
2nd line 1st line 2nd line
- Drain Current (A)
ID
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## **Output Characteristics**
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Axis Title
80 10000
64
1000
48
32
100
16 T C = 125 °C TC = 25 °C
TC = -55 °C
0 10
0 2 4 6 8 10
VGS - Gate-to-Source Voltage (V)
2nd line
2nd line 1st line 2nd line
- Drain Current (A)
ID
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## **Transfer Characteristics**
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Axis Title
75 10000
TC = 25 °C TC = -55 °C
60
1000
45
30 T C = 125 °C
100
15
0 10
0 6 12 18 24 30
ID - Drain Current (A)
2nd line
2nd line 1st line 2nd line
- Transconductance (S)
fs
g
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**Transconductance**
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Axis Title
0.05 10000
0.04
1000
0.03
VGS = 4.5 V
0.02
100
0.01 V GS = 10 V
0.00 10
0 13 26 39 52 65
ID - Drain Current (A)
2nd line
2nd line 1st line 2nd line
- On-Resistance (Ω)
DS(on)
R
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**On-Resistance vs. Drain Current**
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Axis Title
1500 10000
1200
Ciss 1000
900
600
100
Coss
300
Crss
0 10
0 20 40 60 80
VDS - Drain-to-Source Voltage (V)
2nd line
2nd line 1st line 2nd line
C - Capacitance (pF)
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Capacitance
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Axis Title
10 10000
ID = 4 A
8 V DS = 40 V
1000
6
4
100
2
0 10
0 4 8 12 16 20
Qg - Total Gate Charge (nC)
2nd line
2nd line 1st line 2nd line
- Gate-to-Source Voltage (V)
GS
V
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## **Gate Charge**
Document Number: 66501
S18-1115-Rev. B, 05-Nov-2018
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**SQSA80ENW**
Vishay Siliconix
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www.vishay.com
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## **TYPICAL CHARACTERISTICS** (TA = 25 °C, unless otherwise noted)
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Axis Title
2.5 10000
2.1 ID = 6A V GS = 10 V
1000
1.7
1.3 VGS = 4.5 V
100
0.9
0.5 10
-50 -25 0 25 50 75 100 125 150 175
TJ - Junction Temperature (°C)
2nd line
2nd line 1st line 2nd line
- On-Resistance (Normalized)
DS(on)
R
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## **On-Resistance vs. Junction Temperature**
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Axis Title
100 10000
10 TJ = 150 ° C
1000
1
T J = 25 °C
0.1
100
0.01
0.001 10
0 0.2 0.4 0.6 0.8 1.0 1.2
VSD - Source-to-Drain Voltage (V)
2nd line
2nd line 1st line 2nd line
- Source Current (A)
IS
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## **Source Drain Diode Forward Voltage**
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Axis Title
0.10 10000
0.08
1000
0.06
0.04
TJ = 150 °C 100
0.02
TJ = 25 °C
0.00 10
0 2 4 6 8 10
VGS - Gate-to-Source Voltage (V)
2nd line
2nd line 1st line 2nd line
- On-Resistance (Ω)
DS(on)
R
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**On-Resistance vs. Gate-to-Source Voltage**
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Axis Title
0.5 10000
0.2
1000
-0.1
ID = 5 mA
-0.4
100
-0.7 ID = 250 μA
-1.0 10
-50 -25 0 25 50 75 100 125 150 175
TJ - Temperature (°C)
2nd line
2nd line Variance (V) 1st line 2nd line
GS(th)
V
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**Threshold Voltage**
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Axis Title
105 10000
101 I D = 1 mA
1000
97
93
100
89
85 10
-50 -25 0 25 50 75 100 125 150 175
TJ - Junction Temperature (°C)
2nd line
2nd line 1st line 2nd line
- Drain-to-Source Voltage (V)
DS
V
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**Drain Source Breakdown vs. Junction Temperature**
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Axis Title
1000 10000
I DM limited
100
100 μs 1000
10
I D limited 1 ms
1 10 ms
Limited by R DS(on) (1) 100 ms, 1 s, 10 s, DC100
0.1
TC = 25 °C BVDSS limited
Single pulse
0.01 10
0.01 0.1 1 10 100 1000
VDS - Drain-to-Source Voltage (V)
(1) VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area
2nd line 1st line 2nd line
- Drain Current (A)
ID
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S18-1115-Rev. B, 05-Nov-2018
Document Number: 66501
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**SQSA80ENW**
Vishay Siliconix
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www.vishay.com
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## **THERMAL RATINGS** (TA = 25 °C, unless otherwise noted)
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1
Duty cycle = 0.5
0.2
0.1 Notes:
0.1
P DM
0.05
t1
0.02 1. Duty cycle, D = t2 tt12
2. Per unit base = RthJA = 81 °C/W
Single pulse 3. TJM - TA = PDMZthJA [(t)]
4. Surface mounted
0.01
10 [-4] 10 [-3] 10 [-2] 10 [-1] 1 10 100 1000
Square Wave Pulse Duration (s)
Thermal Impedance
Normalized Effective Transient
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**Normalized Thermal Transient Impedance, Junction-to-Ambient**
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2
1
Duty cycle = 0.5
0.2
0.1
0.1 Single pulse
0.05
0.02
0.01
10 [-4] 10 [-3] 10 [-2] 10 [-1] 1
Square Wave Pulse Duration (s)
Thermal Impedance
Normalized Effective Transient
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**Normalized Thermal Transient Impedance, Junction-to-Case**
## **Note**
- The characteristics shown in the two graphs
- Normalized Transient Thermal Impedance Junction-to-Ambient (25 °C)
- Normalized Transient Thermal Impedance Junction-to-Case (25 °C)
- are given for general guidelines only to enable the user to get a “ball park” indication of part capabilities. The data are extracted from single pulse transient thermal impedance characteristics which are developed from empirical measurements. The latter is valid for the part mounted on printed circuit board - FR4, size 1" x 1" x 0.062", double sided with 2 oz. copper, 100 % on both sides. The part capabilities can widely vary depending on actual application parameters and operating conditions
_Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see www.vishay.com/ppg?66501._
S18-1115-Rev. B, 05-Nov-2018
Document Number: 66501
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**Package Information**
Vishay Siliconix
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## **PowerPAK[®] 1212-8W Case Outline**
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L
H E2 K
W A2 E4
1 8 1
Z
2 7 2
2
3 6 3
4 5 4
L1 E3
Backside view of single pad
θ θ A1
Notes
1 Inch will govern
2 Dimensions exclusive of mold gate burrs
3 Dimensions exclusive of mold flash and
2 cutting burrs
E1 Detail Z
E
D4
θ
M
e
D1 D D2 D5
b
θ
A
c
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|**DIM.**|**MILLIMETERS**|**MILLIMETERS**|**MILLIMETERS**|**INCHES**|**INCHES**|**INCHES**|
|---|---|---|---|---|---|---|
||**MIN.**|**NOM.**|**MAX.**|**MIN.**|**NOM.**|**MAX.**|
|A|0.97|1.04|1.12|0.038|0.041|0.044|
|A1|0|-|0.05|0|-|0.002|
|A2|0|-|0.13|0|-|0.005|
|b|0.23|0.30|0.41|0.009|0.012|0.016|
|c|0.23|0.28|0.33|0.009|0.011|0.013|
|D|3.20|3.30|3.40|0.126|0.130|0.134|
|D1|2.95|3.05|3.15|0.116|0.120|0.124|
|D2|1.98|2.11|2.24|0.078|0.083|0.088|
|D4|0.47 typ.|||0.0185 typ.|||
|D5|2.3 typ.|||0.090 typ.|||
|E|3.20|3.30|3.40|0.126|0.130|0.134|
|E1|2.95|3.05|3.15|0.116|0.120|0.124|
|E2|1.47|1.60|1.73|0.058|0.063|0.068|
|E3|1.75|1.85|1.98|0.069|0.073|0.078|
|E4|0.34 typ.|||0.013 typ.|||
|e|0.65 BSC.|||0.026 BSC|||
|K|0.86 typ.|||0.034 typ.|||
|H|0.30|0.41|0.51|0.012|0.016|0.020|
|L|0.30|0.43|0.56|0.012|0.017|0.022|
|L1|0.06|0.13|0.20|0.002|0.005|0.008|
||0°|-|12°|0°|-|12°|
|W|0.15|0.25|0.36|0.006|0.010|0.014|
|M|0.125 typ.|||0.005 typ.|||
|ECN: C15-1530-Rev. B, 16-Nov-15
DWG: 6032|||||||
ECN: C15-1530-Rev. B, 16-Nov-15 DWG: 6032
Revision: 16-Nov-15
Document Number: 64614
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**AN822**
Vishay Siliconix
## **PowerPAK**[®]
## **1212 Mounting and Thermal Considerations**
## **Johnson Zhao**
MOSFETs for switching applications are now available with die on resistances around 1 m Ω and with the capability to handle 85 A. While these die capabilities represent a major advance over what was available just a few years ago, it is important for power MOSFET packaging technology to keep pace. It should be obvious that degradation of a high performance die by the package is undesirable. PowerPAK is a new package technology that addresses these issues. The PowerPAK 1212-8 provides ultra-low thermal impedance in a small package that is ideal for space-constrained applications. In this application note, the PowerPAK 1212-8’s construction is described. Following this, mounting information is presented. Finally, thermal and electrical performance is discussed.
## **THE PowerPAK PACKAGE**
The PowerPAK 1212-8 package (Figure 1) is a derivative of PowerPAK SO-8. It utilizes the same packaging technology, maximizing the die area. The bottom of the die attach pad is exposed to provide a direct, low resistance thermal path to the substrate the device is mounted on. The PowerPAK 1212-8 thus translates the benefits of the PowerPAK SO-8 into a smaller package, with the same level of thermal performance. (Please refer to application note “PowerPAK SO-8 Mounting and Thermal Considerations.”)
The PowerPAK 1212-8 has a footprint area comparable to TSOP-6. It is over 40 % smaller than standard TSSOP-8. Its die capacity is more than twice the size of the standard TSOP-6’s. It has thermal performance an order of magnitude better than the SO-8, and 20 times better than TSSOP-8. Its thermal performance is better than all current SMT packages in the market. It will take the advantage of any PC board heat sink capability. Bringing the junction temperature down also
increases the die efficiency by around 20 % compared with TSSOP-8. For applications where bigger packages are typically required solely for thermal consideration, the PowerPAK 1212-8 is a good option.
Both the single and dual PowerPAK 1212-8 utilize the same pin-outs as the single and dual PowerPAK SO-8. The low 1.05 mm PowerPAK height profile makes both versions an excellent choice for applications with space constraints.
## **PowerPAK 1212 SINGLE MOUNTING**
To take the advantage of the single PowerPAK 1212-8’s thermal performance see Application Note 826,
_Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs._ Click on the PowerPAK 1212-8 single in the index of this document.
In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-toambient thermal resistance. Under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in[2] of will yield little improvement in thermal performance.
**Figure 1.** PowerPAK 1212 Devices
Document Number 71681 03-Mar-06
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1
**AN822** ~~oC~~ Vishay Siliconix
## **PowerPAK 1212 DUAL**
To take the advantage of the dual PowerPAK 1212-8’s thermal performance, the minimum recommended land pattern can be found in Application Note 826, _Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs_ . Click on the PowerPAK 1212-8 dual in the index of this document.
ture profile used, and the temperatures and time duration, are shown in Figures 2 and 3. For the lead (Pb)-free solder profile, see http://www.vishay.com/ doc?73257.
The gap between the two drain pads is 10 mils. This matches the spacing of the two drain pads on the PowerPAK 1212-8 dual package.
This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-toambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in[2] of will yield little improvement in thermal performance.
## **REFLOW SOLDERING**
Vishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a preconditioning test and are then reliability-tested using temperature cycle, bias humidity, HAST, or pressure pot. The solder reflow tempera-
|Ramp-Up Rate|+ 6°C /Second Maximum|
|---|---|
|Temperature at 155 ± 15°C|120 Seconds Maximum|
|Temperature Above 180°C|70 - 180 Seconds|
|Maximum Temperature|240 + 5/- 0°C|
|Time at Maximum Temperature|20 - 40 Seconds|
|Ramp-Down Rate|+ 6°C/Second Maximum|
**Figure 2.** Solder Reflow Temperature Profile
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| 10 s (max) |
210 - 220 °C —_—_
3 °C/s (max) —— 4 °C/s (max)
183 °C
140 - 170 °C | |
50 s (max)
pe —|
| |
3° C/s (max) 60 s (min) Reflow Zone
Pre-Heating Zone
| i |
Maximum peak temperature at 240 °C is allowed.
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**Figure 3.** Solder Reflow Temperatures and Time Durations
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Document Number 71681 03-Mar-06
**AN822**
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Vishay Siliconix
|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|
|---|---|---|---|---|---|---|---|---|---|---|
|**Package**|**SO-8**||**TSSOP-8**||**TSOP-8**||**PPAK 1212**||**PPAK SO-8**||
|**Configuration**|**Single**|**Dual**|**Single**|**Dual**|**Single**|**Dual**|**Single**|**Dual**|**Single**|**Dual**|
|Thermal Resiatance RthJC(C/W)|20|40|52|83|40|90|2.4|5.5|1.8|5.5|
||||||||||||
|PowerPAK 1212
Standard SO-8
Standard TSSOP-8
TSOP-6|||||||||||
|2.4 °C/W
49.8 °C
20 °C/W
85 °C
PC Board at 45 °C
52 °C/W
149 °C
40 °C/W
125 °C|||||||||||
||||||||||||
**Figure 4.** Temperature of Devices on a PC Board
## **THERMAL PERFORMANCE**
## **Introduction**
## **Spreading Copper**
A basic measure of a device’s thermal performance is the junction-to-case thermal resistance, R θ jc, or the junction to- foot thermal resistance, R θ jf. This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows a comparison of the PowerPAK 1212-8, PowerPAK SO-8, standard TSSOP-8 and SO-8 equivalent steady state performance.
By minimizing the junction-to-foot thermal resistance, the MOSFET die temperature is very close to the temperature of the PC board. Consider four devices mounted on a PC board with a board temperature of 45 °C (Figure 4). Suppose each device is dissipating 2 W. Using the junction-to-foot thermal resistance characteristics of the PowerPAK 1212-8 and the other SMT packages, die temperatures are determined to be 49.8 °C for the PowerPAK 1212-8, 85 °C for the standard SO-8, 149 °C for standard TSSOP-8, and 125 °C for TSOP-6. This is a 4.8 °C rise above the board temperature for the PowerPAK 1212-8, and over 40 °C for other SMT packages. A 4.8 °C rise has minimal effect on r whereas a rise DS(ON) of over 40 °C will cause an increase in rDS(ON) as high as 20 %.
Designers add additional copper, spreading copper, to the drain pad to aid in conducting heat from a device. It is helpful to have some information about the thermal performance for a given area of spreading copper.
Figure 5 and Figure 6 show the thermal resistance of a PowerPAK 1212-8 single and dual devices mounted on a 2-in. x 2-in., four-layer FR-4 PC boards. The two internal layers and the backside layer are solid copper. The internal layers were chosen as solid copper to model the large power and ground planes common in many applications. The top layer was cut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken. The results indicate that an area above 0.2 to 0.3 square inches of spreading copper gives no additional thermal performance improvement. A subsequent experiment was run where the copper on the back-side was reduced, first to 50 % in stripes to mimic circuit traces, and then totally removed. No significant effect was observed.
Document Number 71681 03-Mar-06
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3
**AN822**
## Vishay Siliconix
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**----- Start of picture text -----**
105
Spreading Copper (sq. in.)
95
85
75
65
100 %
55
50 %
0 %
45
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Figure 5. Spreading Copper - Si7401DN
(°C/W)
A
J
Rht
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**----- Start of picture text -----**
130
120 Spreading Copper (sq. in.)
110
100
90
80
50 % 100 %
70
0 %
60
50
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
(°C/W)
A
RhJ t
**----- End of picture text -----**
**Figure 6.** Spreading Copper - Junction-to-Ambient Performance
## **CONCLUSIONS**
As a derivative of the PowerPAK SO-8, the PowerPAK 1212-8 uses the same packaging technology and has been shown to have the same level of thermal performance while having a footprint that is more than 40 % smaller than the standard TSSOP-8.
Recommended PowerPAK 1212-8 land patterns are provided to aid in PC board layout for designs using this new package.
The PowerPAK 1212-8 combines small size with attractive thermal characteristics. By minimizing the thermal rise above the board temperature, PowerPAK simplifies thermal design considerations, allows the device to run cooler, keeps rDS(ON) low, and permits the device to handle more current than a same- or larger-size MOSFET die in the standard TSSOP-8 or SO-8 packages.
www.vishay.com 4
Document Number 71681 03-Mar-06
**Application Note 826**
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## Vishay Siliconix
## **RECOMMENDED MINIMUM PADS FOR PowerPAK[®] 1212-8 Single**
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**----- Start of picture text -----**
0.152
(3.860)
0.039 0.068 0.010
(0.990) (1.725) (0.255)
0.016
(0.405)
0.026
(0.660)
0.025 0.030
(0.635) (0.760)
0.088 (2.235) 0.094 (2.390)
**----- End of picture text -----**
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**----- Start of picture text -----**
Return to Index
**----- End of picture text -----**
Return to Index
Recommended Minimum Pads Dimensions in Inches/(mm)
Document Number: 72597 Revision: 21-Jan-08
www.vishay.com
7
**Legal Disclaimer Notice** Vishay
www.vishay.com
**==> picture [59 x 48] intentionally omitted <==**
## **Disclaimer**
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
_**© 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED**_
Revision: 08-Feb-17
Document Number: 91000
**1**
## Links
- [View this product on Novapart](https://novapart.co/products/SQSA80ENW-T1_GE3/power-mosfet-n-channel-80-v-18-a-0015-ohm-powerpak)
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---
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