# Bipolar Pre-Biased / Digital Transistor, Dual NPN, 50 V, 100 mA, 4.7 kohm, 4.7 kohm ![Product image](https://novapart.co/image/farnell:3617436/) **URL**: https://novapart.co/products/SMUN5232DW1T1G/bipolar-pre-biased-digital-transistor-dual-npn-50 **SKU**: SMUN5232DW1T1G **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || Transistors || Bipolar Transistors || Pre-Biased / Digital Bipolar Transistors **Price**: €0.0260 **Stock**: 10+ **Lead Time**: 92 days (indicative) ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | No SVHC (25-Jun-2025) | | No. Of Pins | 6 Pin | | Product Range | MUN5232DW1 Series | | Qualification | AEC-Q101 | | Power Dissipation | 385mW | | Transistor Mounting | Surface Mount | | Transistor Polarity | Dual NPN | | Transistor Case Style | SOT-363 | | Base Input Resistor R1 | 4.7kohm | | Dc Current Gain Hfe Min | 15hFE | | Base Emitter Resistor R2 | 4.7kohm | | Operating Temperature Max | 150°C | | Continuous Collector Current | 100mA | | Collector Emitter Voltage Max Npn | 50V | | Collector Emitter Voltage Max Pnp | - | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:3617436/) ## MUN5232DW1, NSBC143EDXV6, NSBC143EDP6 ## Dual NPN Bias Resistor Transistors R1 = 4.7 k R2 = 4.7 k **www.onsemi.com** ## **NPN Transistors with Monolithic Bias Resistor Network** This series of digital transistors is designed to replace a single device and its external resistor bias network. The Bias Resistor Transistor (BRT) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base-emitter resistor. The BRT eliminates these individual components by integrating them into a single device. The use of a BRT can reduce both system cost and board space. ## **Features** **==> picture [144 x 144] intentionally omitted <==** **----- Start of picture text -----**
PIN CONNECTIONS
(3) (2) (1)
R1 R2
Q1
Q2
R2 R1
(4) (5) (6)
**----- End of picture text -----**
- Simplifies Circuit Design - Reduces Board Space ## **MARKING DIAGRAMS** - Reduces Component Count • S and NSV Prefix for Automotive and Other Applications 6 Requiring Unique Site and Control Change Requirements; **SOT−363** 7J M AEC-Q101 Qualified and PPAP Capable **CASE 419B−02** e • These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS 1 Compliant **MAXIMUM RATINGS** (TA = 25 ° C, common for Q1 and Q2, unless otherwise noted) **CASE 463ASOT−563** 7J M **Rating Symbol Max Unit** ¢ 1 Collector-Base Voltage VCBO 50 Vdc Collector-Emitter Voltage VCEO 50 Vdc **SOT−963** T M Collector Current − Continuous IC 100 mAdc **CASE 527AD** Input Forward Voltage VIN(fwd) 30 Vdc 1 ~~——~~ Input Reverse Voltage VIN(rev) 10 Vdc 7J/T = Specific Device Code Stresses exceeding those listed in the Maximum Ratings table may damage the e M = Date Code* device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. = Pb-Free Package (Note: Microdot may be in either location) ## **ORDERING INFORMATION** - *Date Code orientation may vary depending upon manufacturing location. |**ORDERING INFORMATION**||| |---|---|---| |**Device**|**Package**|**Shipping**†| |MUN5232DW1T1G,
SMUN5232DW1T1G|SOT−363|3,000/Tape & Reel| |NSBC143EDXV6T1G|SOT−563|4,000/Tape & Reel| |NSBC143EDP6T5G|SOT−963|8,000/Tape & Reel| - †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: **55** © Semiconductor Components Industries, LLC, 2012 **June, 2017 − Rev. 1** **DTC143ED/D** ## **MUN5232DW1, NSBC143EDXV6, NSBC143EDP6** ## **THERMAL CHARACTERISTICS** |**THERMAL CHARACTERISTICS**|||| |---|---|---|---| |**Characteristic**|**Symbol**|**Max**|**Unit**| |**MUN5232DW1 (SOT−363) ONE JUNCTION HEATED**|||| |Total Device Dissipation
TA= 25°C
(Note 37)
(Note 38)
Derate above 25°C
(Note 37)
(Note 38)|PD|187
256
1.5
2.0|mW
mW/°C| |Thermal Resistance,
(Note 37)
Junction to Ambient
(Note 38)|R�JA|670
490|°C/W| |**MUN5232DW1 (SOT−363) BOTH JUNCTION HEATED**(Note 39)|||| |Total Device Dissipation
TA= 25°C
(Note 37)
(Note 38)
Derate above 25°C
(Note 37)
(Note 38)|PD|250
385
2.0
3.0|mW
mW/°C| |Thermal Resistance,
Junction to Ambient
(Note 37)
(Note 38)|R�JA|493
325|°C/W| |Thermal Resistance,
Junction to Lead (Note 37)
(Note 38)|R�JL|188
208|°C/W| |Junction and Storage Temperature Range|TJ, Tstg|−55 to +150|°C| |**NSBC143EDXV6 (SOT−563) ONE JUNCTION HEATED**|||| |Total Device Dissipation
TA= 25°C
(Note 37)
Derate above 25°C
(Note 37)|PD|357
2.9|mW
mW/°C| |Thermal Resistance,
Junction to Ambient
(Note 37)|R�JA|350|°C/W| |**NSBC143EDXV6 (SOT−563) BOTH JUNCTION HEATED**(Note 39)|||| |Total Device Dissipation
TA= 25°C
(Note 37)
Derate above 25°C
(Note 37)|PD|500
4.0|mW
mW/°C| |Thermal Resistance,
Junction to Ambient
(Note 37)|R�JA|250|°C/W| |Junction and Storage Temperature Range|TJ, Tstg|−55 to +150|°C| |**NSBC143EDP6 (SOT−963) ONE JUNCTION HEATED**|||| |Total Device Dissipation
TA= 25°C
(Note 40)
(Note 41)
Derate above 25°C
(Note 40)
(Note 41)|PD|231
269
1.9
2.2|MW
mW/°C| |Thermal Resistance,
Junction to Ambient
(Note 40)
(Note 41)|R�JA|540
464|°C/W| |**NSBC143EDP6 (SOT−963) BOTH JUNCTION HEATED**(Note 39)|||| |Total Device Dissipation
TA= 25°C
(Note 40)
(Note 41)
Derate above 25°C
(Note 40)
(Note 41)|PD|339
408
2.7
3.3|MW
mW/°C| |Thermal Resistance,
Junction to Ambient
(Note 40)
(Note 41)|R�JA|369
306|°C/W| |Junction and Storage Temperature Range|TJ, Tstg|−55 to +150|°C| 37.FR−4 @ Minimum Pad. 38.FR−4 @ 1.0 × 1.0 Inch Pad. 39.Both junction heated values assume total power is sum of two equally powered channels. 40.FR−4 @ 100 mm[2] , 1 oz. copper traces, still air. 41.FR−4 @ 500 mm[2] , 1 oz. copper traces, still air. **www.onsemi.com** **56** ## **MUN5232DW1, NSBC143EDXV6, NSBC143EDP6** ## **ELECTRICAL CHARACTERISTICS** (TA = 25 ° C, common for Q1 and Q2, unless otherwise noted) |**Characteristic**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---| |**OFF CHARACTERISTICS**|||||| |Collector-Base Cutoff Current
(VCB= 50 V, IE= 0)|ICBO|−|−|100|nAdc| |Collector-Emitter Cutoff Current
(VCE= 50 V, IB= 0)|ICEO|−|−|500|nAdc| |Emitter-Base Cutoff Current
(VEB= 6.0 V, IC= 0)|IEBO|−|−|1.5|mAdc| |Collector-Base Breakdown Voltage
(IC= 10�A, IE= 0)|V(BR)CBO|50|−|−|Vdc| |Collector-Emitter Breakdown Voltage (Note 42)
(IC= 2.0 mA, IB= 0)|V(BR)CEO|50|−|−|Vdc| |**ON CHARACTERISTICS**|||||| |DC Current Gain (Note 42)
(IC= 5.0 mA, VCE= 10 V)|hFE|15|30|−|| |Collector-Emitter Saturation Voltage (Note 42)
(IC= 10 mA, IB= 1.0 mA)|VCE(sat)|−|−|0.25|V| |Input Voltage (Off)
(VCE= 5.0 V, IC= 100�A)|Vi(off)|−|1.2|−|Vdc| |Input Voltage (On)
(VCE= 0.2 V, IC= 20 mA)|Vi(on)|−|2.4|−|Vdc| |Output Voltage (On)
(VCC= 5.0 V, VB= 2.5 V, RL= 1.0 k�)|VOL|−|−|0.2|Vdc| |Output Voltage (Off)
(VCC= 5.0 V, VB= 0.25 V, RL= 1.0 k�)|VOH|4.9|−|−|Vdc| |Input Resistor|R1|3.3|4.7|6.1|k�| |Resistor Ratio|R1/R2|0.8|1.0|1.2|| 42.Pulsed Condition: Pulse Width = 300 ms, Duty Cycle ≤ 2%. **==> picture [415 x 173] intentionally omitted <==** **----- Start of picture text -----**
400
350
300
250
(1) SOT−363; 1.0 × 1.0 Inch Pad
200
(2) SOT−563; Minimum Pad
(1) (2) (3)
150 (3) SOT−963; 100 mm [2] , 1 oz. Copper Trace
100
50
0
−50 −25 0 25 50 75 100 125 150
AMBIENT TEMPERATURE ( ° C)
, POWER DISSIPATION (mW)
D
P
**----- End of picture text -----**
**Figure 98. Derating Curve** **www.onsemi.com** **57** **MUN5232DW1, NSBC143EDXV6, NSBC143EDP6** ## **TYPICAL CHARACTERISTICS MUN5232DW1, NSBC143EDXV6** **==> picture [489 x 388] intentionally omitted <==** **----- Start of picture text -----**
1 1000
IC/IB = 10 VCE = 10 VCE = 10 V = 10 V 25 ° C 150 ° C
100
−55 ° C
0.1 10
150 ° C
25 ° C
1
−55 ° C
0.01 0.1
0 10 20 30 40 50 0.1 1 10 100
IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA)C, COLLECTOR CURRENT (mA), COLLECTOR CURRENT (mA)
Figure 99. VCE(sat), vs. IC Figure 100. DC Current Gain
3.6 100
f = 10 kHz 150 ° C 25 ° C −55 ° C
3.2 I E = 0 A
2.8 TA = 25 ° C
10
2.4
2.0
1
1.6
1.2
0.1
0.8
0.4 VO = 5 V
0 0.01
0 10 20 30 40 50 0 1 2 3 4 5
VR, REVERSE VOLTAGE (V) Vin, INPUT VOLTAGE (V)
, DC CURRENT GAIN
FE
h
, COLLECTOR−EMITTER VOLTAGE (V)
CE(sat)
V
, OUTPUT CAPACITANCE (pF) , COLLECTOR CURRENT (mA)
Cob IC
**----- End of picture text -----**
**==> picture [240 x 172] intentionally omitted <==** **----- Start of picture text -----**
1000
VCE = 10 VCE = 10 V = 10 V 25 ° C 150 ° C
100
−55 ° C
10
1
0.1
0.1 1 10 100
IC, COLLECTOR CURRENT (mA)C, COLLECTOR CURRENT (mA), COLLECTOR CURRENT (mA)
, DC CURRENT GAIN
FE
h
**----- End of picture text -----**
**Figure 101. Output Capacitance** **Figure 102. Output Current vs. Input Voltage** **==> picture [241 x 173] intentionally omitted <==** **----- Start of picture text -----**
100
10 25 ° C
−55 ° C
1
150 ° C
VO = 0.2 V
0.1
0 10 20 30 40 50
IC, COLLECTOR CURRENT (mA)
, INPUT VOLTAGE (V)
in
V
**----- End of picture text -----**
**Figure 103. Input Voltage vs. Output Current** **www.onsemi.com** **58** **MUN5232DW1, NSBC143EDXV6, NSBC143EDP6** ## **TYPICAL CHARACTERISTICS NSBC143EDP6** **==> picture [490 x 389] intentionally omitted <==** **----- Start of picture text -----**
1 1000
IC/IB = 10 VCE = 10 V 25 ° C 150 ° C
100
−55 ° C
25 ° C
0.1 150 ° C 10
−55 ° C 1
0.01 0.1
0 10 20 30 40 50 0.1 1 10 100
IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA)
Figure 104. VCE(sat), vs. IC Figure 105. DC Current Gain
2.4 100
150 ° C 25 ° C
f = 10 kHz −55 ° C
2.0 IE = 0 A
TA = 25 ° C 10
1.6
1.2 1
0.8
0.1
0.4 VO = 5 V
0 0.01
0 10 20 30 40 50 0 1 2 3 4
VR, REVERSE VOLTAGE (V) Vin, INPUT VOLTAGE (V)
, DC CURRENT GAIN
FE
h
, COLLECTOR−EMITTER VOLTAGE (V)
CE(sat)
V
, OUTPUT CAPACITANCE (pF) , COLLECTOR CURRENT (mA)
Cob IC
**----- End of picture text -----**
**Figure 106. Output Capacitance** **Figure 107. Output Current vs. Input Voltage** **==> picture [241 x 172] intentionally omitted <==** **----- Start of picture text -----**
10
25 ° C
−55 ° C
1 150 ° C
VO = 0.2 V
0.1
0 10 20 30 40 50
IC, COLLECTOR CURRENT (mA)
, INPUT VOLTAGE (V)
in
V
**----- End of picture text -----**
**Figure 108. Input Voltage vs. Output Current** **www.onsemi.com** **59** MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** **SC−88/SC70−6/SOT−363** CASE 419B−02 ISSUE Y **==> picture [479 x 420] intentionally omitted <==** **----- Start of picture text -----**
1
SCALE 2:1 2X DATE 11 DEC 2012
aaa H D
- D H NOTES:1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
A 3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
D GAGE PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
PLANE SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
6 5 4 THE PLASTIC BODY AND DATUM H.
L2 L 5. DATUMS A AND B ARE DETERMINED AT DATUM H.
E E1 DETAIL A 6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THELEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
1 2 3
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-
2X aaa C TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
bbb H D 2X 3 TIPS RADIUS OF THE FOOT.
e MILLIMETERS INCHES
DIM MIN NOM MAX MIN NOM MAX
B l= 6X b : A −−− −−− 1.10 −−− −−− 0.043
ddd M C A-B D A1 0.00 −−− 0.10 0.000 −−− 0.004
TOP VIEW A2 0.70 0.90 1.00 0.027 0.035 0.039
b 0.15 0.20 0.25 0.006 0.008 0.010
C 0.08 0.15 0.22 0.003 0.006 0.009
A2 DETAIL A D 1.80 2.00 2.20 0.070 0.078 0.086
A E 2.00 2.10 2.20 0.078 0.082 0.086
E1 1.15 1.25 1.35 0.045 0.049 0.053
e 0.65 BSC 0.026 BSC
L 0.26 0.36 0.46 0.010 0.014 0.018
L2 0.15 BSC 0.006 BSC
aaa 0.15 0.006
bbb 0.30 0.012
6X ccc C ccc 0.10 0.004
(tll, A1 C A SEATINGPLANE Ma c === ddd 0.10 0.004
SIDE VIEW END VIEW GENERIC
MARKING DIAGRAM*
RECOMMENDED 6
SOLDERING FOOTPRINT*
6X 6X XXXM
0.30 0.66
1
Ta os 2.50 XXX = Specific Device Code
M = Date Code*
= Pb−Free Package
0.65 yo (Note: Microdot may be in either location)
PITCH
**----- End of picture text -----**
## DATE 11 DEC 2012 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. - *Date Code orientation and/or position may vary depending upon manufacturing location. **==> picture [83 x 5] intentionally omitted <==** **----- Start of picture text -----**
DIMENSIONS: MILLIMETERS
**----- End of picture text -----**
- *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. - *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ ”, may or may not be present. ## **STYLES ON PAGE 2** **DOCUMENT NUMBER: 98ASB42985B** **DESCRIPTION: SC−88/SC70−6/SOT−363** Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **PAGE 1 OF 2** ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. www.onsemi.com © Semiconductor Components Industries, LLC, 2019 ## **SC−88/SC70−6/SOT−363** CASE 419B−02 ISSUE Y ## DATE 11 DEC 2012 **==> picture [452 x 271] intentionally omitted <==** **----- Start of picture text -----**
STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5: STYLE 6:
PIN 1. EMITTER 2 CANCELLED CANCELLED PIN 1. CATHODE PIN 1. ANODE PIN 1. ANODE 2
2. BASE 2 2. CATHODE 2. ANODE 2. N/C
3. COLLECTOR 1 3. COLLECTOR 3. COLLECTOR 3. CATHODE 1
4. EMITTER 1 4. EMITTER 4. EMITTER 4. ANODE 1
5. BASE 1 5. BASE 5. BASE 5. N/C
6. COLLECTOR 2 6. ANODE 6. CATHODE 6. CATHODE 2
STYLE 7: STYLE 8: STYLE 9: STYLE 10: STYLE 11: STYLE 12:
PIN 1. SOURCE 2 CANCELLED PIN 1. EMITTER 2 PIN 1. SOURCE 2 PIN 1. CATHODE 2 PIN 1. ANODE 2
2. DRAIN 2 2. EMITTER 1 2. SOURCE 1 2. CATHODE 2 2. ANODE 2
3. GATE 1 3. COLLECTOR 1 3. GATE 1 3. ANODE 1 3. CATHODE 1
4. SOURCE 1 4. BASE 1 4. DRAIN 1 4. CATHODE 1 4. ANODE 1
5. DRAIN 1 5. BASE 2 5. DRAIN 2 5. CATHODE 1 5. ANODE 1
6. GATE 2 6. COLLECTOR 2 6. GATE 2 6. ANODE 2 6. CATHODE 2
STYLE 13: STYLE 14: STYLE 15: STYLE 16: STYLE 17: STYLE 18:
PIN 1. ANODE PIN 1. VREF PIN 1. ANODE 1 PIN 1. BASE 1 PIN 1. BASE 1 PIN 1. VIN1
2. N/C 2. GND 2. ANODE 2 2. EMITTER 2 2. EMITTER 1 2. VCC
3. COLLECTOR 3. GND 3. ANODE 3 3. COLLECTOR 2 3. COLLECTOR 2 3. VOUT2
4. EMITTER 4. IOUT 4. CATHODE 3 4. BASE 2 4. BASE 2 4. VIN2
5. BASE 5. VEN 5. CATHODE 2 5. EMITTER 1 5. EMITTER 2 5. GND
6. CATHODE 6. VCC 6. CATHODE 1 6. COLLECTOR 1 6. COLLECTOR 1 6. VOUT1
STYLE 19: STYLE 20: STYLE 21: STYLE 22: STYLE 23: STYLE 24:
PIN 1. I OUT PIN 1. COLLECTOR PIN 1. ANODE 1 PIN 1. D1 (i) PIN 1. Vn PIN 1. CATHODE
2. GND 2. COLLECTOR 2. N/C 2. GND 2. CH1 2. ANODE
3. GND 3. BASE 3. ANODE 2 3. D2 (i) 3. Vp 3. CATHODE
4. V CC 4. EMITTER 4. CATHODE 2 4. D2 (c) 4. N/C 4. CATHODE
5. V EN 5. COLLECTOR 5. N/C 5. VBUS 5. CH2 5. CATHODE
6. V REF 6. COLLECTOR 6. CATHODE 1 6. D1 (c) 6. N/C 6. CATHODE
STYLE 25: STYLE 26: STYLE 27: STYLE 28: STYLE 29: STYLE 30:
PIN 1. BASE 1 PIN 1. SOURCE 1 PIN 1. BASE 2 PIN 1. DRAIN PIN 1. ANODE PIN 1. SOURCE 1
2. CATHODE 2. GATE 1 2. BASE 1 2. DRAIN 2. ANODE 2. DRAIN 2
3. COLLECTOR 2 3. DRAIN 2 3. COLLECTOR 1 3. GATE 3. COLLECTOR 3. DRAIN 2
4. BASE 2 4. SOURCE 2 4. EMITTER 1 4. SOURCE 4. EMITTER 4. SOURCE 2
5. EMITTER 5. GATE 2 5. EMITTER 2 5. DRAIN 5. BASE/ANODE 5. GATE 1
6. COLLECTOR 1 6. DRAIN 1 6. COLLECTOR 2 6. DRAIN 6. CATHODE 6. DRAIN 1
**----- End of picture text -----**
|**DOCUMENT NUMBER:**|**98ASB42985B**|Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.|Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.| |---|---|---|---| |**DESCRIPTION:**|**SC−88/SC70−6/SOT−363**||**PAGE 2 OF 2**| ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. www.onsemi.com © Semiconductor Components Industries, LLC, 2019 MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** **==> picture [456 x 552] intentionally omitted <==** **----- Start of picture text -----**
SOT−563, 6 LEAD
6 CASE 463A
& ISSUE G
1
SCALE 4:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
D 2. CONTROLLING DIMENSION: MILLIMETERS
−X− A 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
L FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE MATERIAL.
6 5 4 MILLIMETERS INCHES
o −Y−E HE t DIMA 0.50 MIN NOM 0.55 MAX 0.60 0.020 MIN 0.021 NOM 0.023 MAX
1 2 3 b 0.17 0.22 0.27 0.007 0.009 0.011
C 0.08 0.12 0.18 0.003 0.005 0.007
LJe [ - D 1.50 1.60 e 1.70 0.059 e 0.062 0.066
b 5 PL6 C E 1.10 1.20 1.30 0.043 0.047 0.051
e 0.08 (0.003) M X Y Le 0.10 0.5 BSC0.20 0.30 0.004 0.02 BSC0.008 0.012
HE 1.50 1.60 1.70 0.059 0.062 0.066
GENERIC
STYLE 1: STYLE 2: STYLE 3:
PIN 1. EMITTER 1 PIN 1. EMITTER 1 PIN 1. CATHODE 1 MARKING DIAGRAM*
2. BASE 1 2. EMITTER2 2. CATHODE 1
3. COLLECTOR 2 3. BASE 2 3. ANODE/ANODE 2
4. EMITTER 2 4. COLLECTOR 2 4. CATHODE 2
5. BASE 2 5. BASE 1 5. CATHODE 2
6. COLLECTOR 1 6. COLLECTOR 1 6. ANODE/ANODE 1 XX M
STYLE 4: STYLE 5: STYLE 6: 1
PIN 1. COLLECTOR PIN 1. CATHODE PIN 1. CATHODE
2. 3. BASECOLLECTOR 2. 3. ANODECATHODE 2. 3. ANODECATHODE XX = Specific Device Code
4. EMITTER 4. ANODE 4. CATHODE M = Month Code
5. 6. COLLECTORCOLLECTOR 5. 6. CATHODECATHODE 5. 6. CATHODECATHODE = Pb−Free Package
STYLE 7: STYLE 8: STYLE 9:
PIN 1. CATHODE PIN 1. DRAIN PIN 1. SOURCE 1 *This information is generic. Please refer to
2. ANODE 2. DRAIN 2. GATE 1 device data sheet for actual part marking.
3. 4. CATHODECATHODE 3. 4. GATESOURCE 3. 4. SOURCE 2DRAIN 2 Pb−Free indicator, “G” or microdot “ ”,
5. ANODE 5. DRAIN 5. GATE 2 may or may not be present.
6. CATHODE 6. DRAIN 6. DRAIN 1
STYLE 10:
PIN 1. CATHODE 1 SOLDERING FOOTPRINT*
2. N/C
3. CATHODE 2 0.3
4. ANODE 2
5. N/C 0.0118
6. ANODE 1 i ry
0.45
0.0177
1.0
1.35 ree 0.0394
0.0531
load
0.5 0.5
0.0197 0.0197
SCALE 20:1 mm
inches
— — — (—})
**----- End of picture text -----**
DATE 23 SEP 2015 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON11126D** Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **DESCRIPTION: SOT−563, 6 LEAD PAGE 1 OF 1** ~~————_——————~~ ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. www.onsemi.com © Semiconductor Components Industries, LLC, 2019 MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** **SOT−963** CASE 527AD−01 ISSUE E ## DATE 09 FEB 2010 **SCALE 4:1** NOTES: **==> picture [407 x 204] intentionally omitted <==** **----- Start of picture text -----**
D X A 1.
Y Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3.
6 5 4 FINISH THICKNESS. MINIMUM LEAD
E HE BASE MATERIAL.
4.
1 2 3 FLASH, PROTRUSIONS, OR GATE BURRS.
a||4 MILLIMETERS
DIM MIN NOM MAX
TOP VIEW C —> | A 0.34 0.37 0.40
SIDE VIEW b 0.10 0.15 0.20
C 0.07 0.12 0.17
D 0.95 1.00 1.05
e 6X L E 0.75 0.80 0.85
e 0.35 BSC
H E 0.95 1.00 1.05
L 0.19 REF
L2 0.05 0.10 0.15
GENERIC
Et MARKING DIAGRAM*
6X L2 6X b
0.08 X Y
t BOTTOM VIEW o ec o XM
**----- End of picture text -----**
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS |2.|Y14.5M, 1994.
CONTROLLING DIMENSION: MILLIMETERS|Y14.5M, 1994.
CONTROLLING DIMENSION: MILLIMETERS| |---|---|---| |3.
4.
~~|4~~
~~a||44~~|**DIM**
**MIN**
**NOM**
**MAX**
**MILLIMETERS**
MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
~~|4~~
~~a||44~~|| ||**A**
0.34
0.37
0.40|| ||**b**
0.10
0.15
0.20|| ||**C**
0.07
0.12
0.17|| ||**D**
0.95
1.00
1.05|| ||**E**
0.75
0.80
0.85|| ||**e**
0.35 BSC
0.95
1.00
1.05
**HE**
**L**
0.19 REF
**L2**
0.05
0.10
0.15|| - XM - 1 - X = Specific Device Code M = Month Code - STYLE 1: STYLE 2: STYLE 3: PIN 1. EMITTER 1 PIN 1. EMITTER 1 PIN 1. CATHODE 1 2. BASE 1 2. EMITTER2 2. CATHODE 1 3. COLLECTOR 2 3. BASE 2 3. ANODE/ANODE 2 4. EMITTER 2 4. COLLECTOR 2 4. CATHODE 2 5. BASE 2 5. BASE 1 5. CATHODE 2 6. COLLECTOR 1 6. COLLECTOR 1 6. ANODE/ANODE 1 - STYLE 4: STYLE 5: STYLE 6: PIN 1. COLLECTOR PIN 1. CATHODE PIN 1. CATHODE 2. COLLECTOR 2. CATHODE 2. ANODE 3. BASE 3. ANODE 3. CATHODE 4. EMITTER 4. ANODE 4. CATHODE 5. COLLECTOR 5. CATHODE 5. CATHODE 6. COLLECTOR 6. CATHODE 6. CATHODE - STYLE 7: STYLE 8: STYLE 9: PIN 1. CATHODE PIN 1. DRAIN PIN 1. SOURCE 1 2. ANODE 2. DRAIN 2. GATE 1 3. CATHODE 3. GATE 3. DRAIN 2 4. CATHODE 4. SOURCE 4. SOURCE 2 5. ANODE 5. DRAIN 5. GATE 2 6. CATHODE 6. DRAIN 6. DRAIN 1 - *This information is generic. Please refer to device data sheet for actual part marking. - Pb−Free indicator, “G” or microdot “ ”, may or may not be present. **==> picture [124 x 123] intentionally omitted <==** **----- Start of picture text -----**
RECOMMENDED
MOUNTING FOOTPRINT
6X 6X
0.20 “ ie 0.35
PACKAGE
OUTLINE
Oo 1.20
0.35 oe
PITCH
DIMENSIONS: MILLIMETERS
**----- End of picture text -----**
STYLE 10: PIN 1. CATHODE 1 2. N/C 3. CATHODE 2 4. ANODE 2 5. N/C 6. ANODE 1 **DOCUMENT NUMBER: 98AON26456D DESCRIPTION: SOT−963, 1X1, 0.35P** Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **PAGE 1 OF 1** ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. www.onsemi.com © Semiconductor Components Industries, LLC, 2019 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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