# Bipolar Pre-Biased / Digital Transistor, Dual NPN, 50 V, 100 mA, 10 kohm, 47 kohm ![Product image](https://novapart.co/image/farnell:2724482/) **URL**: https://novapart.co/products/SMUN5214DW1T1G/bipolar-pre-biased-digital-transistor-dual-npn-50 **SKU**: SMUN5214DW1T1G **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || Transistors || Bipolar Transistors || Pre-Biased / Digital Bipolar Transistors **Price**: €0.0620 **Stock**: 1000+ **Lead Time**: 141 days (indicative) ## Description Digital Transistor Polarity:Dual NPN; Collector Emitter Voltage V(br)ceo:50V; Continuous Collector Current Ic:100mA; Base Input Resistor R1:10kohm; Base-Emitter Resistor R2:47kohm ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | No SVHC (25-Jun-2025) | | No. Of Pins | 6 Pin | | Product Range | - | | Qualification | AEC-Q101 | | Power Dissipation | 385mW | | Transistor Mounting | Surface Mount | | Transistor Polarity | Dual NPN | | Transistor Case Style | SOT-363 | | Base Input Resistor R1 | 10kohm | | Dc Current Gain Hfe Min | 80hFE | | Base Emitter Resistor R2 | 47kohm | | Operating Temperature Max | 150°C | | Continuous Collector Current | 100mA | | Collector Emitter Voltage Max Npn | 50V | | Collector Emitter Voltage Max Pnp | - | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2724482/) ## Dual NPN Bias Resistor Transistors R1 = 10 k R2 = 47 k **NPN Transistors with Monolithic Bias Resistor Network** ## MUN5214DW1, NSBC114YDXV6, NSBC114YDP6 **www.onsemi.com PIN CONNECTIONS** **==> picture [144 x 119] intentionally omitted <==** **----- Start of picture text -----**
(3) (2) (1)
R1 R2
Q1
Q2
R2 R1
(4) (5) (6)
**----- End of picture text -----**
This series of digital transistors is designed to replace a single device and its external resistor bias network. The Bias Resistor Transistor (BRT) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base-emitter resistor. The BRT eliminates these individual components by integrating them into a single device. The use of a BRT can reduce both system cost and board space. ## **Features** - Simplifies Circuit Design - Reduces Board Space - Reduces Component Count ## **MARKING DIAGRAMS** - S and NSV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q101 Qualified and PPAP Capable* 6 7D M 1 **==> picture [104 x 144] intentionally omitted <==** **----- Start of picture text -----**
SOT−363
CASE 419B
1
SOT−563
7D M
CASE 463A
1
SOT−963
PM
CASE 527AD
1
**----- End of picture text -----**
- These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant ## **MAXIMUM RATINGS** (TA = 25 ° C, common for Q1 and Q2, unless otherwise noted) **Rating Symbol Max Unit** Collector-Base Voltage VCBO 50 Vdc Collector-Emitter Voltage VCEO 50 Vdc Collector Current − Continuous IC 100 mAdc Input Forward Voltage VIN(fwd) 40 Vdc ~~===~~ Input Reverse Voltage VIN(rev) 6 Vdc & Stresses exceeding those listed in the Maximum Ratings table may damage the ¢ device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. **==> picture [147 x 42] intentionally omitted <==** **----- Start of picture text -----**
7D/P = Specific Device Code
M = Date Code*
= Pb-Free Package
(Note: Microdot may be in either location)
**----- End of picture text -----**
## **ORDERING INFORMATION** |**ORDERING INFORMATION**||| |---|---|---| |**Device**|**Package**|**Shipping**†| |MUN5214DW1T1G,
SMUN5214DW1T1G*,
NSVMUN5214DW1T2G*|SOT−363|3,000 / Tape & Reel| |NSVMUN5214DW1T3G*|SOT−363|10,000 / Tape & Reel| |NSBC114YDXV6T1G
NSVBC114YDXV6T1G*|SOT−563|4,000 / Tape & Reel| |NSBC114YDXV6T5G|SOT−563|8,000 / Tape & Reel| |NSBC114YDP6T5G|SOT−963|8,000 / Tape & Reel| - *Date Code orientation may vary depending upon manufacturing location. - †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: **DTC114YD/D** **1** © Semiconductor Components Industries, LLC, 2014 **July, 2021 − Rev. 5** ## **MUN5214DW1, NSBC114YDXV6, NSBC114YDP6** ## **THERMAL CHARACTERISTICS** |**THERMAL CHARACTERISTICS**|||| |---|---|---|---| |**Characteristic**|**Symbol**|**Max**|**Unit**| |**MUN5214DW1 (SOT−363) ONE JUNCTION HEATED**|||| |Total Device Dissipation
TA= 25°C
(Note 1)
(Note 2)
Derate above 25°C
(Note 1)
(Note 2)|PD|187
256
1.5
2.0|mW
mW/°C| |Thermal Resistance,
(Note 1)
Junction to Ambient
(Note 2)|R�JA|670
490|°C/W| |**MUN5214DW1 (SOT−363) BOTH JUNCTION HEATED**(Note 3)|||| |Total Device Dissipation
TA= 25°C
(Note 1)
(Note 2)
Derate above 25°C
(Note 1)
(Note 2)|PD|250
385
2.0
3.0|mW
mW/°C| |Thermal Resistance,
Junction to Ambient
(Note 1)
(Note 2)|R�JA|493
325|°C/W| |Thermal Resistance,
Junction to Lead (Note 1)
(Note 2)|R�JL|188
208|°C/W| |Junction and Storage Temperature Range|TJ, Tstg|−55 to +150|°C| |**NSBC114YDXV6 (SOT−563) ONE JUNCTION HEATED**|||| |Total Device Dissipation
TA= 25°C
(Note 1)
Derate above 25°C
(Note 1)|PD|357
2.9|mW
mW/°C| |Thermal Resistance,
Junction to Ambient
(Note 1)|R�JA|350|°C/W| |**NSBC114YDXV6 (SOT−563) BOTH JUNCTION HEATED**(Note 3)|||| |Total Device Dissipation
TA= 25°C
(Note 1)
Derate above 25°C
(Note 1)|PD|500
4.0|mW
mW/°C| |Thermal Resistance,
Junction to Ambient
(Note 1)|R�JA|250|°C/W| |Junction and Storage Temperature Range|TJ, Tstg|−55 to +150|°C| |**NSBC114YDP6 (SOT−963) ONE JUNCTION HEATED**|||| |Total Device Dissipation
TA= 25°C
(Note 4)
(Note 5)
Derate above 25°C
(Note 4)
(Note 5)|PD|231
269
1.9
2.2|MW
mW/°C| |Thermal Resistance,
Junction to Ambient
(Note 4)
(Note 5)|R�JA|540
464|°C/W| |**NSBC114YDP6 (SOT−963) BOTH JUNCTION HEATED**(Note 3)|||| |Total Device Dissipation
TA= 25°C
(Note 4)
(Note 5)
Derate above 25°C
(Note 4)
(Note 5)|PD|339
408
2.7
3.3|MW
mW/°C| |Thermal Resistance,
Junction to Ambient
(Note 4)
(Note 5)|R�JA|369
306|°C/W| |Junction and Storage Temperature Range|TJ, Tstg|−55 to +150|°C| 1. FR−4 @ Minimum Pad. 2. FR−4 @ 1.0 × 1.0 Inch Pad. 3. Both junction heated values assume total power is sum of two equally powered channels. 4. FR−4 @ 100 mm[2] , 1 oz. copper traces, still air. 5. FR−4 @ 500 mm[2] , 1 oz. copper traces, still air. **www.onsemi.com** **2** ## **MUN5214DW1, NSBC114YDXV6, NSBC114YDP6** ## **ELECTRICAL CHARACTERISTICS** (TA = 25 ° C, common for Q1 and Q2, unless otherwise noted) |**Characteristic**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---| |**OFF CHARACTERISTICS**|||||| |Collector-Base Cutoff Current
(VCB= 50 V, IE= 0)|ICBO|−|−|100|nAdc| |Collector-Emitter Cutoff Current
(VCE= 50 V, IB= 0)|ICEO|−|−|500|nAdc| |Emitter-Base Cutoff Current
(VEB= 6.0 V, IC= 0)|IEBO|−|−|0.2|mAdc| |Collector-Base Breakdown Voltage
(IC= 10�A, IE= 0)|V(BR)CBO|50|−|−|Vdc| |Collector-Emitter Breakdown Voltage (Note 6)
(IC= 2.0 mA, IB= 0)|V(BR)CEO|50|−|−|Vdc| |**ON CHARACTERISTICS**|||||| |DC Current Gain (Note 6)
(IC= 5.0 mA, VCE= 10 V)|hFE|80|140|−|| |Collector-Emitter Saturation Voltage (Note 6)
(IC= 10 mA, IB= 0.3 mA)|VCE(sat)|−|−|0.25|V| |Input Voltage (Off)
(VCE= 5.0 V, IC= 100�A)|Vi(off)|−|0.7|0.3|Vdc| |Input Voltage (On)
(VCE= 0.2 V, IC= 1.0 mA)|Vi(on)|1.4|0.8|−|Vdc| |Output Voltage (On)
(VCC= 5.0 V, VB= 2.5 V, RL= 1.0 k�)|VOL|−|−|0.2|Vdc| |Output Voltage (Off)
(VCC= 5.0 V, VB= 0.5 V, RL= 1.0 k�)|VOH|4.9|−|−|Vdc| |Input Resistor|R1|7|10|13|k�| |Resistor Ratio|R1/R2|0.17|0.21|0.25|| 6. Pulsed Condition: Pulse Width = 300 ms, Duty Cycle ≤ 2%. **==> picture [415 x 173] intentionally omitted <==** **----- Start of picture text -----**
400
350
300
250
(1) SOT−363; 1.0 × 1.0 Inch Pad
200
(2) SOT−563; Minimum Pad
(1) (2) (3)
150 (3) SOT−963; 100 mm [2] , 1 oz. Copper Trace
100
50
0
−50 −25 0 25 50 75 100 125 150
AMBIENT TEMPERATURE ( ° C)
, POWER DISSIPATION (mW)
D
P
**----- End of picture text -----**
**Figure 1. Derating Curve** **www.onsemi.com** **3** **MUN5214DW1, NSBC114YDXV6, NSBC114YDP6** ## **TYPICAL CHARACTERISTICS MUN5214DW1, NSBC114YDXV6** **==> picture [489 x 609] intentionally omitted <==** **----- Start of picture text -----**
1
1000
IC/IB = 10 VCE = 10 V 25 ° C 150 ° C
25 ° C 100
−55 ° C
0.1 150 ° C
10
−55 ° C
0.01 1
0 10 20 30 40 50 0.1 1 10 100
IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA)
Figure 2. VCE(sat) vs. IC Figure 3. DC Current Gain
3.6 100
3.2 f = 10 kHz
2.8 I T EA = 0 A = 25 ° C 10 −55 ° C
2.4
2 1 25 ° C
1.6
0.1 150 ° C
1.2
0.8
0.01
0.4
VO = 5 V
0
0.001
0 10 20 30 40 50 0 1 2 3 4 5 6 7 8 9 10
VR, REVERSE VOLTAGE (V) Vin, INPUT VOLTAGE (V)
Figure 4. Output Capacitance Figure 5. Output Current vs. Input Voltage
100
10 25 ° C −55 ° C
1
150 ° C
VO = 0.2 V
0.1
0 10 20 30 40 50
IC, COLLECTOR CURRENT (mA)
, DC CURRENT GAIN
FE
h
, COLLECTOR−EMITTER VOLTAGE (V)
CE(sat)
V
, OUTPUT CAPACITANCE (pF)Cob , COLLECTOR CURRENT (mA)IC
, INPUT VOLTAGE (V)
in
V
**----- End of picture text -----**
**Figure 6. Input Voltage vs. Output Current** **www.onsemi.com** **4** **MUN5214DW1, NSBC114YDXV6, NSBC114YDP6** ## **TYPICAL CHARACTERISTICS NSBC114YDP6** **==> picture [488 x 390] intentionally omitted <==** **----- Start of picture text -----**
1
1000
IC/IB = 10 VCE = 10 V 25 ° C 150 ° C
25 ° C
100 −55 ° C
0.1 150 ° C
10
−55 ° C
0.01 1
0 10 20 30 40 50 0.1 1 10 100
IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA)
Figure 7. VCE(sat) vs. IC Figure 8. DC Current Gain
2.4 100
f = 10 kHz
2 ITEA = 0 A = 25 ° C 10 −55 ° C
1.6
1
1.2
0.1 25 ° C
0.8
0.4 0.01 150 ° C
VO = 5 V
0 0.001
0 10 20 30 40 50 0 1 2 3 4 5 6 7
VR, REVERSE VOLTAGE (V) Vin, INPUT VOLTAGE (V)
, DC CURRENT GAIN
FE
h
, COLLECTOR−EMITTER VOLTAGE (V)
CE(sat)
V
, OUTPUT CAPACITANCE (pF)Cob , COLLECTOR CURRENT (mA)IC
**----- End of picture text -----**
**Figure 9. Output Capacitance** **Figure 10. Output Current vs. Input Voltage** **==> picture [235 x 171] intentionally omitted <==** **----- Start of picture text -----**
100
10 25 ° C −55 ° C
1
150 ° C
VO = 0.2 V
0.1
0 10 20 30 40 50
IC, COLLECTOR CURRENT (mA)
, INPUT VOLTAGE (V)
in
V
**----- End of picture text -----**
**Figure 11. Input Voltage vs. Output Current** **www.onsemi.com** **5** MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** **SC−88/SC70−6/SOT−363** CASE 419B−02 ISSUE Y **==> picture [479 x 420] intentionally omitted <==** **----- Start of picture text -----**
1
SCALE 2:1 2X DATE 11 DEC 2012
aaa H D
- D H NOTES:1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
A 3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
D GAGE PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
PLANE SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
6 5 4 THE PLASTIC BODY AND DATUM H.
L2 L 5. DATUMS A AND B ARE DETERMINED AT DATUM H.
E E1 DETAIL A 6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THELEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
1 2 3
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-
2X aaa C TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
bbb H D 2X 3 TIPS RADIUS OF THE FOOT.
e MILLIMETERS INCHES
DIM MIN NOM MAX MIN NOM MAX
B l= 6X b : A −−− −−− 1.10 −−− −−− 0.043
ddd M C A-B D A1 0.00 −−− 0.10 0.000 −−− 0.004
TOP VIEW A2 0.70 0.90 1.00 0.027 0.035 0.039
b 0.15 0.20 0.25 0.006 0.008 0.010
C 0.08 0.15 0.22 0.003 0.006 0.009
A2 DETAIL A D 1.80 2.00 2.20 0.070 0.078 0.086
A E 2.00 2.10 2.20 0.078 0.082 0.086
E1 1.15 1.25 1.35 0.045 0.049 0.053
e 0.65 BSC 0.026 BSC
L 0.26 0.36 0.46 0.010 0.014 0.018
L2 0.15 BSC 0.006 BSC
aaa 0.15 0.006
bbb 0.30 0.012
6X ccc C ccc 0.10 0.004
(tll, A1 C A SEATINGPLANE Ma c === ddd 0.10 0.004
SIDE VIEW END VIEW GENERIC
MARKING DIAGRAM*
RECOMMENDED 6
SOLDERING FOOTPRINT*
6X 6X XXXM
0.30 0.66
1
Ta os 2.50 XXX = Specific Device Code
M = Date Code*
= Pb−Free Package
0.65 yo (Note: Microdot may be in either location)
PITCH
**----- End of picture text -----**
## DATE 11 DEC 2012 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. - *Date Code orientation and/or position may vary depending upon manufacturing location. **==> picture [83 x 5] intentionally omitted <==** **----- Start of picture text -----**
DIMENSIONS: MILLIMETERS
**----- End of picture text -----**
- *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. - *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ ”, may or may not be present. Some products may not follow the Generic Marking. ## **STYLES ON PAGE 2** **DOCUMENT NUMBER: 98ASB42985B** **DESCRIPTION: SC−88/SC70−6/SOT−363** Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **PAGE 1 OF 2** ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. www.onsemi.com © Semiconductor Components Industries, LLC, 2019 ## **SC−88/SC70−6/SOT−363** CASE 419B−02 ISSUE Y ## DATE 11 DEC 2012 |STYLE 1:|STYLE 2:|STYLE 3:|STYLE 4:|STYLE 5:|STYLE 6:| |---|---|---|---|---|---| |PIN 1. EMITTER 2|CANCELLED|CANCELLED|PIN 1. CATHODE|PIN 1. ANODE|PIN 1. ANODE 2| |2. BASE 2|||2. CATHODE|2. ANODE|2. N/C| |3. COLLECTOR 1|||3. COLLECTOR|3. COLLECTOR|3. CATHODE 1| |4. EMITTER 1|||4. EMITTER|4. EMITTER|4. ANODE 1| |5. BASE 1|||5. BASE|5. BASE|5. N/C| |6. COLLECTOR 2|||6. ANODE|6. CATHODE|6. CATHODE 2| |STYLE 7:|STYLE 8:|STYLE 9:|STYLE 10:|STYLE 11:|STYLE 12:| |PIN 1. SOURCE 2|CANCELLED|PIN 1. EMITTER 2|PIN 1. SOURCE 2|PIN 1. CATHODE 2|PIN 1. ANODE 2| |2. DRAIN 2||2. EMITTER 1|2. SOURCE 1|2. CATHODE 2|2. ANODE 2| |3. GATE 1||3. COLLECTOR 1|3. GATE 1|3. ANODE 1|3. CATHODE 1| |4. SOURCE 1||4. BASE 1|4. DRAIN 1|4. CATHODE 1|4. ANODE 1| |5. DRAIN 1||5. BASE 2|5. DRAIN 2|5. CATHODE 1|5. ANODE 1| |6. GATE 2||6. COLLECTOR 2|6. GATE 2|6. ANODE 2|6. CATHODE 2| |STYLE 13:|STYLE 14:|STYLE 15:|STYLE 16:|STYLE 17:|STYLE 18:| |PIN 1. ANODE|PIN 1. VREF|PIN 1. ANODE 1|PIN 1. BASE 1|PIN 1. BASE 1|PIN 1. VIN1| |2. N/C|2. GND|2. ANODE 2|2. EMITTER 2|2. EMITTER 1|2. VCC| |3. COLLECTOR|3. GND|3. ANODE 3|3. COLLECTOR 2|3. COLLECTOR 2|3. VOUT2| |4. EMITTER|4. IOUT|4. CATHODE 3|4. BASE 2|4. BASE 2|4. VIN2| |5. BASE|5. VEN|5. CATHODE 2|5. EMITTER 1|5. EMITTER 2|5. GND| |6. CATHODE|6. VCC|6. CATHODE 1|6. COLLECTOR 1|6. COLLECTOR 1|6. VOUT1| |STYLE 19:|STYLE 20:|STYLE 21:|STYLE 22:|STYLE 23:|STYLE 24:| |PIN 1. I OUT|PIN 1. COLLECTOR|PIN 1. ANODE 1|PIN 1. D1 (i)|PIN 1. Vn|PIN 1. CATHODE| |2. GND|2. COLLECTOR|2. N/C|2. GND|2. CH1|2. ANODE| |3. GND|3. BASE|3. ANODE 2|3. D2 (i)|3. Vp|3. CATHODE| |4. V CC|4. EMITTER|4. CATHODE 2|4. D2 (c)|4. N/C|4. CATHODE| |5. V EN|5. COLLECTOR|5. N/C|5. VBUS|5. CH2|5. CATHODE| |6. V REF|6. COLLECTOR|6. CATHODE 1|6. D1 (c)|6. N/C|6. CATHODE| |STYLE 25:|STYLE 26:|STYLE 27:|STYLE 28:|STYLE 29:|STYLE 30:| |PIN 1. BASE 1|PIN 1. SOURCE 1|PIN 1. BASE 2|PIN 1. DRAIN|PIN 1. ANODE|PIN 1. SOURCE 1| |2. CATHODE|2. GATE 1|2. BASE 1|2. DRAIN|2. ANODE|2. DRAIN 2| |3. COLLECTOR 2|3. DRAIN 2|3. COLLECTOR 1|3. GATE|3. COLLECTOR|3. DRAIN 2| |4. BASE 2|4. SOURCE 2|4. EMITTER 1|4. SOURCE|4. EMITTER|4. SOURCE 2| |5. EMITTER|5. GATE 2|5. EMITTER 2|5. DRAIN|5. BASE/ANODE|5. GATE 1| |6. COLLECTOR 1|6. DRAIN 1|6. COLLECTOR 2|6. DRAIN|6. CATHODE|6. DRAIN 1| Note: Please refer to datasheet for style callout. If style type is not called out in the datasheet refer to the device datasheet pinout or pin assignment. |**DOCUMENT NUMBER:**|**98ASB42985B**|Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.|Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.| |---|---|---|---| |**DESCRIPTION:**|**SC−88/SC70−6/SOT−363**||**PAGE 2 OF 2**| ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. www.onsemi.com © Semiconductor Components Industries, LLC, 2019 MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** **==> picture [32 x 23] intentionally omitted <==** **----- Start of picture text -----**
6
1
**----- End of picture text -----**
## **SOT−563, 6 LEAD** CASE 463A ISSUE H ## DATE 26 JAN 2021 **==> picture [42 x 7] intentionally omitted <==** **----- Start of picture text -----**
SCALE 4:1
**----- End of picture text -----**
## **DOCUMENT NUMBER:** ## **98AON11126D** ## **DESCRIPTION: SOT−563, 6 LEAD** Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **PAGE 1 OF 2** ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. www.onsemi.com © Semiconductor Components Industries, LLC, 2019 ## **SOT−563, 6 LEAD** CASE 463A ISSUE H ## DATE 26 JAN 2021 ## **GENERIC MARKING DIAGRAM*** XX M 1 XX = Specific Device Code M = Month Code . = Pb−Free Package - *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ " ”, may or may not be present. Some products may not follow the Generic Marking. ## **DOCUMENT NUMBER:** **98AON11126D** **DESCRIPTION: SOT−563, 6 LEAD** Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **PAGE 2 OF 2** ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. www.onsemi.com © Semiconductor Components Industries, LLC, 2019 MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** **SOT−963** CASE 527AD−01 ISSUE E ## DATE 09 FEB 2010 **SCALE 4:1** NOTES: **==> picture [407 x 204] intentionally omitted <==** **----- Start of picture text -----**
D X A 1.
Y Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3.
6 5 4 FINISH THICKNESS. MINIMUM LEAD
E HE BASE MATERIAL.
4.
1 2 3 FLASH, PROTRUSIONS, OR GATE BURRS.
a||4 MILLIMETERS
DIM MIN NOM MAX
TOP VIEW C —> | A 0.34 0.37 0.40
SIDE VIEW b 0.10 0.15 0.20
C 0.07 0.12 0.17
D 0.95 1.00 1.05
e 6X L E 0.75 0.80 0.85
e 0.35 BSC
H E 0.95 1.00 1.05
L 0.19 REF
L2 0.05 0.10 0.15
GENERIC
Et MARKING DIAGRAM*
6X L2 6X b
0.08 X Y
t BOTTOM VIEW o ec o XM
**----- End of picture text -----**
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS |2.|Y14.5M, 1994.
CONTROLLING DIMENSION: MILLIMETERS|Y14.5M, 1994.
CONTROLLING DIMENSION: MILLIMETERS| |---|---|---| |3.
4.
~~|4~~
~~a||44~~|**DIM**
**MIN**
**NOM**
**MAX**
**MILLIMETERS**
MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
~~|4~~
~~a||44~~|| ||**A**
0.34
0.37
0.40|| ||**b**
0.10
0.15
0.20|| ||**C**
0.07
0.12
0.17|| ||**D**
0.95
1.00
1.05|| ||**E**
0.75
0.80
0.85|| ||**e**
0.35 BSC
0.95
1.00
1.05
**HE**
**L**
0.19 REF
**L2**
0.05
0.10
0.15|| - XM - 1 - X = Specific Device Code M = Month Code - STYLE 1: STYLE 2: STYLE 3: PIN 1. EMITTER 1 PIN 1. EMITTER 1 PIN 1. CATHODE 1 2. BASE 1 2. EMITTER2 2. CATHODE 1 3. COLLECTOR 2 3. BASE 2 3. ANODE/ANODE 2 4. EMITTER 2 4. COLLECTOR 2 4. CATHODE 2 5. BASE 2 5. BASE 1 5. CATHODE 2 6. COLLECTOR 1 6. COLLECTOR 1 6. ANODE/ANODE 1 - STYLE 4: STYLE 5: STYLE 6: PIN 1. COLLECTOR PIN 1. CATHODE PIN 1. CATHODE 2. COLLECTOR 2. CATHODE 2. ANODE 3. BASE 3. ANODE 3. CATHODE 4. EMITTER 4. ANODE 4. CATHODE 5. COLLECTOR 5. CATHODE 5. CATHODE 6. COLLECTOR 6. CATHODE 6. CATHODE - STYLE 7: STYLE 8: STYLE 9: PIN 1. CATHODE PIN 1. DRAIN PIN 1. SOURCE 1 2. ANODE 2. DRAIN 2. GATE 1 3. CATHODE 3. GATE 3. DRAIN 2 4. CATHODE 4. SOURCE 4. SOURCE 2 5. ANODE 5. DRAIN 5. GATE 2 6. CATHODE 6. DRAIN 6. DRAIN 1 - *This information is generic. Please refer to device data sheet for actual part marking. - Pb−Free indicator, “G” or microdot “ ”, may or may not be present. **==> picture [124 x 123] intentionally omitted <==** **----- Start of picture text -----**
RECOMMENDED
MOUNTING FOOTPRINT
6X 6X
0.20 “ ie 0.35
PACKAGE
OUTLINE
Oo 1.20
0.35 oe
PITCH
DIMENSIONS: MILLIMETERS
**----- End of picture text -----**
STYLE 10: PIN 1. CATHODE 1 2. N/C 3. CATHODE 2 4. ANODE 2 5. N/C 6. ANODE 1 **DOCUMENT NUMBER: 98AON26456D DESCRIPTION: SOT−963, 1X1, 0.35P** Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **PAGE 1 OF 1** ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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