# Bipolar Pre-Biased / Digital Transistor, Single PNP, 50 V, 100 mA, 47 kohm, 47 kohm ![Product image](https://novapart.co/image/farnell:3617405/) **URL**: https://novapart.co/products/SMUN2113T1G./bipolar-pre-biased-digital-transistor-single-pnp **SKU**: SMUN2113T1G. **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || Transistors || Bipolar Transistors || Pre-Biased / Digital Bipolar Transistors **Price**: €0.0230 **Stock**: 10+ ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | No SVHC (15-Jan-2018) | | No. Of Pins | 3 Pin | | Product Range | MUN2113 Series | | Qualification | AEC-Q101 | | Power Dissipation | 338mW | | Transistor Mounting | Surface Mount | | Transistor Polarity | Single PNP | | Transistor Case Style | SC-59 | | Base Input Resistor R1 | 47kohm | | Dc Current Gain Hfe Min | 80hFE | | Base Emitter Resistor R2 | 47kohm | | Operating Temperature Max | 150°C | | Continuous Collector Current | 100mA | | Collector Emitter Voltage Max Npn | - | | Collector Emitter Voltage Max Pnp | 50V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:3617405/) ## MUN2113, MMUN2113L, MUN5113, DTA144EE, DTA144EM3, NSBA144EF3 ## **www.onsemi.com**[@] **PIN CONNECTIONS** ## Digital Transistors (BRT) R1 = 47 k R2 = 47 k ## **PNP Transistors with Monolithic Bias Resistor Network** PIN 3 COLLECTOR (OUTPUT) PIN 1 R1 BASE (INPUT) R2 ~~@~~ PIN 2 EMITTER (GROUND) **MARKING DIAGRAMS** This series of digital transistors is designed to replace a single device and its external resistor bias network. The Bias Resistor Transistor (BRT) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base− emitter resistor. The BRT eliminates these individual components by integrating them into a single device. The use of a BRT can reduce both system cost and board space. ## **Features** - Simplifies Circuit Design **==> picture [483 x 436] intentionally omitted <==** **----- Start of picture text -----**
Simplifies Circuit Design
• Reduces Board Space SC−59
• Reduces Component Count XX M CASE 318D
STYLE 1
• S and NSV Prefix for Automotive and Other Applications Requiring
1
2
Unique Site and Control Change Requirements; AEC-Q101 Qualified
and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS XXX M SOT−23
CASE 318
Compliant STYLE 6
1
MAXIMUM RATINGS (TA = 25 ° C)
Rating Symbol Max Unit SC−70/SOT−323
XX M
CASE 419
Collector−Base Voltage VCBO 50 Vdc STYLE 3
Collector−Emitter Voltage VCEO 50 Vdc 1
Collector Current − Continuous IC 100 mAdc SC−75
Input Forward Voltage VIN(fwd) 40 Vdc XX M CASE 463
STYLE 1
Input Reverse Voltage VIN(rev) 10 Vdc a: 1
Stresses exceeding those listed in the Maximum Ratings table may damage the SOT−723
device. If any of these limits are exceeded, device functionality should not be XX M CASE 631AA
assumed, damage may occur and reliability may be affected. Sante 1 STYLE 1
SOT−1123
X M 1 CASE 524AA
STYLE 1
XXX = Specific Device Code
M = Date Code*
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending up-
on manufacturing location.
ORDERING INFORMATION
See detailed ordering, marking, and shipping information in
the package dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2012 1 Publication Order Number:
October, 2016 − Rev. 5 DTA144E/D
**----- End of picture text -----**
See detailed ordering, marking, and shipping information in the package dimensions section on page 2 of this data sheet. Publication Order Number: **DTA144E/D** **MUN2113, MMUN2113L, MUN5113, DTA144EE, DTA144EM3, NSBA144EF3** **Table 1. ORDERING INFORMATION** |**Table 1. ORDERING INFORMATION**|||| |---|---|---|---| |**Device**|**Part Marking**|**Package**|**Shipping**†| |MUN2113T1G, SMUN2113T1G*|6C|SC−59
(Pb−Free)|3000 / Tape & Reel| |MMUN2113LT1G, SMMUN2113LT1G*|A6C|SOT−23
(Pb−Free)|3000 / Tape & Reel| |MMUN2113LT3G, NSVMMUN2113LT3G*|A6C|SOT−23
(Pb−Free)|10000 / Tape & Reel| |MUN5113T1G, SMUN5113T1G*|6C|SC−70/SOT−323
(Pb−Free)|3000 / Tape & Reel| |MUN5113T3G|6C|SC−70/SOT−323
(Pb−Free)|10000 / Tape & Reel| |DTA144EET1G, NSVDTA144EET1G*|6C|SC−75
(Pb−Free)|3000 / Tape & Reel| |DTA144EM3T5G|6C|SOT−723
(Pb−Free)|8000 / Tape & Reel| |NSBA144EF3T5G|E|SOT−1123
(Pb−Free)|8000 / Tape & Reel| †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. **==> picture [243 x 172] intentionally omitted <==** **----- Start of picture text -----**
300
250
200
(1) (2) (3) (4) (5)
150
100
50
0
−50 −25 0 25 50 75 100 125 150
AMBIENT TEMPERATURE ( ° C)
, POWER DISSIPATION (mW)
D
P
**----- End of picture text -----**
- (1) SC−75 and SC−70/SOT−323; Minimum Pad - (2) SC−59; Minimum Pad - (3) SOT−23; Minimum Pad - (4) SOT−1123; 100 mm[2] , 1 oz. copper trace - (5) SOT−723; Minimum Pad **Figure 1. Derating Curve** **www.onsemi.com** **2** **MUN2113, MMUN2113L, MUN5113, DTA144EE, DTA144EM3, NSBA144EF3** ## **Table 2. THERMAL CHARACTERISTICS** |**Table 2. THERMAL CHARACTERISTICS**|||| |---|---|---|---| |**Characteristic**|**Symbol**|**Max**|**Unit**| |**THERMAL CHARACTERISTICS (SC−59) (MUN2113)**|||| |Total Device Dissipation
TA= 25°C
(Note 1)
(Note 2)
Derate above 25°C
(Note 1)
(Note 2)|PD|230
338
1.8
2.7|mW
mW/°C| |Thermal Resistance,
(Note 1)
Junction to Ambient
(Note 2)|R�JA|540
370|°C/W| |Thermal Resistance,
(Note 1)
Junction to Lead (Note 2)|R�JL|264
287|°C/W| |Junction and Storage Temperature Range|TJ, Tstg|−55 to +150|°C| |**THERMAL CHARACTERISTICS (SOT−23) (MMUN2113L)**|||| |Total Device Dissipation
TA= 25°C
(Note 1)
(Note 2)
Derate above 25°C
(Note 1)
(Note 2)|PD|246
400
2.0
3.2|mW
mW/°C| |Thermal Resistance,
(Note 1)
Junction to Ambient
(Note 2)|R�JA|508
311|°C/W| |Thermal Resistance,
(Note 1)
Junction to Lead (Note 2)|R�JL|174
208|°C/W| |Junction and Storage Temperature Range|TJ, Tstg|−55 to +150|°C| |**THERMAL CHARACTERISTICS (SC−70/SOT−323) (MUN5113)**|||| |Total Device Dissipation
TA= 25°C
(Note 1)
(Note 2)
Derate above 25°C
(Note 1)
(Note 2)|PD|202
310
1.6
2.5|mW
mW/°C| |Thermal Resistance,
(Note 1)
Junction to Ambient
(Note 2)|R�JA|618
403|°C/W| |Thermal Resistance,
(Note 1)
Junction to Lead (Note 2)|R�JL|280
332|°C/W| |Junction and Storage Temperature Range|TJ, Tstg|−55 to +150|°C| |**THERMAL CHARACTERISTICS (SC−75) (DTA144EE)**|||| |Total Device Dissipation
TA= 25°C
(Note 1)
(Note 2)
Derate above 25°C
(Note 1)
(Note 2)|PD|200
300
1.6
2.4|mW
mW/°C| |Thermal Resistance,
(Note 1)
Junction to Ambient
(Note 2)|R�JA|600
400|°C/W| |Junction and Storage Temperature Range|TJ, Tstg|−55 to +150|°C| |**THERMAL CHARACTERISTICS (SOT−723) (DTA144EM3)**|||| |Total Device Dissipation
TA= 25°C
(Note 1)
(Note 2)
Derate above 25°C
(Note 1)
(Note 2)|PD|260
600
2.0
4.8|mW
mW/°C| |Thermal Resistance,
(Note 1)
Junction to Ambient
(Note 2)|R�JA|480
205|°C/W| |Junction and Storage Temperature Range|TJ, Tstg|−55 to +150|°C| 1. FR−4 @ Minimum Pad. 2. FR−4 @ 1.0 x 1.0 Inch Pad. 3. FR−4 @ 100 mm[2] , 1 oz. copper traces, still air. 4. FR−4 @ 500 mm[2] , 1 oz. copper traces, still air. **www.onsemi.com** **3** **MUN2113, MMUN2113L, MUN5113, DTA144EE, DTA144EM3, NSBA144EF3** **Table 2. THERMAL CHARACTERISTICS** |**Table 2. THERMAL CHARACTERISTICS**|||| |---|---|---|---| |**Characteristic**|**Symbol**|**Max**|**Unit**| |**THERMAL CHARACTERISTICS (SOT−1123) (NSBA144EF3)**|||| |Total Device Dissipation
TA= 25°C
(Note 3)
(Note 4)
Derate above 25°C
(Note 3)
(Note 4)|PD|254
297
2.0
2.4|mW
mW/°C| |Thermal Resistance,
(Note 3)
Junction to Ambient
(Note 4)|R�JA|493
421|°C/W| |Thermal Resistance, Junction to Lead
(Note 3)|R�JL|193|°C/W| |Junction and Storage Temperature Range|TJ, Tstg|−55 to +150|°C| 1. FR−4 @ Minimum Pad. 2. FR−4 @ 1.0 x 1.0 Inch Pad. 3. FR−4 @ 100 mm[2] , 1 oz. copper traces, still air. 4. FR−4 @ 500 mm[2] , 1 oz. copper traces, still air. **Table 3. ELECTRICAL CHARACTERISTICS** (TA = 25 ° C, unless otherwise noted) |**Table 3. ELECTRICAL CHARACTERISTICS**(TA= 25°C, unless otherwi|se noted)||||| |---|---|---|---|---|---| |**Characteristic**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**| |**OFF CHARACTERISTICS**|||||| |Collector−Base Cutoff Current
(VCB= 50 V, IE= 0)|ICBO|−|−|100|nAdc| |Collector−Emitter Cutoff Current
(VCE= 50 V, IB= 0)|ICEO|−|−|500|nAdc| |Emitter−Base Cutoff Current
(VEB= 6.0 V, IC= 0)|IEBO|−|−|0.1|mAdc| |Collector−Base Breakdown Voltage
(IC= 10�A, IE= 0)|V(BR)CBO|50|−|−|Vdc| |Collector−Emitter Breakdown Voltage (Note 5)
(IC= 2.0 mA, IB= 0)|V(BR)CEO|50|−|−|Vdc| |**ON CHARACTERISTICS**|||||| |DC Current Gain (Note 5)
(IC= 5.0 mA, VCE= 10 V)|hFE|80|140|−|| |Collector−Emitter Saturation Voltage (Note 5)
(IC= 10 mA, IB= 0.3 mA)|VCE(sat)|−|−|0.25|Vdc| |Input Voltage (off)
(VCE= 5.0 V, IC= 100�A)|Vi(off)|−|1.2|0.8|Vdc| |Input Voltage (on)
(VCE= 0.3 V, IC= 2.0 mA)|Vi(on)|3.0|1.6|−|Vdc| |Output Voltage (on)
(VCC= 5.0 V, VB= 3.5 V, RL= 1.0 k�)|VOL|−|−|0.2|Vdc| |Output Voltage (off)
(VCC= 5.0 V, VB= 0.5 V, RL= 1.0 k�)|VOH|4.9|−|−|Vdc| |Input Resistor|R1|32.9|47|61.1|k�| |Resistor Ratio|R1/R2|0.8|1.0|1.2|| Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Pulsed Condition: Pulse Width = 300 msec, Duty Cycle ≤ 2%. **www.onsemi.com** **4** **MUN2113, MMUN2113L, MUN5113, DTA144EE, DTA144EM3, NSBA144EF3** ## **TYPICAL CHARACTERISTICS MUN2113, MMUN2113L, MUN5113, DTA144EE, DTA144EM3** **==> picture [488 x 382] intentionally omitted <==** **----- Start of picture text -----**
1 1000
IC/IB = 10
TA = 75 ° C
TA = −25 ° C 25 ° C 25 ° C
75 ° C −25 ° C
0.1 100
0.01
0 10 20 30 40 101 10 100
IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA)
Figure 2. VCE(sat) vs. IC Figure 3. DC Current Gain
10 100 TA = 75 ° C 25 ° C
9 f = 10 kHz
8 TlEA = 0 A = 25 ° C 10 −25 ° C
7
6 1
5
4 0.1
3
2 0.01
1 VO = 5 V
0 0.001
0 10 20 30 40 50 0 1 2 3 4 5 6 7 8 9 10
VR, REVERSE VOLTAGE (V) Vin, INPUT VOLTAGE (V)
VOLTAGE (V)
, CURRENT GAIN
, COLLECTOR−EMITTER
FE
h
CE(sat)
V
, OUTPUT CAPACITANCE (pF) , COLLECTOR CURRENT (mA)
Cob IC
**----- End of picture text -----**
**Figure 4. Output Capacitance** **Figure 5. Output Current vs. Input Voltage** **==> picture [237 x 168] intentionally omitted <==** **----- Start of picture text -----**
100
VO = 2 V
TA = −25 ° C
25 ° C
10
75 ° C
1
0.1
0 10 20 30 40 50
IC, COLLECTOR CURRENT (mA)
, INPUT VOLTAGE (V)
in
V
**----- End of picture text -----**
**Figure 6. Input Voltage vs. Output Current** **www.onsemi.com** **5** **MUN2113, MMUN2113L, MUN5113, DTA144EE, DTA144EM3, NSBA144EF3** **TYPICAL CHARACTERISTICS − NSBA144EF3** **==> picture [491 x 382] intentionally omitted <==** **----- Start of picture text -----**
1 1000
IC/IB = 10 25 ° C
150 ° C
25 ° C 100 −55 ° C
150 ° C
0.1
−55 ° C 10
V CE = 10 V
0.01 1
0 10 20 30 40 50 0.1 1 10 100
IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA)
Figure 7. VCE(sat) vs. IC Figure 8. DC Current Gain
7 100
f = 10 kHz 150 ° C
6 IE = 0 A −55 ° C
TA = 25 ° C 10
5 25 ° C
1
4
3
0.1
2
0.01
1 VO = 5 V
0 0.001
0 10 20 30 40 50 0 4 8 12 16 20 24 28
VR, REVERSE VOLTAGE (V) Vin, INPUT VOLTAGE (V)
VOLTAGE (V)
, COLLECTOR−EMITTER , DC CURRENT GAIN
FE
h
CE(sat)
V
, OUTPUT CAPACITANCE (pF) , COLLECTOR CURRENT (mA)
Cob IC
**----- End of picture text -----**
**Figure 9. Output Capacitance** **Figure 10. Output Current vs. Input Voltage** **==> picture [241 x 172] intentionally omitted <==** **----- Start of picture text -----**
100
25 ° C −55 ° C
10
1 150 ° C
V O = 0.2 V
0.1
0 10 20 30 40 50
IC, COLLECTOR CURRENT (mA)
, INPUT VOLTAGE (V)
in
V
**----- End of picture text -----**
**Figure 11. Input Voltage vs. Output Current** **www.onsemi.com** **6** MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** **==> picture [494 x 668] intentionally omitted <==** **----- Start of picture text -----**
SOT−23 (TO−236)
CASE 318−08
ISSUE AS
2 DATE 30 JAN 2018
SCALE 4:1
D NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.
0.25 MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF
“a 3 t = THE BASE MATERIAL.
| E HE T 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,PROTRUSIONS, OR GATE BURRS.
1 2
MILLIMETERS INCHES
DIM MIN NOM MAX MIN NOM MAX
L A 0.89 1.00 1.11 0.035 0.039 0.044
3X b L1 A1b 0.010.37 0.060.44 0.100.50 0.0000.015 0.0020.017 0.0040.020
e VIEW C c 0.08 0.14 0.20 0.003 0.006 0.008
TOP VIEW D 2.80 2.90 3.04 0.110 0.114 0.120
E 1.20 1.30 1.40 0.047 0.051 0.055
e 1.78 1.90 2.04 0.070 0.075 0.080
L 0.30 0.43 0.55 0.012 0.017 0.022
A L1 0.35 0.54 0.69 0.014 0.021 0.027
H E 2.10 2.40 2.64 0.083 0.094 0.104
= T 0 ° −−− 10 ° 0 ° −−− 10 °
a A1 SIDE VIEW SEE VIEW C c
GENERIC
END VIEW
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT XXXM
1
2.90 i 0.903X XXX = Specific Device Code oo
M = Date Code
= Pb−Free Package
LO | cr ,
*This information is generic. Please refer to
3X 0.80 a) LL 0.95 device data sheet for actual part marking.
PITCH Pb−Free indicator, “G” or microdot “ ”, |
DIMENSIONS: MILLIMETERS may or may not be present.
STYLE 1 THRU 5: STYLE 6: STYLE 7: STYLE 8:
CANCELLED PIN 1. BASE PIN 1. EMITTER PIN 1. ANODE
2. EMITTER 2. BASE 2. NO CONNECTION
3. COLLECTOR 3. COLLECTOR 3. CATHODE
STYLE 9: STYLE 10: STYLE 11: STYLE 12: STYLE 13: STYLE 14:
PIN 1. ANODE PIN 1. DRAIN PIN 1. ANODE PIN 1. CATHODE PIN 1. SOURCE PIN 1. CATHODE
2. ANODE 2. SOURCE 2. CATHODE 2. CATHODE 2. DRAIN 2. GATE
3. CATHODE 3. GATE 3. CATHODE−ANODE 3. ANODE 3. GATE 3. ANODE
STYLE 15: STYLE 16: STYLE 17: STYLE 18: STYLE 19: STYLE 20:
PIN 1. GATE PIN 1. ANODE PIN 1. NO CONNECTION PIN 1. NO CONNECTION PIN 1. CATHODE PIN 1. CATHODE
2. CATHODE 2. CATHODE 2. ANODE 2. CATHODE 2. ANODE 2. ANODE
3. ANODE 3. CATHODE 3. CATHODE 3. ANODE 3. CATHODE−ANODE 3. GATE
STYLE 21: STYLE 22: STYLE 23: STYLE 24: STYLE 25: STYLE 26:
PIN 1. GATE PIN 1. RETURN PIN 1. ANODE PIN 1. GATE PIN 1. ANODE PIN 1. CATHODE
2. SOURCE 2. OUTPUT 2. ANODE 2. DRAIN 2. CATHODE 2. ANODE
3. DRAIN 3. INPUT 3. CATHODE 3. SOURCE 3. GATE 3. NO CONNECTION
STYLE 27: STYLE 28:
PIN 1. CATHODE PIN 1. ANODE
2. CATHODE 2. ANODE
3. CATHODE 3. ANODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42226B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: SOT−23 (TO−236) PAGE 1 OF 1
aes
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
**----- End of picture text -----**
www.onsemi.com © Semiconductor Components Industries, LLC, 2019 MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** **==> picture [275 x 39] intentionally omitted <==** **----- Start of picture text -----**
SC−59
CASE 318D−04
ISSUE H
DATE 28 JUN 2012
**----- End of picture text -----**
**==> picture [216 x 363] intentionally omitted <==** **----- Start of picture text -----**
SCALE 2:1
ros D
3
HE 1 2 E
b
e
C
A
L
A1
SOLDERING FOOTPRINT*
0.95
a 0.95 0.037
0.037
2.4
ae
0.094
1.0
0.039
0.8 SCALE 10:1 mm
0.031 - A inches
**----- End of picture text -----**
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. **==> picture [193 x 107] intentionally omitted <==** **----- Start of picture text -----**
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
— MILLIMETERS INCHES
DIM MIN NOM MAX MIN NOM MAX
A 1.00 1.15 1.30 0.039 0.045 0.051
A1 0.01 0.06 0.10 0.001 0.002 0.004
b 0.35 0.43 0.50 0.014 0.017 0.020
c 0.09 0.14 0.18 0.003 0.005 0.007
D 2.70 2.90 3.10 0.106 0.114 0.122
E 1.30 1.50 1.70 0.051 0.059 0.067
e 1.70 1.90 2.10 0.067 0.075 0.083
L 0.20 0.40 0.60 0.008 0.016 0.024
H E 2.50 2.80 3.00 0.099 0.110 0.118
**----- End of picture text -----**
**==> picture [150 x 128] intentionally omitted <==** **----- Start of picture text -----**
GENERIC
MARKING DIAGRAM
XXX M
1 =
XXX = Specific Device Code
M = Date Code
= Pb−Free Package*
(*Note: Microdot may be in either location)
**----- End of picture text -----**
*This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ ”, may or may not be present. **==> picture [201 x 72] intentionally omitted <==** **----- Start of picture text -----**
STYLE 1: STYLE 2: STYLE 3:
PIN 1. BASE PIN 1. ANODE PIN 1. ANODE
2. EMITTER 2. N.C. 2. ANODE
3. COLLECTOR 3. CATHODE 3. CATHODE
STYLE 4: STYLE 5: STYLE 6:
PIN 1. CATHODE PIN 1. CATHODE PIN 1. ANODE
2. N.C. 2. CATHODE 2. CATHODE
3. ANODE 3. ANODE 3. ANODE/CATHODE
**----- End of picture text -----**
Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ASB42664B** Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **DESCRIPTION: SC−59 PAGE 1 OF 1** ~~aes~~ ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. www.onsemi.com © Semiconductor Components Industries, LLC, 2019 MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** **==> picture [480 x 409] intentionally omitted <==** **----- Start of picture text -----**
SC−70 (SOT−323)
CASE 419−04
ISSUE N
® DATE 11 NOV 2008
SCALE 4:1
D NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
e1 2. CONTROLLING DIMENSION: INCH.
MILLIMETERS INCHES
3 DIM MIN NOM MAX MIN NOM MAX
A 0.80 0.90 1.00 0.032 0.035 0.040
HE E A1 0.00 0.05 0.10 0.000 0.002 0.004
1 2 A2 0.70 REF 0.028 REF
b 0.30 0.35 0.40 0.012 0.014 0.016
c 0.10 0.18 0.25 0.004 0.007 0.010
i an ) = D 1.80 2.10 2.20 0.071 0.083 0.087
j an ) ==
b E 1.15 1.24 1.35 0.045 0.049 0.053
e 1.20 1.30 1.40 0.047 0.051 0.055
e e1 0.65 BSC 0.026 BSC
L 0.20 0.38 0.56 0.008 0.015 0.022
H E 2.00 2.10 2.40 0.079 0.083 0.095
A A2 c
GENERIC
0.05 (0.002) L MARKING DIAGRAM
_ —_ He A1 , Joka
SOLDERING FOOTPRINT* XX M
0.65
oe 0.65 0.025 1 =
0.025
XX = Specific Device Code
M = Date Code
= Pb−Free Package
1.9 *This information is generic. Please refer to
oe
0.075 device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ ”,
0.9 may or may not be present.
0.035
0.7
0.028
SCALE 10:1 mm
~ ~ = inches
**----- End of picture text -----**
DATE 11 NOV 2008 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. **==> picture [411 x 63] intentionally omitted <==** **----- Start of picture text -----**
STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5:
CANCELLED PIN 1. ANODE PIN 1. BASE PIN 1. CATHODE PIN 1. ANODE
2. N.C. 2. EMITTER 2. CATHODE 2. ANODE
3. CATHODE 3. COLLECTOR 3. ANODE 3. CATHODE
STYLE 6: STYLE 7: STYLE 8: STYLE 9: STYLE 10: STYLE 11:
PIN 1. EMITTER PIN 1. BASE PIN 1. GATE PIN 1. ANODE PIN 1. CATHODE PIN 1. CATHODE
2. BASE 2. EMITTER 2. SOURCE 2. CATHODE 2. ANODE 2. CATHODE
3. COLLECTOR 3. COLLECTOR 3. DRAIN 3. CATHODE-ANODE 3. ANODE-CATHODE 3. CATHODE
**----- End of picture text -----**
Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ASB42819B** Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **DESCRIPTION: SC−70 (SOT−323) PAGE 1 OF 1** ~~[_eo~~ ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. www.onsemi.com © Semiconductor Components Industries, LLC, 2019 MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** **==> picture [35 x 49] intentionally omitted <==** **----- Start of picture text -----**
3 oe 2
1
SCALE 4:1
**----- End of picture text -----**
**SC−75/SOT−416** CASE 463−01 ISSUE G DATE 07 AUG 2015 **==> picture [430 x 472] intentionally omitted <==** **----- Start of picture text -----**
−E− NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
T o T Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
2
MILLIMETERS INCHES
3 DIM MIN NOM MAX MIN NOM MAX
e −D− A 0.70 0.80 0.90 0.027 0.031 0.035
1 A1 0.00 0.05 0.10 0.000 0.002 0.004
b 3 PL b 0.15 0.20 0.30 0.006 0.008 0.012
0.20 (0.008) a M D HE 0.20 (0.008) E CDE 0.101.550.70 0.151.600.80 0.251.650.90 0.0040.0610.027 0.0060.0630.031 0.0100.0650.035
e 1.00 BSC 0.04 BSC
L 0.10 0.15 0.20 0.004 0.006 0.008
q a—D = B HE 1.50 1.60 BE 1.70 0.060 0.063 0.067
C
A GENERIC
MARKING DIAGRAM*
L A1
XX M
STYLE 1: STYLE 2: STYLE 3:
PIN 1. BASE PIN 1. ANODE PIN 1. ANODE
2. EMITTER Jo 2. N/C 2. ANODE 1 a
3. COLLECTOR 3. CATHODE 3. CATHODE
XX = Specific Device Code
STYLE 4: STYLE 5: M = Date Code
PIN 1. CATHODE PIN 1. GATE
2. CATHODE 2. SOURCE = Pb−Free Package
3. ANODE 3. DRAIN *This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ ”,
may or may not be present.
SOLDERING FOOTPRINT*
0.356
0.014
aT
1.803 0.787
0.071 0.031
7 Mm _
_ 0.508 a
0.020 1.000
0.039
SCALE 10:1 mm
(—) inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
**----- End of picture text -----**
**PAGE 1 OF 1** ~~—_~~ Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ASB15184C** Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **DESCRIPTION: SC−75/SOT−416 PAGE 1 OF 1** ~~[[-_}__—__§_—___—_~~ ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. www.onsemi.com © Semiconductor Components Industries, LLC, 2019 MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** **SOT−1123** CASE 524AA ISSUE C ## DATE 29 NOV 2011 **SCALE 8:1** **==> picture [384 x 260] intentionally omitted <==** **----- Start of picture text -----**
D −X− NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
OR −Y− Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
1 3 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
E FINISH. MINIMUM LEAD THICKNESS IS THE
2 MINIMUM THICKNESS OF BASE MATERIAL.
coe 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
TOP VIEW
MILLIMETERS
A DIM MIN MAX
A 0.34 0.40
b 0.15 0.28
b1 0.10 0.20
c 0.07 0.17
D 0.75 0.85
c Ph HE E 0.55 0.65
e 0.35 0.40
SIDE VIEW HE 0.95 1.05
L 0.185 REF
foi O L2 0.05 o 0.15
3X L2 b GENERIC
0.08 X Y
y “Efe MARKING DIAGRAM*
e
X M
3X L
ee 2X b1
BOTTOM VIEW X = Specific Device Code
M = Date Code
SOLDERING FOOTPRINT* *This information is generic. Please refer
**----- End of picture text -----**
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ ”, may or may not be present. **==> picture [160 x 99] intentionally omitted <==** **----- Start of picture text -----**
1.20
3X 0.34
0.26
1
al:
0.38 2X
aan 0.20 S PACKAGE s
OUTLINE
DIMENSIONS: MILLIMETERS
**----- End of picture text -----**
- *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. **==> picture [300 x 26] intentionally omitted <==** **----- Start of picture text -----**
STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5:
PIN 1. BASE PIN 1. ANODE PIN 1. ANODE PIN 1. CATHODE PIN 1. GATE
2. EMITTER 2. N/C 2. ANODE 2. CATHODE 2. SOURCE
3. COLLECTOR 3. CATHODE 3. CATHODE 3. ANODE 3. DRAIN
**----- End of picture text -----**
Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON23134D** Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **DESCRIPTION: SOT−1123, 3−LEAD, 1.0X0.6X0.37, 0.35P PAGE 1 OF 1** ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. www.onsemi.com © Semiconductor Components Industries, LLC, 2019 MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** **SOT−723** CASE 631AA−01 ISSUE D DATE 10 AUG 2009 **SCALE 4:1** **==> picture [451 x 252] intentionally omitted <==** **----- Start of picture text -----**
−X− NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
D Y14.5M, 1994.
b1 A 2. CONTROLLING DIMENSION: MILLIMETERS.
3 −Y− 3. MAXIMUM LEAD THICKNESS INCLUDES LEADFINISH. MINIMUM LEAD THICKNESS IS THE MINIMUMFINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM
THICKNESS OF BASE MATERIAL.
E H E 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
1 2
Go 2X b tf MILLIMETERS
C DIM MIN NOM MAX
2X e 0.08 X Y A 0.45 0.50 0.55
SIDE VIEW b 0.15 0.21 0.27
TOP VIEW b1 0.25 0.31 0.37
C 0.07 0.12 0.17
3X L D 1.15 1.20 1.25
1 E 0.75 0.80 0.85
e 0.40 BSC
H E 1.15 1.20 1.25
L 0.29 REF
L2 0.15 0.20 0.25
3X L2 |CU E GENERIC
BOTTOM VIEW MARKING DIAGRAM*
STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5:
PIN 1. BASE PIN 1. ANODE PIN 1. ANODE PIN 1. CATHODE PIN 1. GATE XX M
2. EMITTER 2. N/C 2. ANODE 2. CATHODE 2. SOURCE
3. COLLECTOR 3. CATHODE 3. CATHODE 3. ANODE 3. DRAIN
=
1
XX = Specific Device Code
RECOMMENDED
M = Date Code
**----- End of picture text -----**
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. MAXIMUM LEAD THICKNESS INCLUDES LEADFINISH. MINIMUM LEAD THICKNESS IS THE MINIMUMFINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. **==> picture [177 x 173] intentionally omitted <==** **----- Start of picture text -----**
RECOMMENDED
SOLDERING FOOTPRINT*
2X
0.40
2X 0.27
“Ar
PACKAGE
OUTLINE
SAE]
1.50
3X 0.52 aoe 0.36
DIMENSIONS: MILLIMETERS
**----- End of picture text -----**
*This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G”, may or not be present. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON12989D** Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **DESCRIPTION: SOT−723 PAGE 1 OF 1** ~~SE~~ ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. www.onsemi.com © Semiconductor Components Industries, LLC, 2019 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. 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