# Oscillator, LVDS, 644.53125 MHz, 25 ppm, SMD, 3.2mm x 2.5mm, 2.5 V, SiT9367 Series

![Product image](https://novapart.co/image/farnell:2850202/)

**URL**: https://novapart.co/products/SIT9367AC-2B2-25E644.531250G/oscillator-lvds-64453125-mhz-25-ppm-smd-32mm-x
**SKU**: SIT9367AC-2B2-25E644.531250G
**Manufacturer**: SITIME
**Category**: Crystals & Oscillators || Oscillators || MEMS Oscillators
**Price**: €15.2400
**Stock**: 50+
**Lead Time**: 50 days (indicative)

## Description

Frequency Nom:644.53125MHz; Frequency Stability + / -:25ppm; Oscillator Case:SMD, 3.2mm x 2.5mm; Supply Voltage Nom:2.5V; Product Range:SiT9367 Series; Operating Temperature Min:-20°C;

## Specifications

| Parameter | Value |
|---|---|
| Svhc | No SVHC (27-Jun-2024) |
| Frequency Nom | 644.53125MHz |
| Product Range | SiT9367 |
| Supply Voltage Nom | 2.5V |
| Frequency Stability + / - | 25ppm |
| Operating Temperature Max | 70°C |
| Operating Temperature Min | -20°C |
| Oscillator Case / Package | SMD, 3.2mm x 2.5mm |
| Oscillator Output Compatibility | LVDS |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2850202/)

## **SiT9367** 

## 220 MHz to 725 MHz Ultra-low Jitter Differential Oscillator 

## **Description** 

The SiT9367 is a 220.000001 MHz to 725 MHz differential MEMS XO engineered for low-jitter applications. Utilizing SiTime’s unique DualMEMS™ temperature sensing and TurboCompensation™ technology, the SiT9367 delivers exceptional dynamic performance by providing resistance to airflow, thermal gradients, shock and vibration. This device also integrates multiple on-chip regulators to filter power supply noise, eliminating the need for a dedicated external LDO. 

## **Features** 

- Any frequency between 220.000001 MHz and 725 MHz, accurate to 6 decimal places. 

   - For HCSL output signaling, maximum frequency is 500 MHz. Contact SiTime for higher frequency options. (For additional frequencies, refer to SiT9366 and SiT9365 datasheets) 

- LVPECL, Low-swing LVPECL, LVDS and HCSL output signaling 

- 0.1ps RMS phase jitter (random) for Ethernet applications 

- Frequency stability as low ±10 ppm 

The SiT9367 can be factory programmed for any combination of frequency, stability, voltage, and output signaling. Programmability enables designers to optimize clock configurations while eliminating long lead times and customization costs associated with quartz devices where each frequency is custom built. 

The wide frequency range and programmability makes this device ideal for telecom, networking, and industrial applications that require a variety of frequencies and operate in noisy environments. 

- Wide temperature range from -40°C to 105°C Contact SiTime for higher temperature range options 

- Industry-standard packages: 3.2 x 2.5 mm[2] , 7.0 x 5.0 mm[2] and 5.0 x 3.2 mm[2] package 

## **Applications** 

- 100 Gbps Ethernet, SONET, SATA, SAS, Fibre Channel 

- Telecom, networking, instrumentation, storage, servers 

Refer to Manufacturing Notes for proper reflow profile, tape and reel dimension, and other manufacturing related information. 

## **Block Diagram** 

## **Package Pinout** 

**==> picture [106 x 64] intentionally omitted <==**

**----- Start of picture text -----**<br>
OE/NC 1= 1 Jrt 6 VDD<br>[.--- |--<br>NC 1 2 i i) 5 ! OUT-<br>mot |<br>GND |; 3 4 ot 4 | OUT+<br>voy Loy<br>**----- End of picture text -----**<br>


**Figure 1. SiT9367 Block Diagram** 

**Figure 2. Pin Assignments (Top view)** (Refer to Table 6 for Pin Descriptions) 

Rev 1.06 

August 17, 2019 

www.sitime.com 

**SiT9367** 220 MHz to 725 MHz Ultra-low Jitter Differential Oscillator 

## **Ordering Information** 

## SiT9367AC -1B2-33E322.265625T 

**==> picture [377 x 326] intentionally omitted <==**

**----- Start of picture text -----**<br>
Part Family Packaging<br>“SiT9367” “T”, “Y”, “D” or “E”<br>Refer to table below for packing method<br>Leave Blank for Bulk [[1]]<br>Revision Letter<br>“A” is the revision of Silicon<br>Frequency<br>220.00001 to 725 MHz for LVDS and<br>Temperature Range<br>LVPECL output drivers<br>“C”: Extended Commercial, -20 to 70°C 220.00001 to 500 MHz for HCSL driver [[2]]<br>“I”:  Industrial, -40 to 85°C<br>“B”: -40 to 95°C<br>“E”: Extended Industrial, -40 to 105°C Feature Pin<br>“N”: No Connect<br>“E”: Output Enable<br>Signalling Type<br>“1”:  LVPECL<br>“2”:  LVDS<br>“4”:  HCSL<br>Voltage Supply<br>“5”:  Low-swing LVPECL<br>“25”: 2.5 V ±10%<br>“28”: 2.8 V ±10%<br>“30”: 3.0 V ±10%<br>Package Size<br>“33”: 3.3 V ±10%<br>“B”: 3.2 x 2.5 mm<br>“C”: 5.0 x 3.2 mm with center pad<br>“E”: 7.0 x 5.0 mm with center pad<br>Frequency Stability<br>“F”:  ±10 ppm<br>“1”:  ±20 ppm<br>“2”:  ±25 ppm<br>“3”:  ±50 ppm<br>**----- End of picture text -----**<br>


## **Notes:** 

1. Bulk is available for sampling only. 

2. Contact SiTime for higher frequency HCSL options. 

**Table 1. Ordering Codes for Supported Tape & Reel Packing Method** 

|**Device Size**|**8 mm T&R**|**8 mm T&R**|**12 mm T&R**|**12 mm T&R**|**16 mm T&R**|**16 mm T&R**|
|---|---|---|---|---|---|---|
|**(mm x mm)**|**(3ku)**|**(1ku)**|**(3ku)**|**(1ku)**|**(3ku)**|**(1ku)**|
|7.0 x 5.0|—|—|—|—|T|Y|
|5.0 x 3.2|||T|Y|||
|3.2 x 2.5|D|E|||—|—|



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Rev 1.06 

www.sitime.com 

**SiT9367** 220 MHz to 725 MHz Ultra-low Jitter Differential Oscillator 

## **TABLE OF CONTENTS** 

Description ................................................................................................................................................................................... 1 Features ....................................................................................................................................................................................... 1 Applications .................................................................................................................................................................................. 1 Block Diagram .............................................................................................................................................................................. 1 Package Pinout ............................................................................................................................................................................ 1 Ordering Information .................................................................................................................................................................... 2 Electrical Characteristics .............................................................................................................................................................. 2 Waveform Diagrams..................................................................................................................................................................... 6 Termination Diagrams .................................................................................................................................................................. 8 LVPECL and Low-swing LVPECL ......................................................................................................................................... 8 LVDS ................................................................................................................................................................................... 10 HCSL .................................................................................................................................................................................. 11 Dimensions and Patterns ― 3.2 x 2.5 mm[2] ................................................................................................................................ 12 Dimensions and Patterns ― 5.0 x 3.2 mm[2] ................................................................................................................................ 12 Dimensions and Patterns ― 7.0 x 5.0 mm[2] ................................................................................................................................ 13 Additional Information ................................................................................................................................................................. 14 Revision History ......................................................................................................................................................................... 15 

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Rev 1.06 

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**SiT9367** 220 MHz to 725 MHz Ultra-low Jitter Differential Oscillator 

## **Electrical Characteristics** 

All Min and Max limits in the Electrical Characteristics tables are specified over temperature and rated operating voltage with standard output termination shown in the termination diagrams. Typical values are at 25°C at nominal supply voltage. 

**Table 2. Electrical Characteristics – Common to LVPECL, Low-swing LVPECL, LVDS and HCSL** 

|**Parameter**|**Symbol**|**Min.**|**Typ.**|**Typ.**|**Max.**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|---|
||||**Frequency Range **|||||
|**Output Frequency Range **|f|220.000001|–||725|MHz|Accurate to 6 decimalplaces|
||||**Frequency Stability**|||||
|**Frequency Stability**|F_stab|-10|–||+10|ppm|Inclusive of initial tolerance, operating temperature, rated power<br>supply voltage and load variations|
|||-20|–||+20|ppm||
|||-25|–||+25|ppm||
|||-50|–||+50|ppm||
|**First Year Aging**|F_1y|-0.7|±0.4||+0.7|ppm|At 85°C|
|**5 Year Aging**|F_5y|-1.1|±0.7||+1.1|ppm|At 85°C|
|**10 Year Aging**|F_10y|-1.3|±0.8||+1.3|ppm|At 85°C|
|**20 Year Aging**|F_20y|-1.5|±1.0||+1.5|ppm|At 85°C|
||||**Temperature Range**|||||
|**Operating Temperature Range**|T_use|-20|–||+70|°C|Extended Commercial|
|||-40|–||+85|°C|Industrial|
|||-40|–||+95|°C||
|||-40|–||+105|°C|Extended Industrial|
||||**Supply Voltage **|||||
|**Supply Voltage**|Vdd|2.97|3.30||3.63|V||
|||2.70|3.00||3.30|V||
|||2.52|2.80||3.08|V||
|||2.25|2.50||2.75|V||
||||**Input Characteristics**|||||
|**Input Voltage High **|VIH|70%|–||–|Vdd|Pin 1,OE|
|**Input Voltage Low**|VIL|–|–||30%|Vdd|Pin 1,OE|
|**Input Pull-up Impedance**|Z_in|–|100||-|kΩ|Pin 1,OE logic high or logic low|
||||**Output Characteristics**|||||
|**Duty Cycle**|DC|45|–||55|%||
||||**Startup and OE Timing**|||||
|**Startup Time**|T_start|–|–|3.0||ms|Measured from the time Vdd reaches its rated minimum value.|
|**OE Enable/Disable Time**|T_oe|–|–|3.8||µs|f = 322.265625 MHz. Measured from the time OE pin reaches rated<br>VIH and VIL to the time clock pins reach 90% of swing and high-Z.<br>SeeFigure 8andFigure 9|



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Rev 1.06 

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**SiT9367** 220 MHz to 725 MHz Ultra-low Jitter Differential Oscillator 

**Table 3. Electrical Characteristics – LVPECL Specific** 

|**Parameter**|**Symbol**|**Min.**|**Typ.**|**Max.**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|||**Current Consumption**|||||
|**Current Consumption**|Idd|–|–|94|mA|ExcludingLoad Termination Current,Vdd = 3.3V or 2.5V|
|**OE Disable Supply Current**|I_OE|–|–|63|mA|OE = Low|
|**Output Disable Leakage Current**|I_leak|–|0.15|–|A|OE = Low|
|**Maximum Output Current**|I_driver|–|–|33|mA|Maximum average current drawn from OUT+ or OUT-|
|||**Output Characteristics for LVPECL**|||||
|**Output High Voltage **|VOH|Vdd-1.15|–|Vdd-0.7|V|SeeFigure 4|
|**Output Low Voltage **|VOL|Vdd-2.0|–|Vdd-1.5|V|SeeFigure 4|
|**Output Differential Voltage Swing**|V_Swing|1.2|1.6|2.0|V|SeeFigure 5|
|**Rise/Fall Time**|Tr,Tf|–|225|330|ps|20% to 80%,seeFigure 5|
|||**Output Characteristics for Low-swing LVPECL**|||||
|**Output High Voltage **|VOH|Vdd-1.2|–|Vdd-0.75|<br>V|SeeFigure 4|
|**Output Low Voltage **|VOL|Vdd-1.8|–|Vdd-1.25|<br>V|SeeFigure 4|
|**Output Differential Voltage**<br>**Swing**|V_Swing|0.4|1|1.2|V|Output frequency1 to 220 MHz,SeeFigure 5|
|||0.4|1|1.6|V|Output frequency greater than 220 MHz,SeeFigure 5|
|**Rise/Fall Time**|Tr,Tf|–|225|320|ps|20% to 80%. SeeFigure 5|
|||**Jitter – 7.0 x 5.0 mm Package**|||||
|**RMS Period Jitter[3]**|T_jitt|–|1.0|1.6|Ps|f = 100,156.25 or 212.5 MHz,Vdd = 3.3V or 2.5V|
|**RMS Phase Jitter (random)**|T_phj|–|0.220|0.270|Ps|f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all<br>Vdd levels, includes spurs. Temperature ranges -20 to 70ºC and<br>-40 to 85ºC.|
|||–|0.220|0.300|Ps|f = 322.265625  MHz, Integration bandwidth = 12 kHz to 20 MHz,<br>all Vdd levels, includes spurs. Temperature ranges -40 to 95ºC and<br>-40 to 105ºC|
|||–|0.1|–|Ps|f = 322.265625 MHz, IEEE802.3-2005 10GbE jitter mask<br>integration bandwidth = 1.875 MHz to 20 MHz, Includes spurs, all<br>Vdd levels|
|||**Jitter – 5.0 x**||**3.2 and 3.2 x 2.5 m**||**m Packages**|
|**RMS Period Jitter[3]**|T_jitt|–|1.0|1.6|Ps|f = 100,156.25 or 212.5 MHz,Vdd = 3.3V or 2.5V|
|**RMS Phase Jitter (random)**|T_phj|–|0.225|0.282|ps|f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all<br>Vdd levels, includes spurs. Temperature ranges -20 to 70ºC and<br>-40 to 85ºC.|
|||–|0.225|0.315|ps|f = 322.265625  MHz, Integration bandwidth = 12 kHz to 20 MHz,<br>all Vdd levels, includes spurs. Temperature ranges -40 to 95ºC and<br>-40 to 105ºC|
|||–|0.1|–|ps|f = 322.265625 MHz, IEEE802.3-2005 10GbE jitter mask<br>integration bandwidth = 1.875 MHz to 20 MHz, Includes spurs, all<br>Vdd levels|



## **Notes:** 

3. Measured according to JESD65B 

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Rev 1.06 

www.sitime.com 

**SiT9367** 220 MHz to 725 MHz Ultra-low Jitter Differential Oscillator 

**Table 4. Electrical Characteristics – LVDS Specific** 

|**Parameter**|**Symbol**|**Min.**|**Typ.**|**Max.**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|||**Current Consumption**|||||
|**Current Consumption**|Idd|–|–|85|mA|ExcludingLoad Termination Current,Vdd = 3.3V or 2.5V|
|**OE Disable Supply Current**|I_OE|–|–|63|mA|OE = Low|
|**Output Disable Leakage Current**|I_leak|–|0.15|–|A|OE = Low|
|||**Output Characteristics**|||||
|**Differential Output Voltage **|VOD|300|–|450|mV|SeeFigure 6|
|**VOD Magnitude Change **|ΔVOD|–|–|50|mV|SeeFigure 6|
|**Offset Voltage **|VOS|1.125|–|1.375|V|SeeFigure 6|
|**VOS Magnitude Change **|ΔVOS|–|–|50|mV|SeeFigure 6|
|**Rise/Fall Time**|Tr, Tf|–|370|470|ps|Measured with 2 pF capacitive loading to GND, 20% to 80%,<br>seeFigure 3|
|||**Jitter – 7.0 x 5.0 mm Package**|||||
|**RMS Period Jitter[4]**|T_jitt|–|0.92|1.6|ps|f = 100, 156.25 or 212.5 MHz, Vdd = 3.3V or 2.5V|
|**RMS Phase Jitter (random)**|T_phj|–|0.215|0.265|ps|f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all<br>Vdd levels, includes spurs. Temperature ranges -20 to 70ºC and<br>-40-85ºC.|
|||–|0.215|0.280|ps|f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all<br>Vdd levels, includes spurs. Temperature ranges are -40 to 95ºC<br>and -40 to 105ºC.|
|||–|0.1|–|ps|f = 322.265625 MHz, IEEE802.3-2005 10GbE jitter mask<br>integration bandwidth = 1.875 MHz to 20 MHz. Includes spurs for<br>all Vdd levels.|
|||**Jitter – 5.0 x**||**3.2 and 3.2 x 2.5 m**||**m Packages**|
|**RMS Period Jitter[4]**|T_jitt|–|0.92|1.6|ps|f = 100, 156.25 or 212.5 MHz, Vdd = 3.3V or 2.5V|
|**RMS Phase Jitter (random)**|T_phj|–|0.235|0.282|ps|f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all<br>Vdd levels, includes spurs. Temperature ranges -20 to 70ºC and<br>-40-85ºC.|
|||–|0.235|0.310|ps|f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all<br>Vdd levels, includes spurs. Temperature ranges are -40 to 95ºC<br>and -40 to 105ºC.|
|||–|0.1|–|ps|f = 322.265625 MHz, IEEE802.3-2005 10GbE jitter mask<br>integration bandwidth = 1.875 MHz to 20 MHz. Includes spurs for<br>all Vdd levels.|



## **Notes:** 

4. Measured according to JESD65B 

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Rev 1.06 

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**SiT9367** 220 MHz to 725 MHz Ultra-low Jitter Differential Oscillator 

## ~~ee~~ 

**Table 5. Electrical Characteristics – HCSL Specific** 

|**Parameter**|**Symbol**|**Min.**|**Typ.**|**Max.**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|**Current Consumption**<br>~~es~~|||||||
|**Current Consumption**<br>~~es~~|Idd|–|–|97|mA|ExcludingLoad Termination Current,Vdd = 3.3V or 2.5V|
|**OE Disable Supply Current**<br>~~es~~<br>~~_~~|I_OE|–|–<br>~~—~~|63<br>~~—~~|mA<br>~~—~~|OE = Low|
|**Output Disable Leakage Current**<br>~~es~~<br>~~_~~|I_leak|–|0.15<br>~~—~~|–<br>~~—~~|A<br>~~—~~|OE = Low|
|**Maximum Output Current**<br>~~_~~<br>~~es~~|I_driver|–|–<br>~~—~~|35<br>~~—~~|mA<br>~~—~~|Maximum average current drawn from OUT+ or OUT-|
|**Output Characteristics**<br>~~_~~<br>~~—~~<br>~~es~~|||||||
|**Output High Voltage **<br>~~es~~<br>~~es~~|VOH|0.60|–|0.90|V|SeeFigure 4|
|**Output Low Voltage **<br>~~es~~<br>~~es~~|VOL|-0.05|–|0.08|V|SeeFigure 4|
|**Output Differential Voltage Swing**<br>~~es~~<br>~~re~~|V_Swing|1.2|1.4|1.9|V|SeeFigure 5|
|**Rise/Fall Time**<br>~~es~~<br>~~re~~<br>~~es~~|Tr, Tf|–<br>~~ee~~|360<br>~~ee~~|505|ps|Measured with 2 pF capacitive loading to GND, 20% to 80%,<br>seeFigure 4|
|**Jitter – 7.0 x 5.0 mm Package**<br>~~re~~<br>~~es~~<br>~~ee~~|||||||
|**RMS Period Jitter[5]**<br>~~es~~|T_jitt|–<br>~~ee~~<br>~~tt~~|1.0<br>~~ee~~<br>~~tt~~|1.6<br>~~ttep~~|ps<br>~~ep~~|f = 100,156.25 or 212.5 MHz,Vdd = 3.3V or 2.5V<br>~~ep~~|
|**RMS Phase Jitter (random)**<br>~~es~~<br>~~es~~|T_phj<br>|–<br>~~ee~~<br>~~tt~~<br>~~tft~~|0.215<br>~~ee~~<br>~~tt~~<br>~~tft~~|0.265<br>~~ttep~~<br>~~tfttf~~|ps<br>~~ep~~<br>~~tf~~|f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all<br>Vdd levels, includes spurs. Temperature ranges -20 to 70ºC and -<br>40 to 85ºC<br>~~ep~~<br>~~tf~~|
|||–<br>~~tt~~<br>~~tft~~<br>|0.215<br>~~tt~~<br>~~tft~~<br>|0.282<br>~~tt ep~~<br>~~tfttf~~<br>|ps<br>~~ep~~<br>~~tf~~<br>~~fp~~<br>|f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all<br>Vdd levels, includes spurs. Temperature range ranges  -40 to 95ºC<br>and -40 to 105ºC<br>~~ep~~<br>~~tf~~<br>~~fp~~<br>|
|||–<br>~~tft~~<br>~~ttt~~<br>|0.1<br>~~tft~~<br>~~ttt~~<br>|–<br>~~tft tf~~<br>~~ttt~~<br>|ps<br>~~tf~~<br>~~ttt~~<br>~~fp~~<br>|f = 322.265625 MHz, IEEE802.3-2005 10GbE jitter mask<br>integration bandwidth = 1.875 MHz to 20 MHz, Includes spurs, all<br>Vdd levels<br>~~tf~~<br>~~ttt~~<br>~~fp~~<br>|
|**Jitter – 5.0 x 3.2 and 3.2 x 2.5 mm Packages**<br>~~fp~~<br>~~es~~|||||||
|**RMS Period Jitter[5]**<br>~~es~~|T_jitt<br>|–<br>~~tt~~|1.0<br>~~tt~~|1.6<br>~~ttep~~|ps<br>~~fp~~<br>~~ep~~|f = 100,156.25 or 212.5 MHz,Vdd = 3.3V or 2.5V<br>~~fp~~<br>~~ep~~|
|**RMS Phase Jitter (random)**<br>~~es ~~|T_phj<br> <br>~~Pott~~|–<br> ~~tt~~<br>~~tt~~|0.235<br>~~tt~~<br>~~tt~~|0.282<br>~~ttep~~<br>~~ttep~~|ps<br>~~fp~~<br>~~ep~~<br>~~ep~~|f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all<br>Vdd levels, includes spurs. Temperature ranges -20 to 70ºC and -<br>40 to 85ºC<br>~~fp~~<br>~~ep~~<br>~~ep~~|
|||–<br> ~~tt~~<br>~~tt~~<br>~~Pott~~|0.235<br>~~tt~~<br>~~tt~~<br>~~Pott~~|0.305<br>~~tt ep~~<br>~~ttep~~<br>~~PottEp~~|ps<br>~~ep~~<br>~~ep~~<br>~~Ep~~|f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all<br>Vdd levels, includes spurs. Temperature ranges -40 to 95ºC and -<br>40 to 105ºC<br>~~ep~~<br>~~ep~~<br>~~Ep~~|
|||–<br>~~tt~~<br>~~Pott~~|0.1<br>~~tt~~<br>~~Pott~~|–<br>~~tt ep~~<br>~~PottEp~~|ps<br>~~ep~~<br>~~Ep~~|f = 322.265625 MHz, IEEE802.3-2005 10GbE jitter mask<br>integration bandwidth = 1.875 MHz to 20 MHz, Includes spurs for<br>all Vdd levels.<br>~~ep~~<br>~~Ep~~|



## **Note:** 

5. Measured according to JESD65B 

**Table 6. Pin Description** 

|**Pin**|**Map**|**Functionality**|**Functionality**|
|---|---|---|---|
|1|OE/NC|Output Enable<br>(OE)|H[6]: specified frequency output<br>L: output is high impedance|
|||Non Connect<br>(NC)|H or L or Open: No effect on output frequency or other device<br>functions.|
|2|NC|NA|No Connect; Leave it floating or connect to GND for better<br>heat dissipation|
|3|GND|Power|VDD Power SupplyGround|
|4|OUT+|Output|Oscillator output|
|5|OUT-|Output|Complementaryoscillator output|
|6|VDD|Power|Power supplyvoltage[7]|



## **Notes:** 

6. In OE mode, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. 

7. A capacitor of value 0.1 µF or higher between VDD and GND is required. An additional 10 µF capacitor between VDD and GND is required for the best phase jitter performance. 

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Rev 1.06 

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**SiT9367** 220 MHz to 725 MHz Ultra-low Jitter Differential Oscillator 

## **Table 7. Absolute Maximum Ratings** 

**Caution** : Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings. 

|**Parameter**|**Min.**|**Max.**|**Unit**|
|---|---|---|---|
|Vdd|-0.5|4.0|V|
|VIH||Vdd + 0.3V|V|
|VIL|-0.3||V|
|Storage Temperature|-65|150|ºC|
|Maximum Junction Temperature||130|ºC|
|SolderingTemperature(follow standard Pb-free soldering guidelines)||260|ºC|



## **Table 8. Thermal Considerations[[8]]** 

|**Package**|**JA, 4 Layer Board (°C/W)**|**JC, Bottom (°C/W)**|
|---|---|---|
|**3225, 6-pin**|80|30|
|**5032, 6-pin**|53|20|
|**7050, 6-pin**|52|19|



## **Notes:** 

8. Refer to JESD51 for JA and JC definitions, and reference layout used to determine the JA and JC values in the above table. 

**Table 9. Maximum Operating Junction Temperature[[9]]** 

|**Max Operating Temperature (ambient)**|**Maximum Operating Junction Temperature**|
|---|---|
|70°C|95°C|
|85°C|110°C|
|95°C|120°C|
|105°C|130°C|



## **Notes:** 

9. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature. 

## **Table 10. Environmental Compliance** 

|**Parameter**|**Test Conditions**|**Value**|**Unit**|
|---|---|---|---|
|Mechanical Shock Resistance|MIL-STD-883F, Method 2002|10,000|_g_|
|Mechanical Vibration Resistance|MIL-STD-883F,Method 2007|70|_g_|
|SolderingTemperature(follow standard Pb free soldering guidelines)|MIL-STD-883F,Method 2003|260|°C|
|Moisture SensitivityLevel|MSL1 @ 260°C|||
|Electrostatic Discharge(HBM)|HBM,JESD22-A114|2,000|V|
|Charge-Device Model ESD Protection|JESD220C101|750|V|
|Latch-upTolerance|JESD78 Compliant|||



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**SiT9367** 220 MHz to 725 MHz Ultra-low Jitter Differential Oscillator 

## **Waveform Diagrams** 

**==> picture [300 x 102] intentionally omitted <==**

**----- Start of picture text -----**<br>
OUT-<br>VOH<br>OUT+<br>VOL<br>GND<br>**----- End of picture text -----**<br>


**Figure 4. LVPECL, Low-swing LVPECL, and HCSL Voltage Levels per Differential Pin (i.e. OUT+, or OUT-)** 

**==> picture [230 x 193] intentionally omitted <==**

**----- Start of picture text -----**<br>
V<br>80% 80%<br>V_ Swing<br>0 V<br>t<br>20% 20%<br>Tr Tf<br>**----- End of picture text -----**<br>


**Figure 5. LVPECL, Low-swing LVPECL, and HCSL Voltage Levels Across Differential Pair (i.e. OUT+ minus OUT-)** 

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## **Waveform Diagrams (continued)** 

**==> picture [386 x 133] intentionally omitted <==**

**----- Start of picture text -----**<br>
OUT-<br>VOD<br>OUT+<br>VOS<br>Sf<br>GND<br>**----- End of picture text -----**<br>


## **Figure 6. LVDS Voltage Levels per Differential Pin (i.e. OUT+, or OUT-)** 

**==> picture [188 x 187] intentionally omitted <==**

**----- Start of picture text -----**<br>
V<br>80% 80%<br>0 V<br>t<br>20% 20%<br>Tr Tf<br>**----- End of picture text -----**<br>


**Figure 7. LVDS Differential Waveform (i.e. OUT+ minus OUT-)** 

**==> picture [431 x 135] intentionally omitted <==**

**----- Start of picture text -----**<br>
Vdd Vdd<br>OE Voltage<br>VIH<br>VIL<br>OE Voltage f T_oe_hw o<br>T_oe_hw<br>OUT- 90% OUT-<br>HZ HZ<br>OUT+ Se w hn OUT+ Ann<br>GND GND<br>Figure 8. Hardware OE Enable Timing  Figure 9. Hardware OE Disable Timing<br>**----- End of picture text -----**<br>


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## **Termination Diagrams** 

## **LVPECL and Low-swing LVPECL** 

**==> picture [330 x 118] intentionally omitted <==**

**----- Start of picture text -----**<br>
Shunt Bias Termination<br>LVPECL network 0.1μF<br>OUT+ Zo = 50Ω D+<br>OUT- Zo = 50Ω D-<br>0.1μF<br>RB RB VDD RB 50 Ω 50 Ω<br>3.3 V 100 Ω<br>2.5 V 48.7 Ω VT<br>**----- End of picture text -----**<br>


**Figure 10. LVPECL and Low-swing LVPECL with AC-coupled Termination** 

**==> picture [332 x 145] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>Thevenin-equivalent<br>Termination network<br>LVPECL R1 R1<br>OUT+ Zo = 50Ω D+<br>OUT- Zo = 50Ω D-<br>VDD R1 R2 R2 R2<br>3.3 V 127 Ω 82.5 Ω<br>2.5 V 250 Ω 62.5 Ω<br>**----- End of picture text -----**<br>


**Figure 11. LVPECL and Low-swing LVPECL DC-coupled Load Termination with Thevenin Equivalent Network** 

**==> picture [333 x 154] intentionally omitted <==**

**----- Start of picture text -----**<br>
Y-Bias Termination<br>network<br>LVPECL<br>OUT+ Zo = 50Ω D+<br>OUT- Zo = 50Ω D-<br>R1 R2<br>VDD R1 R2 R3<br>3.3 V 50 Ω 50 Ω 50 Ω C1 R3<br>0.1μF<br>2.5 V 50 Ω 50 Ω 18 Ω<br>**----- End of picture text -----**<br>


**Figure 12. LVPECL and Low-swing LVPECL with Y-Bias Termination** 

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## **Termination Diagrams (continued) LVPECL and Low-swing LVPECL (continued)** 

**==> picture [327 x 115] intentionally omitted <==**

**----- Start of picture text -----**<br>
Shunt Bias<br>LVPECL Termination network<br>OUT+ Zo = 50Ω D+<br>OUT- Zo = 50Ω D-<br>50 Ω 50 Ω<br>VT=VDD-2V<br>**----- End of picture text -----**<br>


**Figure 13. LVPECL and Low-swing LVPECL with DC-coupled Parallel Shunt Load Termination** 

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## **Termination Diagrams (continued)** 

## **LVDS** 

**==> picture [319 x 93] intentionally omitted <==**

**----- Start of picture text -----**<br>
LVDS<br>OUT+ Zo = 50Ω OUT+<br>100 Ω<br>OUT- Zo = 50Ω OUT-<br>**----- End of picture text -----**<br>


**Figure 14. LVDS Single DC Termination at the Load** 

**==> picture [318 x 92] intentionally omitted <==**

**----- Start of picture text -----**<br>
LVDS 0.1μF<br>OUT+ Zo = 50Ω OUT+<br>100 Ω 100 Ω 0.1μF<br>OUT- Zo = 50Ω OUT-<br>**----- End of picture text -----**<br>


**Figure 15. LVDS double AC Termination with Capacitor Close to the Load** 

**==> picture [318 x 92] intentionally omitted <==**

**----- Start of picture text -----**<br>
LVDS<br>OUT+ Zo = 50Ω OUT+<br>100 Ω 100 Ω<br>OUT- Zo = 50Ω OUT-<br>**----- End of picture text -----**<br>


**Figure 16. LVDS Double DC Termination** 

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## **Termination Diagrams (continued)** 

## **HCSL** 

**==> picture [341 x 114] intentionally omitted <==**

**----- Start of picture text -----**<br>
R1<br>OUT+ Zo = 50Ω D+<br>OUT- Zo = 50Ω D-<br>R2<br>50Ω 50Ω<br>R1 = R2 = 33 Ω<br>**----- End of picture text -----**<br>


**Figure 17. HCSL Interface Termination** 

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## **Dimensions and Patterns ― 3.2 x 2.5 mm[2]** 

**==> picture [480 x 143] intentionally omitted <==**

**----- Start of picture text -----**<br>
Package Size – Dimensions (Unit: mm) [[10]] Recommended Land Pattern (Unit: mm) [[11]]<br>3.2 x 2.5 x 0.85 mm  3.2 x 2.5 x 0.85 mm<br>ra<br>Fora moaess | a [200 oomi]| ao]<br>-—{D}—~ (B| b | L -(L1)li wer\BODY SIZE |=w [om omens] 2.25<br>Pr) ay CE [exowors | _» | 0880] 0600 [osso|<br>E) so tunemn<br>Zz UU LU (P) Procekesorronrousrance|e[owe || 1 0 1000850 |<br>CORNER | jowramess | we | 0100 | __<br>ror porrouviw (T) urccocerparseuensne|»| = || evtorer | 0.65 1.05<br>Notes [=| ovonner | a<br>1.6<br>1.00<br>**----- End of picture text -----**<br>


## **Dimensions and Patterns ― 5.0 x 3.2 mm[2 ]** 

**==> picture [480 x 25] intentionally omitted <==**

**----- Start of picture text -----**<br>
Package Size – Dimensions (Unit: mm) [[10]] Recommended Land Pattern (Unit: mm) [[11]]<br>5.0 x 3.2 x 0.85 mm [[12]] 5.0 x 3.2 x 0.85 mm [[12]]<br>**----- End of picture text -----**<br>


## **Notes:** 

10. Top Marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the assembly location of the device. 

11. A capacitor of value 0.1 µF or higher between VDD and GND is required. An additional 10 µF capacitor between VDD and GND is required for the best phase jitter performance. 

12. The center pad has no electrical function. Soldering down the center pad to the GND is recommended for best thermal dissipati on, but is optional. 

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## **Dimensions and Patterns ― 7.0 x 5.0 mm[2 ]** 

**==> picture [480 x 25] intentionally omitted <==**

**----- Start of picture text -----**<br>
Package Size – Dimensions (Unit: mm) [[13]] Recommended Land Pattern (Unit: mm) [[14]]<br>7.0 x 5.0 x 0.85 mm [[15]] 7.0 x 5.0 x 0.85 mm [[15]]<br>**----- End of picture text -----**<br>


## **Notes:** 

13. Top Marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the assembly location of the device. 

14. A capacitor of value 0.1 µF or higher between VDD and GND is required. An additional 10 µF capacitor between VDD and GND is required for the best phase jitter performance. 

15. The center pad has no electrical function. Soldering down the center pad to the GND is recommended for best thermal dissipation, but is optional. 

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## **Additional Information** 

## **Table 11. Additional Information** 

|**Document**|**Description**|**Download Link**|
|---|---|---|
|**ECCN #: EAR99**|Five character designation used on the<br>commerce Control List (CCL) to identify dual<br>use items for export controlpurposes.|—|
|**HTS Classification Code:**<br>**8542.39.0000**|A Harmonized Tariff Schedule (HTS) code<br>developed by the World Customs Organization<br>to classify/define internationallytradedgoods.|—|
|**Part number Generator**|Tool used to create the part number based on<br>desired features.|—|
|**Manufacturing Notes**|Tape & Reel dimension, reflow profile and<br>other manufacturingrelated info|http://www.sitime.com/manufacturing-notes|
|**Qualification Reports**|RoHS report, reliability reports,<br>composition reports|http://www.sitime.com/support/quality-and-reliability|
|**Performance Reports**|Additional performance data such as phase<br>noise, current consumption and jitter for<br>selected frequencies|http://www.sitime.com/support/performance-measurement-report|
|**Termination Techniques**|Termination design recommendations|http://www.sitime.com/support/application-notes|
|**Layout Techniques**|Layout recommendations|http://www.sitime.com/support/application-notes|
|**Evaluation Boards**|SiT6085/6EB rev. 3.0, SiT6085EB rev.3.1 and<br>SiT6097EB rev. 2.0 Evaluation Boards for<br>Differential Oscillators User Manual|https://www.sitime.com/support/user-guides|



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## **Revision History** 

## **Table 12. Revision History** 

|**Revision**|**Release Date**|**Change Summary**|
|---|---|---|
|1.0|07/21/17|Initialdraft|
|1.03||Corrected max frequency in ordering information table.<br>Added 5.0 x 3.2 package.<br>Added preliminary IPJ numbers for 5032 package. Will be updated after characterization.<br>Corrected minor errors.<br>AddedAdditional Information Table.|
|1.04|05/11/2018|Performedminoredits and updated OrderingInformation.|
|1.05|10/25/2018|Removed “Contact SiTime” for ±10ppm|
|1.06|08/17/2019|Updated package Dimensions Drawings<br>Updated Table 8 Thermal Considerations for 5032 package<br>Updated Table 2 specification for First Year Aging<br>Added 5, 10, and 20 year aging specs<br>Added Evaluation Boards SiT6085EB reference in Additional Information<br>Rearranged layout, added Description, Block Diagram and TOC<br>Tightened LVDS minimum VOD specification<br>Added HTS code<br>Added low-swing LVPECL package code and specifications|



**SiTime Corporation** , 5451 Patrick Henry Drive, Santa Clara, CA 95054, USA | **Phone:** +1-408-328-4400 | **Fax:** +1-408-328-4439 

> © SiTime Corporation 2017-2019. The information contained herein is subject to change at any time without notice. SiTime assumes no responsibility or liability for any loss, damage or defect of a Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect or accident, (iii) unauthorized modification or repairs which have been soldered or altered during assembly and are not capable of being tested by SiTime under its normal test conditions, or (iv) improper installation, storage, handling, warehousing or transportation, or (v) being subjected to unusual physical, thermal, or electrical stress. 

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## CRITICAL USE EXCLUSION POLICY 

BUYER AGREES NOT TO USE SITIME'S PRODUCTS FOR ANY APPLICATION OR IN ANY COMPONENTS USED IN LIFE SUPPORT DEVICES OR TO OPERATE NUCLEAR FACILITIES OR FOR USE IN OTHER MISSION-CRITICAL APPLICATIONS OR COMPONENTS WHERE HUMAN LIFE OR PROPERTY MAY BE AT STAKE. 

SiTime owns all rights, title and interest to the intellectual property related to SiTime's products, including any software, firmware, copyright, patent, or trademark. The sale of SiTime products does not convey or imply any license under patent or other rights. SiTime retains the copyright and trademark rights in all documents, catalogs and plans supplied pursuant to or ancillary to the sale of products or services by SiTime. Unless otherwise agreed to in writing by SiTime, any reproduction, modification, translation, compilation, or representation of this material shall be strictly prohibited. 

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## Links

- [View this product on Novapart](https://novapart.co/products/SIT9367AC-2B2-25E644.531250G/oscillator-lvds-64453125-mhz-25-ppm-smd-32mm-x)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/sitime/sit9367ac-2b2-25e644-531250g/osc-644-53125mhz-3-2x2-5mm-lvds/dp/2850202)
---

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