# Oscillator, HCSL, 156.25 MHz, 25 ppm, SMD, 3.2mm x 2.5mm, 3.3 V, SiT9365 Series

![Product image](https://novapart.co/image/farnell:2850196/)

**URL**: https://novapart.co/products/SIT9365AC-4B2-33E156.250000G/oscillator-hcsl-15625-mhz-25-ppm-smd-32mm-x-25mm
**SKU**: SIT9365AC-4B2-33E156.250000G
**Manufacturer**: SITIME
**Category**: Crystals & Oscillators || Oscillators || Standard Oscillators
**Price**: €4.3400
**Stock**: 10+

## Specifications

| Parameter | Value |
|---|---|
| Frequency Nom | 156.25MHz |
| Product Range | SiT9365 |
| Oscillator Case | SMD, 3.2mm x 2.5mm |
| Supply Voltage Nom | 3.3V |
| Frequency Stability + / - | 25ppm |
| Operating Temperature Max | 70°C |
| Operating Temperature Min | -20°C |
| Oscillator Output Compatibility | HCSL |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2850196/)

Standard Frequency Ultra-low Jitter Differential Oscillator 

## **SiT9365** 

## **Features** 

- 32 standard frequencies from 25 MHz to 322.265625 MHz 

- LVPECL, LVDS and HCSL output signaling 

## **Applications** 

   - 10/40/100 GB Ethernet, SONET, SATA, SAS, Fibre Channel 

   - Telecom, networking, instrumentation, storage, servers 

- 0.1 ps RMS phase jitter (random) for Ethernet applications 

- Contact SiTime for ±10 ppm frequency stability 

- Wide temperature range from -40°C to 85°C Contact SiTime for higher temperature range options 

- Industry-standard packages: 3.2 x 2.5, 7.0 x 5.0 mm Contact SiTime for 5.0 x 3.2 mm package 

**==> picture [244 x 48] intentionally omitted <==**

## **Electrical Characteristics** 

All Min and Max limits in the Electrical Characteristics tables are specified over temperature and rated operating voltage with standard output termination show in the termination diagrams. Typical values are at 25°C and nominal supply voltage. 

**Table 1. Electrical Characteristics – Common to LVPECL, LVDS and HCSL** 

|**Parameter**|**Symbol**|**Min.**|**Typ.**|**Max.**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|||**Frequency Range **|||||
|**Output Frequency Range**|f|32 standard frequencies between<br>25 MHz and 322.265625 MHz|||MHz|Refer toTable 10for the list of supported frequencies|
||||**Frequency Stability**||||
|**Frequency Stability**|F_stab|-10|–|+10|ppm|Inclusive of initial tolerance, operating temperature, rated power<br>supplyvoltage and load variations. ContactSiTimefor ±10ppm|
|||-20|–|+20|ppm|Inclusive of initial tolerance, operating temperature, rated power<br>supply voltage and load variations.|
|||-25|–|+25|ppm||
|||-50|–|+50|ppm||
|**First Year Aging**|F_1y|–|±1|–|ppm|At 25°C|
||||**Temperature Range**||||
|**Operating Temperature Range**|T_use|-20|–|+70|°C|Extended Commercial|
|||-40|–|+85|°C|Industrial. ContactSiTimefor higher temperature range options|
||||**Supply Voltage **||||
|**Supply Voltage**|Vdd|2.97|3.30|3.63|V||
|||2.70|3.00|3.30|V||
|||2.52|2.80|3.08|V||
|||2.25|2.50|2.75|V||
||||**Input Characteristics**||||
|**Input Voltage High **|VIH|70%|–|–|Vdd|Pin 1,OE|
|**Input Voltage Low**|VIL|–|–|30%|Vdd|Pin 1,OE|
|**Input Pull-up Impedance**|Z_in|–|100|-|kΩ|Pin 1, OE logic high or logic low|
||||**Output Characteristics**||||
|**Duty Cycle**|DC|45|–|55|%||
||||**Startup and OE Timing**||||
|**Startup Time**|T_start|–|–|3.0|ms|Measured from the time Vdd reaches its rated minimum value.|
|**OE Enable/Disable Time**|T_oe|–|–|3.8|µs|f = 156.25 MHz.|



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**SiT9365** Standard Frequency Ultra-low Jitter Differential Oscillator 

**Table 2. Electrical Characteristics – LVPECL** 

|**Parameter**|**Symbol**|**Min.**|**Typ.**|**Max.**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|||||**Current Consumption**|||
|**Current Consumption**|Idd|–|–|89|mA|ExcludingLoad Termination Current,Vdd = 3.3V or 2.5V|
|**OE Disable Supply Current**|I_OE|–|–|58|mA|OE = Low|
|**Output Disable Leakage Current**|I_leak|–|0.15|–|µA|OE = Low|
|**Maximum Output Current**|I_driver|–|–|32|mA|Maximum average current drawn from OUT+ or OUT-|
|||||**Output Characteristics**|||
|**Output High Voltage **|VOH|Vdd-1.1|–|Vdd-0.7|V|See Figure 2|
|**Output Low Voltage **|VOL|Vdd-1.9|–|Vdd-1.5|V|See Figure 2|
|**Output Differential Voltage Swing**|V_Swing|1.2|1.6|2.0|V|See Figure 3|
|**Rise/Fall Time**|Tr, Tf|–|225|290|ps|20% to 80%, see Figure 2|
|||||**Jitter**|||
|**RMS Phase Jitter (random)**|T_phj|–|0.220|0.270|ps|f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdds.<br>Includes spurs. 7.0 x 5.0 mmpackage.|
|||–|0.225|0.280|ps|f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdds.<br>Includes spurs,3.2 x 2.5 mmpackage.|
|||–|0.1|–|ps|f = 156.25, IEEE802.3-2005 10GbE jitter mask integration bandwidth =<br>1.875 MHz to 20 MHz, Includes spurs, all Vdds|
|**RMS Period Jitter[1]**|T_jitt|–|1.0|1.6|ps|f = 100,156.25 or 212.5 MHz,VDD = 3.3V or 2.5V|



**Notes:** 

1. Measured according to JESD65B 

**Table 3. Electrical Characteristics – LVDS** 

|**Parameter**|**Symbol**|**Min.**|**Typ.**|**Max.**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|||||**Current Consumption**|||
|**Current Consumption**|Idd|–|–|79|mA|ExcludingLoad Termination Current,Vdd = 3.3V or 2.5V|
|**OE Disable Supply Current**|I_OE|–|–|58|mA|OE = Low|
|**Output Disable Leakage Current**|I_leak|–|0.15|–|µA|OE = Low|
|||||**Output Characteristics**|||
|**Differential Output Voltage **|VOD|250|–|455|mV|See Figure 4|
|**VOD Magnitude Change **|∆VOD|–|–|50|mV|See Figure 4|
|**Offset Voltage **|VOS|1.125|–|1.375|V|See Figure 4|
|**VOS Magnitude Change **|∆VOS|–|–|50|mV|See Figure 4|
|**Rise/Fall Time**|Tr, Tf|–|400|470|ps|Measured with 2 pF capacitive loading to GND, 20% to 80%, see<br>Figure 4|
||||||**Jitter**||
|**RMS Phase Jitter (random)**|T_phj|–|0.215|0.265|ps|f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdds.<br>Includes spurs. 7.0 x 5.0 mmpackage.|
||||0.235|0.275|ps|f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdds.<br>Includes spurs. 5.0 x 3.2 mmpackage. 0.275ps.|
|||–|0.1|–|ps|f = 156.25, IEEE802.3-2005 10GbE jitter mask integration bandwidth =<br>1.875 MHz to 20 MHz,Includes spurs,all Vdds|
|**RMS Period Jitter[2]**|T_jitt|–|1.0|1.6|ps|f = 100, 156.25 or 212.5 MHz, VDD = 3.3V or 2.5V|



## **Notes:** 

2. Measured according to JESD65B 

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**Table 4. Electrical Characteristics – HCSL** 

|**Parameter**<br>~~Cc~~|**Symbol**|**Min.**|**Typ.**|**Max.**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|**Current Consumption**<br>~~CcRs~~<br>~~rn~~<br>~~QO~~|||||||
|**Current Consumption**<br>~~CcRs~~<br>~~Rs~~|Idd<br>~~rn~~<br>~~rn~~|–<br>~~rs~~|–<br>~~QO~~<br>~~GQ~~|89<br>~~QO~~<br>~~GQ~~|mA<br>~~QO~~<br>~~GQ~~|ExcludingLoad Termination Current,Vdd = 3.3V or 2.5V|
|**OE Disable Supply Current**<br>~~Rs~~<br>~~Rs~~<br>~~Rs~~|I_OE<br>~~rn~~<br>~~rn~~<br>~~rs~~|–<br>~~rs~~<br>~~ne~~|–<br>~~QO~~<br>~~GQ~~<br>~~ne Qn~~|58<br>~~QO~~<br>~~GQ~~<br>~~Qn~~|mA<br>~~QO~~<br>~~GQ~~<br>~~Qn~~|OE = Low<br>~~Qn~~|
|**Output Disable Leakage Current**<br>~~Rs~~<br>~~Rs~~<br>~~Rs~~|I_leak<br>~~rn~~<br>~~rs~~<br>~~rn~~|–<br>~~rs ~~<br>~~ne~~<br>~~rs~~|0.15<br> ~~GQ~~<br>~~ne Qn~~<br>~~Df~~|–<br>~~GQ~~<br>~~Qn~~<br>~~Df~~|µA<br>~~GQ~~<br>~~Qn~~<br>~~Df~~|OE = Low<br>~~Qn~~|
|**Maximum Output Current**<br>~~Rs~~<br>~~Rs~~<br>~~Cn~~|I_driver<br>~~rs~~<br>~~rn~~|–<br>~~ne~~<br>~~rs~~|–<br>~~ne Qn~~<br>~~Df~~|35<br>~~Qn~~<br>~~Df~~|mA<br>~~Qn~~<br>~~Df~~|Maximum average current drawn from OUT+ or OUT-<br>~~Qn~~|
|**Output Characteristics**<br>~~Rs rn~~<br>~~rs~~<br>~~Df~~<br>~~Cn~~<br>~~eers~~<br>~~rsGr QsQQ~~|||||||
|**Output High Voltage **<br>~~Cn~~<br>~~ee~~<br>~~ee rs~~|VOH<br>~~rs~~<br>~~rs~~|0.60<br>~~rs~~<br>~~re~~|–<br>~~Gr Qs~~<br>~~Gr~~|0.90<br>~~Qs~~<br>~~QO GQ~~|V<br>~~QQ~~<br>~~GQ~~|See Figure 2<br>~~QQ~~<br>~~GQ~~|
|**Output Low Voltage **<br>~~ee ~~<br>~~ee rs~~<br>~~ee rs~~|VOL<br> ~~rs~~<br>~~rs~~<br>~~rs~~|-0.05<br>~~rs~~<br>~~re~~<br>~~re~~|–<br>~~Gr Qs~~<br>~~Gr~~<br>~~Gr~~|0.08<br>~~Qs~~<br>~~QO GQ~~<br>~~QO GQ~~|V<br>~~QQ~~<br>~~GQ~~<br>~~GQ~~|See Figure 2<br>~~QQ~~<br>~~GQ~~<br>~~GQ~~|
|**Output Differential Voltage Swing**<br>~~ee rs~~<br>~~ee rs~~|V_Swing<br>~~rs~~<br>~~rs~~|1.2<br>~~re~~<br>~~re~~|1.4<br>~~Gr ~~<br>~~Gr~~|1.80<br> ~~QO GQ~~<br>~~QO GQ~~|V<br>~~GQ~~<br>~~GQ~~|See Figure 3<br>~~GQ~~<br>~~GQ~~|
|**Rise/Fall Time**<br>~~ee rs~~<br>~~Cn~~|Tr, Tf<br>~~rs~~|–<br>~~re~~|360<br>~~Gr ~~|465<br> ~~QO GQ~~|ps<br>~~GQ~~|Measured with 2 pF capacitive loading to GND, 20% to 80%,<br>see Figure 2<br>~~GQ~~|
|**Jitter**<br>~~Cn~~|||||||
|**RMS Phase Jitter (random)**<br>~~Cn~~<br>~~Re~~|T_phj<br>~~rs~~|–|0.220|0.270|ps|f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdds,<br>Includes spurs,7.0 x 5.0 mmpackage.|
|||–|0.230|0.275|ps|f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdds,<br>Includes spurs,3.2 x 2.5 mmpackage.|
|||–<br>~~re~~|0.1<br>~~Gr~~|–<br>~~rs~~|ps<br>~~Gs~~|f = 156.25, IEEE802.3-2005 10GbE jitter mask integration bandwidth =<br>1.875 MHz to 20 MHz, Includes spurs, all Vdds<br>~~GR~~|
|**RMS Period Jitter[3]**<br>~~Re~~|T_jitt<br>~~rs~~|–<br>~~re~~|1.0<br>~~Gr~~|1.6<br>~~rs~~|ps<br>~~Gs~~|f = 100,156.25 or 212.5 MHz,VDD = 3.3V or 2.5V<br>~~GR~~|



## **Notes:** 

3. Measured according to JESD65B 

## **Table 5. Pin Description** 

|**Pin**|**Map**|**Functionality**|**Functionality**|
|---|---|---|---|
|1|OE/NC|Output Enable<br>(OE)|H[4]: specified frequency output<br>L: output is high impedance|
|||Non Connect<br>(NC)|H or L or Open: No effect on output frequency or other<br>device functions|
|2|NC|NA|No Connect; Leave it floating or connect to GND for better<br>heat dissipation|
|3|GND|Power|VDD Power SupplyGround|
|4|OUT+|Output|Oscillator output|
|5|OUT-|Output|Complementaryoscillator output|
|6|VDD|Power|Power supplyvoltage[5]|



## **Notes:** 

4. In OE mode, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. 

5. A capacitor of value 0.1 µF or higher between Vdd and GND is required. An additional 10 µF capacitor between Vdd and GND is required for the best phase jitter performance 

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## **Table 6. Absolute Maximum Ratings** 

Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings. 

|**Parameter**|**Min.**|**Max.**|**Unit**|
|---|---|---|---|
|VDD|-0.5|4.0|V|
|VIH||VDD + 0.3V|V|
|VIL|-0.3||V|
|Storage Temperature|-65|150|ºC|
|Maximum Junction Temperature||130|ºC|
|SolderingTemperature(follow standard Pb-free soldering guidelines)||260|ºC|



## **Table 7. Thermal Considerations[[6]]** 

||||
|---|---|---|
|**Package**|θ**JA, 4 Layer Board (°C/W)**|θ**JC, Bottom (°C/W)**|
||||
|**3225, 6-pin**|80|30|
|**7050, 6-pin**|52|19|



## **Notes:** 

6. Refer to JESD51 for θJA and θJC definitions, and reference layout used to determine the θJA and θJC values in the above table. 

## **Table 8. Maximum Operating Junction Temperature[[7]]** 

|||
|---|---|
|**Max Operating Temperature (ambient)**|**Maximum Operating Junction Temperature**|
|||
|70°C|95°C|
|85°C|110°C|



## **Notes:** 

7. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature. 

## **Table 9. Environmental Compliance** 

|**Parameter**|**Test Conditions**|**Value**|**Unit**|
|---|---|---|---|
|Mechanical Shock Resistance|MIL-STD-883F, Method 2002|10,000|_G_|
|Mechanical Vibration Resistance|MIL-STD-883F, Method 2007|70|_G_|
|Soldering Temperature (follow standard Pb free<br>soldering guidelines)|MIL-STD-883F, Method 2003|260|°C|
|Moisture Sensitivity Level|MSL1 @ 260°C|||
|Electrostatic Discharge (HBM)|HBM, JESD22-A114|2,000|V|
|Charge-Device Model ESD Protection|JESD220C101|750|V|
|Latch-up Tolerance|JESD78 Compliant|||



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## **Waveform Diagrams** 

**Figure 2. LVPECL/HCSL Voltage Levels per Differential Pin (OUT+/OUT-)** 

**Figure 3. LVPECL/HCSL Voltage Levels across Differential Pair** 

**Figure 4. LVDS Voltage Levels per Differential Pin (OUT+/OUT-)** 

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## **Termination Diagrams** 

## **LVPECL:** 

**Figure 5: LVPECL with AC-coupled termination** 

**==> picture [268 x 128] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>Thevenin-equivalent<br>Termination network<br>LVPECL R1 R1<br>OUT+ Zo = 50Ω D+<br>OUT- > TT Zo = 50Ω T D-<br>VDD R1 R2 R2 R2<br>3.3 V 127 Ω 82.5 Ω<br>J) Ea<br>2.5 V 250 Ω 62.5 Ω<br>**----- End of picture text -----**<br>


**Figure 6: LVPECL DC-coupled load termination with Thevenin equivalent network** 

**==> picture [276 x 128] intentionally omitted <==**

**----- Start of picture text -----**<br>
Y-Bias Termination<br>network<br>LVPECL<br>OUT+ Zo = 50Ω D+<br>OUT- > TTWo) Zo = 50Ω |. tsti—izY D-<br>R1 R2<br>VDD R1 R2 R3<br>3.3 V 50 Ω 50 Ω 50 Ω C1 R3<br>0.1µF<br>2.5 V 50 Ω 50 Ω 18 Ω<br>**----- End of picture text -----**<br>


**Figure 7: LVPECL with Y-Bias termination** 

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## **Termination Diagrams (Continued)** 

**==> picture [394 x 144] intentionally omitted <==**

**----- Start of picture text -----**<br>
Shunt Bias Termination<br>LVPECL network<br>OUT+ Zo = 50Ω D+<br>OUT- Zo = 50Ω D-<br>50 Ω 50 Ω<br>VT=VDD-2V<br>**----- End of picture text -----**<br>


**Figure 8: LVPECL with DC-coupled parallel shunt load termination** 

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## **Termination Diagrams (Continued)** 

## **LVDS:** 

**==> picture [272 x 41] intentionally omitted <==**

**----- Start of picture text -----**<br>
LVDS<br>OUT+ Zo = 50Ω OUT+<br>100 Ω<br>OUT- Zo = 50Ω OUT-<br>**----- End of picture text -----**<br>


**Figure 9: LVDS single DC termination at the load** 

**Figure 10: LVDS double AC termination with capacitor close to the load** 

**Figure 11: LVDS double DC termination** 

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## **Termination Diagrams (Continued)** 

## **HCSL:** 

**==> picture [344 x 116] intentionally omitted <==**

**----- Start of picture text -----**<br>
R1<br>OUT+ Zo = 50Ω D+<br>OUT- Zo = 50Ω D-<br>R2<br>50Ω 50Ω<br>R1 = R2 = 33 Ω<br>**----- End of picture text -----**<br>


**Figure 12: HCSL interface termination** 

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## **Dimensions and Patterns** 

**==> picture [471 x 228] intentionally omitted <==**

**----- Start of picture text -----**<br>
Package Size – Dimensions (Unit: mm) [[8]] Recommended Land Pattern (Unit: mm) [[9]]<br>3.2 x 2.5 x 0.75 mm  3.2 x 2.5 x 0.75 mm<br>Dimension Table 2.2<br>sj A ee ee<br>hale = [roratucrness [a __| aco | aso | asco |<br>[|_|<br>- ~ ae [a [20 |<br>: “ [_& | s200 | 3200 | 3200 |<br>. [teaoerch |e | ttoesc | = a:<br>a) [ fw. 0 6 5 - 1.05 o<br>= LJ CJ 0)<br>6L QFN Package Outline<br>Seuied3.2 x 2.5x0.75mm SiTime.<br>7.0 x 5.0 x 0.90 mm [[10]] 7.0 x 5.0 x 0.90 mm [[10]]<br>**----- End of picture text -----**<br>


## **Notes:** 

8. Top Marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the assembly location of the device. 

9. A capacitor of value 0.1 µF or higher between Vdd and GND is required. An additional 10 µF capacitor between Vdd and GND is required for the best phase jitter performance 

10. The center pad has no electrical function.  Soldering down the center pad to the GND is recommended for best thermal dissipation, but is optional. 

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## **Ordering Information** 

**Notes:** 

11. Contact SiTime for higher temperature range options 

12. Contact SiTime for 5.0 x 3.2 mm package 

13. Contact SiTime for ± 10 ppm option 

14. Bulk is available for sampling only 

## **Table 10. Supported Frequencies** 

|25.000000  MHz|30.720000 MHz|50.000000  MHz|53.125000  MHz|61.440000  MHz|62.500000 MHz|74.175824  MHz|74.250000  MHz|
|---|---|---|---|---|---|---|---|
|75.000000  MHz|77.760000  MHz|98.304000  MHz|100.000000 MHz|106.250000 MHz|122.880000 MHz|125.000000 MHz|133.333333 MHz|
|148.351648 MHz|150.000000 MHz|153.600000 MHz|155.520000 MHz|156.250000 MHz|159.375000 MHz|160.000000 MHz|161.132813 MHz|
|166.666666 MHz|168.040678 MHz|200.000000  MHz|212.500000 MHz|250.000000 MHz|300.000000 MHz|322.265625 MHz|325.000000 MHz|



## **Table 11. Ordering Codes for Supported Tape & Reel Packing Method** 

|**Device Size**<br>**(mm x mm)**|**8 mm T&R**<br>**(3ku)**|**8 mm T&R**<br>**(1ku)**|**12 mm T&R**<br>**(3ku)**|**12 mm T&R**<br>**(1ku)**|**16 mm T&R**<br>**(3ku)**|**16 mm T&R**<br>**(1ku)**|
|---|---|---|---|---|---|---|
|7.0 x 5.0|—|—|—|—|T|Y|
|3.2 x 2.5|D|E|T|Y|—|—|



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## **Table 12. Revision History** 

|**Revision**|**Release Date**|**Change Summary**|
|---|---|---|
|1.0|09/06/2017|Final release|



## **SiTime Corporation** , 5451 Patrick Henry Drive, Santa Clara, CA 95054, USA | **Phone:** +1-408-328-4400 | **Fax:** +1-408-328-4439 

© SiTime Corporation 2017. The information contained herein is subject to change at any time without notice. SiTime assumes no responsibility or liability for any loss, damage or defect of a Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect or accident, (iii) unauthorized modification or repairs which have been soldered or altered during assembly and are not capable of being tested by SiTime under its normal test conditions, or (iv) improper installation, storage, handling, warehousing or transportation, or (v) being subjected to unusual physical, thermal, or electrical stress. 

**Disclaimer:** SiTime makes no warranty of any kind, express or implied, with regard to this material, and specifically disclaims any and all express or implied warranties, either in fact or by operation of law, statutory or otherwise, including the implied warranties of merchantability and fitness for use or a particular purpose, and any implied warranty arising from course of dealing or usage of trade, as well as any common-law duties relating to accuracy or lack of negligence, with respect to this material, any SiTime product and any product documentation. Products sold by SiTime are not suitable or intended to be used in a life support application or component, to operate nuclear facilities, or in other mission critical applications where human life may be involved or at stake. All sales are made conditioned upon compliance with the critical uses policy set forth below. 

## CRITICAL USE EXCLUSION POLICY 

BUYER AGREES NOT TO USE SITIME'S PRODUCTS FOR ANY APPLICATION OR IN ANY COMPONENTS USED IN LIFE SUPPORT DEVICES OR TO OPERATE NUCLEAR FACILITIES OR FOR USE IN OTHER MISSION-CRITICAL APPLICATIONS OR COMPONENTS WHERE HUMAN LIFE OR PROPERTY MAY BE AT STAKE. 

SiTime owns all rights, title and interest to the intellectual property related to SiTime's products, including any software, firmware, copyright, patent, or trademark. The sale of SiTime products does not convey or imply any license under patent or other rights. SiTime retains the copyright and trademark rights in all documents, catalogs and plans supplied pursuant to or ancillary to the sale of products or services by SiTime. Unless otherwise agreed to in writing by SiTime, any reproduction, modification, translation, compilation, or representation of this material shall be strictly prohibited. 

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