# Power MOSFET, N Channel, 500 V, 36 A, 0.13 ohm, Super-247, Through Hole

![Product image](https://novapart.co/image/farnell:3650271/)

**URL**: https://novapart.co/products/SIHS36N50D-GE3/power-mosfet-n-channel-500-v-36-a-013-ohm-super
**SKU**: SIHS36N50D-GE3
**Manufacturer**: VISHAY
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €3.1800
**Stock**: 1000+
**Lead Time**: 2 days (indicative)

## Description

Available until stocks are exhausted Alternative available

## Specifications

| Parameter | Value |
|---|---|
| Svhc | To Be Advised |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | D |
| Qualification | - |
| Power Dissipation | 446W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | Super-247 |
| Drain Source Voltage Vds | 500V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 36A |
| Drain Source On State Resistance | 0.13ohm |
| Gate Source Threshold Voltage Max | 5V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3650271/)

**SiHS36N50D** 

Vishay Siliconix 

www.vishay.com 

## **D Series Power MOSFET** 

## **FEATURES** 

- Optimal design 

**==> picture [189 x 111] intentionally omitted <==**

**----- Start of picture text -----**<br>
Super-247 D<br>S<br>D G<br>G<br>S<br>N-Channel MOSFET<br>**----- End of picture text -----**<br>


|**PRODUCT SUMMARY**|**PRODUCT SUMMARY**|**PRODUCT SUMMARY**|
|---|---|---|
|VDS(V) at TJmax.|550||
|RDS(on)max. at 25 °C (Ω)|VGS= 10 V|0.130|
|Qgmax. (nC)|125||
|Qgs(nC)|23||
|Qgd(nC)|37||
|Configuration|Single||



   - Low area specific on-resistance 

   - Low input capacitance (Ciss) 

   - Reduced capacitive switching losses 

   - High body diode ruggedness 

   - Avalanche energy rated (UIS) 

- Optimal efficiency and operation 

   - Low cost 

   - Simple gate drive circuitry 

   - Low figure-of-merit (FOM): Ron x Qg 

   - Fast switching 

- Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 

## **APPLICATIONS** 

- Consumer electronics 

   - Displays (LCD or Plasma TV 

- Server and telecom power supplies 

   - SMPS 

- Industrial 

   - Welding, induction heating, motor drives 

- Battery chargers 

## **ORDERING INFORMATION** 

|**ABSOLUTE MAXIMUM RATINGS**(TC= 25 °C, unless otherwise noted)<br>~~Cee~~|**ABSOLUTE MAXIMUM RATINGS**(TC= 25 °C, unless otherwise noted)<br>~~Cee~~|**ABSOLUTE MAXIMUM RATINGS**(TC= 25 °C, unless otherwise noted)<br>~~Cee~~|**ABSOLUTE MAXIMUM RATINGS**(TC= 25 °C, unless otherwise noted)<br>~~Cee~~|**ABSOLUTE MAXIMUM RATINGS**(TC= 25 °C, unless otherwise noted)<br>~~Cee~~|**ABSOLUTE MAXIMUM RATINGS**(TC= 25 °C, unless otherwise noted)<br>~~Cee~~|
|---|---|---|---|---|---|
|**PARAMETER**<br>~~eG~~<br>~~—————~~|||**SYMBOL**<br>~~eG~~<br>~~———~~|**LIMIT**<br>~~eG~~<br>~~———~~|**UNIT**<br>~~eG~~|
|Drain-source voltage<br>~~—————~~|||VDS<br>~~———~~|500<br>~~———~~|V|
|Gate-source voltage<br>~~—————~~<br>~~ee~~|||VGS<br>~~———~~<br>~~ee~~|± 30<br>~~———~~<br>~~ee~~||
|Gate-source voltage AC (f > 1 Hz)<br>~~—————~~<br>~~ee~~<br>~~po~~||||30<br>~~———~~<br>~~ee~~||
|Continuous drain current (TJ= 150 °C)<br>~~—————~~<br>~~po~~|VGSat 10 V<br>~~———~~|TC= 25 °C<br>~~———~~|ID<br>~~———~~|36<br>~~———~~|A|
|||TC= 100 °C||23||
|Pulsed drain currenta<br>~~po~~<br>~~ees~~|||IDM<br>~~ees~~|112<br>~~ees~~||
|Linear derating factor<br>~~po~~<br>~~ees~~<br>~~ees~~<br>|||~~ees~~<br>~~ees~~<br>|3.6<br>~~ees~~<br>~~ees~~<br>|W/°C<br>~~ees~~<br>~~J~~|
|Single pulse avalanche energyb<br>~~ees~~<br>~~ees~~|||EAS<br>~~ees~~<br>~~ees~~|332<br>~~ees~~<br>~~ees~~|mJ<br>~~ees~~<br>~~eesJ~~|
|Maximum power dissipation<br><br>~~eee~~|||PD<br><br>~~eee~~|446<br><br>~~eee~~|W<br>~~J~~<br>~~eee~~|
|Operating junction and storage temperature range<br>~~a~~|||TJ, Tstg<br>~~a~~|- 55 to + 150<br>~~a~~<br>~~ee~~|°C<br>~~a~~<br>~~ee~~|
|Drain-source voltage slope<br>~~He~~|TJ= 125 °C<br>~~He~~||dV/dt<br>~~He~~|24<br>~~He~~<br>~~ee~~|V/ns<br>~~He~~<br>~~ee~~|
|Reverse diode dV/dtd<br>~~He~~||||0.1<br>~~He~~<br>~~ee~~||
|Soldering recommendations (peak temperature)<br>~~He~~<br>~~a~~|for 10 s<br>~~He~~<br>~~a~~||~~He~~<br>~~a~~|300c<br>~~He~~<br>~~ee~~<br>~~a~~|°C<br>~~He~~<br>~~ee~~<br>~~a~~|



- a. Repetitive rating; pulse width limited by maximum junction temperature 

- b. VDD = 50 V, starting TJ = 25 °C, L = 2.3 mH, Rg = 25 Ω, IAS = 17 A 

- c. 1.6 mm from case 

- d. ISD ≤ ID, starting TJ = 25 °C 

S21-0019-Rev. B, 18-Jan-2021 

Document Number: 91514 

**1** 

For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**SiHS36N50D** 

www.vishay.com 

Vishay Siliconix 

## **THERMAL RESISTANCE RATINGS** 

|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|
|---|---|---|---|---|
|**PARAMETER**|**SYMBOL**|**TYP.**|**MAX.**|**UNIT**|
|Maximum junction-to-ambient|RthJA|-|40|°C/W|
|Maximum junction-to-case (drain)|RthJC|-|0.28||



|**SPECIFICATIONS**(TJ= 25 °C,unless otherwise noted)|**SPECIFICATIONS**(TJ= 25 °C,unless otherwise noted)|**SPECIFICATIONS**(TJ= 25 °C,unless otherwise noted)|**SPECIFICATIONS**(TJ= 25 °C,unless otherwise noted)|||||
|---|---|---|---|---|---|---|---|
|**PARAMETER**|**SYMBOL**|**TEST CONDITIONS**||**MIN.**|**TYP.**|**MAX.**|**UNIT**|
|**Static**||||||||
|Drain-source breakdown voltage|VDS|VGS= 0 V, ID= 250 μA||500|-|-|V|
|VDStemperature coefficient|ΔVDS/TJ|Reference to 25 °C, ID= 250 μA||-|0.52|-|V/°C|
|Gate threshold voltage (N)|VGS(th)|VDS= VGS, ID= 250 μA||3.0|-|5.0|V|
|Gate-source leakage|IGSS|VGS= ± 30 V||-|-|± 100|nA|
|Zero gate voltage drain current|IDSS|VDS= 500 V, VGS= 0 V||-|-|1|μA|
|||VDS= 400 V, VGS= 0 V, TJ= 125 °C||-|-|10||
|Drain-source on-state resistance|RDS(on)|VGS= 10 V|ID= 18 A|-|0.105|0.130|Ω|
|Forward transconductancea|gfs|VDS= 50 V, ID= 18 A||-|12.8|-|S|
|**Dynamic**||||||||
|Input capacitance|Ciss|VGS= 0 V,<br>VDS= 100 V,<br>f = 1 MHz||-|3233|-|pF|
|Output capacitance|Coss|||-|285|-||
|Reverse transfer capacitance|Crss|||-|25|-||
|Effective output capacitance, energy<br>relateda|Co(er)|VGS= 0 V, VDS= 0 V to 400 V||-|240|-||
|Effective output capacitance, time<br>relatedb|Co(tr)|||-|352|-||
|Totalgate charge|Qg|VGS= 10 V|ID= 18 A, VDS= 400 V|-|83|125|nC|
|Gate-source charge|Qgs|||-|23|-||
|Gate-drain charge|Qgd|||-|37|-||
|Turn-on delay time|td(on)|VDD= 400 V, ID= 18 A,<br>VGS= 10 V, Rg= 9.1Ω||-|33|66|ns|
|Rise time|tr|||-|89|134||
|Turn-off delay time|td(off)|||-|79|119||
|Fall time|tf|||-|68|102||
|Gate input resistance|Rg|f = 1 MHz, open drain||-|1.8|-|Ω|
|**Drain-source body diode characteristics**||||||||
|Continuous source-drain diode current|IS|MOSFET symbol<br>showing the<br>integral reverse<br>p - n junction diode<br>S<br>D<br>G||-|-|36|A|
|Pulsed diode forward current|ISM|||-|-|144||
|Diode forward voltage|VSD|TJ= 25 °C, IS= 18 A, VGS= 0 V||-|-|1.2|V|
|Reverse recovery time|trr|TJ= 25 °C, IF= IS= 18 A,<br>dI/dt = 100 A/μs, VR= 20 V||-|490|-|ns|
|Reverse recovery charge|Qrr|||-|8.2|-|μC|
|Reverse recovery current|IRRM|||-|31|-|A|



## **Notes** 

a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS 

b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS 

S21-0019-Rev. B, 18-Jan-2021 

Document Number: 91514 

**2** 

For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**SiHS36N50D** 

Vishay Siliconix 

**==> picture [77 x 10] intentionally omitted <==**

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www.vishay.com<br>**----- End of picture text -----**<br>


## **TYPICAL CHARACTERISTICS** (25 °C, unless otherwise noted) 

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120 TOP        15 V14 V TJ = 25 °C<br>13 V<br>12 V<br>11 V<br>10 V<br>9 V<br>90 8 V<br>7 V<br>6 V<br>BOTTOM   5 V<br>60<br>30<br>0<br>0  5  10  15  20  25  30<br>VDS, Drain-to-Source Voltage (V)<br> Fig. 1 - Typical Output Characteristics<br>80<br>TOP        15 V14 V TJ = 150 °C<br>13 V<br>12 V<br>11 V<br>60  10 V<br>9 V<br>8 V<br>7 V<br>6 V<br>BOTTOM    5 V<br>40<br>20<br>0<br>0  5  10  15  20  25  30<br>VDS, Drain-to-Source Voltage (V)<br>, Drain-to-Source Current (A)<br>ID<br>, Drain-to-Source Current (A)<br>ID<br>**----- End of picture text -----**<br>


**Fig. 2 - Typical Output Characteristics** 

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**----- Start of picture text -----**<br>
3<br>ID = 18 A<br>2.5<br>2<br>1.5<br>VGS = 10 V<br>1<br>0.5<br>0<br>- 60 - 40 - 20 0 20 40 60 80 100 120 140 160<br>TJ, Junction Temperature (°C)<br>, Drain-to-Source<br>DS(on)<br>R<br>On Resistance (Normalized)<br>**----- End of picture text -----**<br>


**Fig. 4 - Normalized On-Resistance vs. Temperature** 

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**----- Start of picture text -----**<br>
10 000<br>C iss V GS = 0 V, f = 1 MHz<br>1000 Ciss = Cgs + Cgd, Cds Shorted<br>Crss = Cgd<br>Coss = Cds + Cgd<br>100 Coss<br>10 C rss<br>1<br>0 100 200 300 400 500<br>VDS, Drain-to-Source Voltage (V)<br>Capacitance (pF)<br>**----- End of picture text -----**<br>


**Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage** 

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120<br>TJ = 25 °C<br>90<br>60  T J  = 150 °C<br>30<br>0<br>0  5  10  15  20  25<br>VGS, Gate-to-Source Voltage (V)<br>, Drain-to-Source Current (A)<br>ID<br>**----- End of picture text -----**<br>


**Fig. 3 - Typical Transfer Characteristics** 

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**----- Start of picture text -----**<br>
24<br>VD S  = 400 V<br>V DS  = 250 V<br>20 VD S  = 100 V<br>16<br>12<br>8<br>4<br>  0<br>0  30  60  90  120  150<br>Qg, Total Gate Charge (nC)<br>, Gate-to-Source Voltage (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


**Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage** 

S21-0019-Rev. B, 18-Jan-2021 

Document Number: 91514 

**3** For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**SiHS36N50D** 

Vishay Siliconix 

## www.vishay.com 

**==> picture [199 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
1000<br>100<br>T J  = 150 °C<br>10<br>T J  = 25 °C<br>1<br>V GS  = 0 V<br>0.1<br>0.2 0.4 0.6 0.8 1 1.2 1.4 1.6<br>VSD, Source-Drain Voltage (V)<br>, Reverse Drain Current (A)<br>ISD<br>**----- End of picture text -----**<br>


**Fig. 7 - Typical Source-Drain Diode Forward Voltage** 

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**----- Start of picture text -----**<br>
40<br>30<br>20<br>10<br>0<br>25           50            75          100          125          150<br>TJ, Case Temperature (°C)<br>, Drain Current (A)<br>ID<br>**----- End of picture text -----**<br>


**Fig. 9 - Maximum Drain Current vs. Case Temperature** 

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**----- Start of picture text -----**<br>
1000<br>Operation in this Area IDM = Limited<br>Limited by R DS(on)<br>100<br>10 Limited by RDS(on)* 100  μs<br>1 ms<br>1<br>TC = 25 °C 10 m s<br>TJ = 150  ° C<br>Single Pulse BVDSS Limited<br>0.1<br>1  10  100 1000<br>VDS, Drain-to-Source Voltage (V)<br>* VGS > minimum VGS at which RDS(on) is s<br>, Drain Current (A)<br>ID<br>**----- End of picture text -----**<br>


**Fig. 8 - Maximum Safe Operating Area** 

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**----- Start of picture text -----**<br>
 -60 - 40 - 20 0 20 40 60 80 100 120 140 160<br>TJ, Junction Temperature (°C)<br>625<br>600<br>575<br>550<br>525<br>500<br>475<br>, Drain-to-Source<br>DS<br>V Breakdown Voltage (V)<br>**----- End of picture text -----**<br>


**Fig. 10 - Temperature vs. Drain-to-Source Voltage** 

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1<br>Duty Cycle = 0.5<br>0.2<br>0.1<br>0.1<br>0.05<br>Single Pulse<br>0.02<br>0.01<br>0.0001 0.001 0.01 0.1 1<br>Pulse Time (s)<br>Thermal Impedance<br>Normalized Effective Transient<br>**----- End of picture text -----**<br>


**Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case** 

S21-0019-Rev. B, 18-Jan-2021 

Document Number: 91514 

**4** 

For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**SiHS36N50D** 

Vishay Siliconix 

www.vishay.com 

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**----- Start of picture text -----**<br>
RD<br>VDS<br>VGS<br>D.U.T.<br>RG +<br>- VDD<br>10 V<br>Pulse width ≤ 1 μs<br>Duty factor ≤ 0.1 %<br> Fig. 12 - Switching Time Test Circuit<br>VDS<br>90 %<br>10 %<br>VGS<br>td(on) tr td(off) tf<br>**----- End of picture text -----**<br>


**Fig. 13 - Switching Time Waveforms** 

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**----- Start of picture text -----**<br>
L<br>VDS<br>Vary tp to obtain<br>required IAS<br>RG D.U.T. +<br>- [V][ DD]<br>IAS<br>10 V<br>tp 0.01 Ω<br>**----- End of picture text -----**<br>


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QG<br>10 V<br>QGS QGD<br>VG<br>Charge<br> Fig. 16 -  Basic Gate Charge Waveform<br>Current regulator<br>Same type as D.U.T.<br>50 kΩ<br>12 V 0.2 μF<br>0.3 μF<br>+<br>D.U.T. - VDS<br>VGS<br>3 mA<br>IG ID<br>Current sampling resistors<br>**----- End of picture text -----**<br>


**Fig. 16 -  Basic Gate Charge Waveform** 

**Fig. 17 - Gate Charge Test Circuit** 

**Fig. 14 - Unclamped Inductive Test Circuit** 

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**----- Start of picture text -----**<br>
VDS<br>t<br>p<br>VDD<br>VDS<br>IAS<br>**----- End of picture text -----**<br>


**Fig. 15 - Unclamped Inductive Waveforms** 

S21-0019-Rev. B, 18-Jan-2021 

Document Number: 91514 

**5** For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**SiHS36N50D** 

Vishay Siliconix 

**==> picture [77 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
www.vishay.com<br>**----- End of picture text -----**<br>


**==> picture [284 x 492] intentionally omitted <==**

**----- Start of picture text -----**<br>
Peak Diode Recovery dV/dt Test Circuit<br>+ Circuit layout considerations<br>D.U.T.<br>•  Low stray inductance<br>•  Ground plane<br>•  Low leakage inductance<br>  current transformer<br>-<br>+<br>- - +<br>Rg •  dV/dt controlled by Rg +<br>••   Driver same type as D.U.T. ISD controlled by duty factor “D” - VDD<br>• D.U.T. - device under test<br>Driver gate drive<br>Period D = P.W.<br>P.W. Period<br>VGS = 10 V [a]<br>D.U.T. lSD waveform<br>Reverse<br>recovery Body diode forward<br>current current dI/dt<br>D.U.T. VDS waveform Diode recovery<br>dV/dt<br>VDD<br>Re-applied<br>voltage<br>Body diode forward drop<br>Inductor current<br>Ripple ≤ 5 % ISD<br>Note<br>a. VGS = 5 V for logic level devices<br>**----- End of picture text -----**<br>


**Fig. 18 - For N-Channel** 

_Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91514._ 

Document Number: 91514 

S21-0019-Rev. B, 18-Jan-2021 

**6** 

For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**Package Information** 

Vishay Siliconix 

www.vishay.com 

## **TO-274AA (High Voltage)** 

## **VERSION 1: FACILITY CODE = Y** 

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A<br>B E A<br>D2<br>E4 A1 E1<br>R<br>D1<br>D<br>L1<br>L Detail “A”<br>C<br>e b<br>A2<br>0.10 (0.25) M B A M<br>b2 b4<br>Lead Tip<br>Detail “A”<br>10°<br>5°<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
b2 b4<br>Detail “A”<br>Scale: 2:1<br>**----- End of picture text -----**<br>


||**MILLIMETERS**|**MILLIMETERS**|**INCHES**|**INCHES**|
|---|---|---|---|---|
|**DIM.**<br>**M**|**IN.**|**MAX.**|**MIN.**|**MAX.**|
|A<br>4|.70|5.30|0.185|0.209|
|A1<br>1|.50|2.50|0.059|0.098|
|A2<br>2|.25|2.65|0.089|0.104|
|b<br>1|.30|1.60|0.051|0.063|
|b2<br>1|.80|2.20|0.071|0.087|
|b4<br>3|.00|3.25|0.118|0.128|
|c(1)<br>0|.38|0.89|0.015|0.035|
|D<br>1|9.80|20.80|0.780|0.819|



||**MILLIMETERS**|**MILLIMETERS**|**INCHES**|**INCHES**|
|---|---|---|---|---|
|**DIM.**|**MIN.**|**MAX.**|**MIN.**|**MAX.**|
|D1|15.50|16.10|0.610|0.634|
|D2|0.70|1.30|0.028|0.051|
|E|15.10|16.10|0.594|0.634|
|E1|13.30|13.90|0.524|0.547|
|e|5.45 BSC||0.215 BSC||
|L|13.70|14.70|0.539|0.579|
|L1|1.00|1.60|0.039|0.063|
|R|2.00|3.00|0.079|0.118|



## **Notes** 

- Dimensioning and tolerancing per ASME Y14.5M-1994 

- Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outer extremes of the plastic body 

- Outline conforms to JEDEC[®] outline to TO-274AA 

- (1) Dimension measured at tip of lead 

Revision: 19-Oct-2020 

Document Number: 91365 

**1** 

For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**Package Information** 

**==> picture [77 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
www.vishay.com<br>**----- End of picture text -----**<br>


## Vishay Siliconix 

## **VERSION 2: FACILITY CODE = N** 

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H H<br>b3<br>b1<br>0.25 M B A M<br>b’, b2, b4<br>Base metal<br>b, b1, b3<br>Plating<br>A A B<br>E<br>E3 A2<br>F F<br>C<br>G G<br>A1<br>e<br>3 x b<br>C E4<br>E1<br>D2<br>D1<br>D<br>L1<br>L<br>C C’<br>Q<br>E2<br>**----- End of picture text -----**<br>


SECTION "F-F", "G-G" AND "H-H" SCALE: NONE 

|||||SCALE: NON|E|E|
|---|---|---|---|---|---|---|
||**MILLIMETERS**||||**MILLIMETERS**||
|**DIM.**|**MIN.**|**MAX.**||**DIM.**|**MIN.**|**MAX.**|
|A|4.83|5.21||D1|16.25|17.65|
|A1|2.29|2.54||D2|0.50|0.80|
|A2|1.91|2.16||E|15.75|16.13|
|b’|1.07|1.28||E1|13.10|14.15|
|b|1.07|1.33||E2|3.68|5.10|
|b1|1.91|2.41||E3|1.00|1.90|
|b2|1.91|2.16||E4|12.38|13.43|
|b3|2.87|3.38||e|5.44 BSC||
|b4|2.87|3.13||N|3||
|c’|0.55|0.65||L|19.81|20.32|
|c|0.55|0.68||L1|3.70|4.00|
|D|20.80|21.10||Q|5.49|6.00|
|ECN: E20-0538-Rev. C, 19-Oct-2020<br>DWG: 5975|||||||



ECN: E20-0538-Rev. C, 19-Oct-2020 DWG: 5975 

## **Notes** 

- Dimensioning and tolerancing per ASME Y14.5M-1994 

- Outline conforms to JEDEC[®] outline to TO-274AD 

- Dimensions are measured in mm, angles are in degree 

- Metal surfaces are tin plated, except area of cut 

Revision: 19-Oct-2020 

Document Number: 91365 

**2** 

For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

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Revision: 01-Jan-2021 

Document Number: 91000 

**1** 



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---

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