# Power MOSFET, N Channel, 600 V, 35 A, 0.08 ohm, TO-247AC, Through Hole ![Product image](https://novapart.co/image/farnell:3677859/) **URL**: https://novapart.co/products/SIHG080N60E-GE3/power-mosfet-n-channel-600-v-35-a-008-ohm-to-247ac **SKU**: SIHG080N60E-GE3 **Manufacturer**: VISHAY **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €2.4500 **Stock**: 200+ **Lead Time**: 36 days (indicative) ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | Lead (07-Nov-2024) | | No. Of Pins | 3Pins | | Channel Type | N Channel | | Product Range | E | | Qualification | - | | Power Dissipation | 227W | | Transistor Mounting | Through Hole | | Rds(On) Test Voltage | 10V | | Transistor Case Style | TO-247AC | | Drain Source Voltage Vds | 600V | | Operating Temperature Max | 150°C | | Continuous Drain Current Id | 35A | | Drain Source On State Resistance | 0.08ohm | | Gate Source Threshold Voltage Max | 5V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:3677859/) **SiHG080N60E** Vishay Siliconix www.vishay.com ## **E Series Power MOSFET** **==> picture [40 x 7] intentionally omitted <==** **----- Start of picture text -----**
TO-247AC
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D
G
S
D
G S
N-Channel MOSFET
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## **FEATURES** - 4[th] generation E series technology - Low figure-of-merit (FOM) Ron x Qg - Low effective capacitance (Co(er)) - Reduced switching and conduction losses - Avalanche energy rated (UIS) - Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 ## **APPLICATIONS** - Server and telecom power supplies |**PRODUCT SUMMARY**|**PRODUCT SUMMARY**|**PRODUCT SUMMARY**| |---|---|---| |VDS(V) at TJmax.|650|| |RDS(on)typ. (Ω) at 25 °C|VGS= 10 V|0.070| |Qgmax. (nC)|63|| |Qgs(nC)|19|| |Qgd(nC)|10|| |Configuration|Single|| - Switch mode power supplies (SMPS) - Power factor correction power supplies (PFC) - Lighting - High-intensity discharge (HID) - Fluorescent ballast lighting - Industrial - Welding - Induction heating - Motor drives - Battery chargers - Solar (PV inverters) ## **ORDERING INFORMATION** Package TO-247AC Lead (Pb)-free and halogen-free SIHG080N60E-GE3 ~~|~~ **ABSOLUTE MAXIMUM RATINGS** (TC = 25 °C, unless otherwise noted) ~~a~~ **PARAMETER SYMBOL LIMIT UNIT** Drain-source voltage VDS 600 V ~~ee~~ Gate-source voltage VGS ± 30 TC = 25 °C 35 Continuous drain current (TJ = 150 °C) VGS at 10 V ID TC = 100 °C 22 A ~~eea~~ Pulsed drain current[ a] ~~ee~~ IDM 96 ~~ee a~~ Linear derating factor 1.8 W/°C ~~a~~ Single pulse avalanche energy[ b] EAS 226 mJ ~~a~~ Maximum power dissipation PD 227 W ~~a~~ Operating junction and storage temperature range TJ, Tstg -55 to +150 °C Drain-source voltage slope TJ = 125 °C 100 dv/dt V/ns Reverse diode dv/dt[d] 10 ~~a~~ Soldering recommendations (peak temperature)[ c] For 10 s 260 °C **Notes** a. Repetitive rating; pulse width limited by maximum junction temperature b. VDD = 120 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 Ω, IAS = 4.0 A c. 1.6 mm from case d. ISD ≤ ID, di/dt = 100 A/μs, starting TJ = 25 °C S21-0062-Rev. A, 01-Feb-2021 Document Number: 92375 **1** For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 **SiHG080N60E** Vishay Siliconix www.vishay.com ## **THERMAL RESISTANCE RATINGS** |**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**| |---|---|---|---|---| |**PARAMETER**|**SYMBOL**|**TYP.**|**MAX.**|**UNIT**| |Maximum junction-to-ambient|RthJA|-|40|°C/W| |Maximum junction-to-case (drain)|RthJC|-|0.55|| |**SPECIFICATIONS**(TJ= 25 °C,unless otherwise noted)|**SPECIFICATIONS**(TJ= 25 °C,unless otherwise noted)|**SPECIFICATIONS**(TJ= 25 °C,unless otherwise noted)|**SPECIFICATIONS**(TJ= 25 °C,unless otherwise noted)||||| |---|---|---|---|---|---|---|---| |**PARAMETER**|**SYMBOL**|**TEST CONDITIONS**||**MIN.**|**TYP.**|**MAX.**|**UNIT**| |**Static**|||||||| |Drain-source breakdown voltage|VDS|VGS= 0 V, ID= 250 μA||600|-|-|V| |VDStemperature coefficient|ΔVDS/TJ|Reference to 25 °C, ID= 1 mA||-|0.64|-|V/°C| |Gate-source threshold voltage (N)|VGS(th)|VDS= VGS, ID= 250 μA||3.0|-|5.0|V| |Gate-source leakage|IGSS|VGS= ± 20 V||-|-|± 100|nA| |||VGS= ± 30 V||-|-|± 1|μA| |Zero gate voltage drain current|IDSS|VDS= 600 V, VGS= 0 V||-|-|1|μA| |||VDS= 480 V, VGS= 0 V, TJ= 125 °C||-|-|10|| |Drain-source on-state resistance|RDS(on)|VGS= 10 V|ID= 17 A|-|0.070|0.080|Ω| |Forward transconductancea|gfs|VDS= 20 V, ID= 17 A||-|4.6|-|S| |**Dynamic**|||||||| |Input capacitance|Ciss|VGS= 0 V,
VDS= 100 V,
f = 1 MHz||-|2557|-|pF| |Output capacitance|Coss|||-|105|-|| |Reverse transfer capacitance|Crss|||-|6|-|| |Effective output capacitance, energy
relateda|Co(er)|VDS= 0 V to 480 V, VGS= 0 V||-|79|-|| |Effective output capacitance, time
relatedb|Co(tr)|||-|499|-|| |Totalgate charge|Qg|VGS= 10 V|ID= 17 A, VDS= 480 V|-|42|63|nC| |Gate-source charge|Qgs|||-|19|-|| |Gate-drain charge|Qgd|||-|10|-|| |Turn-on delay time|td(on)|VDD= 480 V, ID= 17 A,
VGS= 10 V, Rg= 9.1Ω||-|31|62|ns| |Rise time|tr|||-|96|144|| |Turn-off delay time|td(off)|||-|37|74|| |Fall time|tf|||-|31|62|| |Gate input resistance|Rg|f = 1 MHz, open drain||0.3|0.7|1.4|Ω| |**Drain-Source Body Diode Characteristics**|||||||| |Continuous source-drain diode current|IS|MOSFET symbol
showing the
integral reverse
p - n junction diode
S
D
G||-|-|35|A| |Pulsed diode forward current|ISM|||-|-|96|| |Diode forward voltage|VSD|TJ= 25 °C, IS= 17 A, VGS= 0 V||-|-|1.2|V| |Reverse recovery time|trr|TJ= 25 °C, IF= IS= 17 A,
di/dt = 80 A/μs, VR= 25 V||-|441|882|ns| |Reverse recovery charge|Qrr|||-|5.2|10.4|μC| |Reverse recovery current|IRRM|||-|21|-|A| |**SPECIFICATIONS**(TJ= 25 °C,unless otherwise noted)|**SPECIFICATIONS**(TJ= 25 °C,unless otherwise noted)|**SPECIFICATIONS**(TJ= 25 °C,unless otherwise noted)|**SPECIFICATIONS**(TJ= 25 °C,unless otherwise noted)||||| |---|---|---|---|---|---|---|---| |**PARAMETER**|**SYMBOL**|**TEST CONDITIONS**||**MIN.**|**TYP.**|**MAX.**|**UNIT**| |**Static**|||||||| |Drain-source breakdown voltage|VDS|VGS= 0 V, ID= 250 μA||600|-|-|V| |VDStemperature coefficient|ΔVDS/TJ|Reference to 25 °C, ID= 1 mA||-|0.64|-|V/°C| |Gate-source threshold voltage (N)|VGS(th)|VDS= VGS, ID= 250 μA||3.0|-|5.0|V| |Gate-source leakage|IGSS|VGS= ± 20 V||-|-|± 100|nA| |||VGS= ± 30 V||-|-|± 1|μA| |Zero gate voltage drain current|IDSS|VDS= 600 V, VGS= 0 V||-|-|1|μA| |||VDS= 480 V, VGS= 0 V, TJ= 125 °C||-|-|10|| |Drain-source on-state resistance|RDS(on)|VGS= 10 V|ID= 17 A|-|0.070|0.080|Ω| |Forward transconductancea|gfs|VDS= 20 V, ID= 17 A||-|4.6|-|S| |**Dynamic**|||||||| |Input capacitance|Ciss|VGS= 0 V,
VDS= 100 V,
f = 1 MHz||-|2557|-|pF| |Output capacitance|Coss|||-|105|-|| |Reverse transfer capacitance|Crss|||-|6|-|| |Effective output capacitance, energy
relateda|Co(er)|VDS= 0 V to 480 V, VGS= 0 V||-|79|-|| |Effective output capacitance, time
relatedb|Co(tr)|||-|499|-|| |Totalgate charge|Qg|VGS= 10 V|ID= 17 A, VDS= 480 V|-|42|63|nC| |Gate-source charge|Qgs|||-|19|-|| |Gate-drain charge|Qgd|||-|10|-|| |Turn-on delay time|td(on)|VDD= 480 V, ID= 17 A,
VGS= 10 V, Rg= 9.1Ω||-|31|62|ns| |Rise time|tr|||-|96|144|| |Turn-off delay time|td(off)|||-|37|74|| |Fall time|tf|||-|31|62|| |Gate input resistance|Rg|f = 1 MHz, open drain||0.3|0.7|1.4|Ω| |**Drain-Source Body Diode Characteristics**|||||||| |Continuous source-drain diode current|IS|MOSFET symbol
showing the
integral reverse
p - n junction diode
S
D
G||-|-|35|A| |Pulsed diode forward current|ISM|||-|-|96|| |Diode forward voltage|VSD|TJ= 25 °C, IS= 17 A, VGS= 0 V||-|-|1.2|V| |Reverse recovery time|trr|TJ= 25 °C, IF= IS= 17 A,
di/dt = 80 A/μs, VR= 25 V||-|441|882|ns| |Reverse recovery charge|Qrr|||-|5.2|10.4|μC| |Reverse recovery current|IRRM|||-|21|-|A| ## **Notes** a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS S21-0062-Rev. A, 01-Feb-2021 Document Number: 92375 **2** For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 **SiHG080N60E** Vishay Siliconix **==> picture [77 x 10] intentionally omitted <==** **----- Start of picture text -----**
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## **TYPICAL CHARACTERISTICS** (25 °C, unless otherwise noted) **==> picture [187 x 365] intentionally omitted <==** **----- Start of picture text -----**
100
15 V
9 V
14 V
13 V
75 12 V
11 V
10 V
8 V
50
TJ = 25 °C
7 V
25
6 V
5 V
0
0 5 10 15 20
VDS - Drain-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics
Axis Title
80
TJ = 150 °C 15 V
14 V
13 V
60 12 V
11 V 8 V
10 V
7 V
40
20
6 V
5 V
0
0 5 10 15 20
VDS - Drain-to-Source Voltage (V)
- Drain-to-Source Current (A)
ID
- Drain-to-Source Current (A)
ID
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**Fig. 2 - Typical Output Characteristics** **==> picture [187 x 160] intentionally omitted <==** **----- Start of picture text -----**
120
TJ = 25 °C
90
60
TJ = 150 °C
30
VDS = 25.6 V
0
0 5 10 15 20
VGS - Gate-to-Source Voltage (V)
- Drain-to-Source Current (A)
ID
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**Fig. 3 - Typical Transfer Characteristics** **==> picture [237 x 562] intentionally omitted <==** **----- Start of picture text -----**
3.0 10000
I D =17 A
2.5
2.0 1000
1.5
V GS = 10 V
1.0 100
0.5
0 10
-60 -40 -20 0 20 40 60 80 100 120 140 160
TJ - Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
Axis Title
100 000 10000
10 000
1000 C iss
1000
100
10 C oss
100
1 Crss
VGS = 0 V, f = 1 MHz
0.1 CC iss rss = C= C gs gd + C gd , C ds shorted
Coss = Cds + Cgd
0.01 10
0 100 200 300 400 500 600
VDS - Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Axis Title
20
50 000
15
5000
C oss Eoss 10
500
5
50 0
0 100 200 300 400 500 600
VDS - Drain-to-Source Voltage (V)
1st line 2nd line
(Normalized)
- Drain-to-Source On-Resistance
DS(on)
R
2nd line 1st line 2nd line
C - Capacitance (pF)
2nd line 2nd line
- Output Capacitance (pF)
oss
C
- Output Capacitance Stored Energy (µJ)
oss
E
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**Fig. 6 - Coss and Eoss vs. VDS** S21-0062-Rev. A, 01-Feb-2021 Document Number: 92375 **3** For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 **SiHG080N60E** ## www.vishay.com **==> picture [187 x 161] intentionally omitted <==** **----- Start of picture text -----**
12
VDS = 480 V
VDS = 300 V
9 V DS = 120 V
6
3
0
0 12 24 36 48
Qg - Total Gate Charge (nC)
- Gate-to-Source Voltage (V)
GS
V
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**Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage** **==> picture [209 x 365] intentionally omitted <==** **----- Start of picture text -----**
10000
100
TJ = 150 °C 1000
10
T J = 25 °C
100
1
V GS = 0 V
0.1 10
0.2 0.4 0.6 0.8 1.0 1.2 1.4
VSD - Source-Drain Voltage (V)
Fig. 8 - Typical Source-Drain Diode Forward Voltage
Axis Title
1000 10000
Operation in this area
limited by R DS(on)
100 IDM limited
1000
10 Limited by RDS(on) a 10 0 µs
1
1 m s100
0.1 TC = 25 °C, 10 ms
T J = 150 °C,
single pulse BVDSS limited
0.01 10
1 10 100 1000
VDS - Drain-to-Source Voltage (V)
- Reverse Drain Current (A)
ISD
- Drain Current (A)
ID
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**Fig. 8 - Typical Source-Drain Diode Forward Voltage** ## Vishay Siliconix **==> picture [209 x 160] intentionally omitted <==** **----- Start of picture text -----**
40 10000
30
1000
20
100
10
0 10
25 50 75 100 125 150
TC - Case Temperature (°C)
- Drain Current (A)
ID
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**Fig. 10 - Maximum Drain Current vs. Case Temperature** **==> picture [216 x 160] intentionally omitted <==** **----- Start of picture text -----**
1.2 10000
1.1
1000
1
0.9 100
I D = 250uA
0.8
-60 -40 -20 0 20 40 60 80 100 120 140 160
TJ - Junction Temperature (°C) 10
2nd line (Normalized)
- Drain-to-Source Breakdown Voltage
DS
V
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**Fig. 11 - Temperature vs. Drain-to-Source Voltage** **Fig. 9 - Maximum Safe Operating Area** **Note** a. VGS > minimum VGS at which RDS(on) is specified S21-0062-Rev. A, 01-Feb-2021 Document Number: 92375 **4** For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 **SiHG080N60E** Vishay Siliconix **==> picture [77 x 10] intentionally omitted <==** **----- Start of picture text -----**
www.vishay.com
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1
Duty cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single pulse
0.01
0.0001 0.001 0.01 0.1 1
Pulse Time (s)
Thermal Impedance
Normalized Effective Transient
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**Fig. 12 - Normalized Transient Thermal Impedance, Junction-to-Case** **==> picture [151 x 97] intentionally omitted <==** **----- Start of picture text -----**
RD
VDS
VGS
D.U.T.
R
g +
- VDD
10 V
Pulse width ≤ 1 μs
Duty factor ≤ 0.1 %
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**Fig. 13 - Switching Time Test Circuit** **==> picture [144 x 86] intentionally omitted <==** **----- Start of picture text -----**
VDS
90 %
10 %
VGS
td(on) tr td(off) tf
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**Fig. 14 - Switching Time Waveforms** **==> picture [149 x 240] intentionally omitted <==** **----- Start of picture text -----**
VDS
tp
VDD
VDS
IAS
Fig. 16 - Unclamped Inductive Waveforms
Qg
10 V
Qgs Qgd
VG
Charge
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Fig. 16 - Unclamped Inductive Waveforms
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**==> picture [151 x 8] intentionally omitted <==** **----- Start of picture text -----**
Fig. 17 - Basic Gate Charge Waveform
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L
VDS
Vary tp to obtain
required IAS
Rg D.U.T. +
- [V][DD]
IAS
10 V
tp 0.01 Ω
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**Fig. 15 - Unclamped Inductive Test Circuit** **==> picture [145 x 146] intentionally omitted <==** **----- Start of picture text -----**
Current regulator
Same type as D.U.T.
50 kΩ
12 V 0.2 μF
0.3 μF
+
D.U.T. - VDS
VGS
3 mA
IG ID
Current sampling resistors
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**Fig. 18 - Gate Charge Test Circuit** Document Number: 92375 S21-0062-Rev. A, 01-Feb-2021 **5** For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 **SiHG080N60E** Vishay Siliconix **==> picture [77 x 10] intentionally omitted <==** **----- Start of picture text -----**
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Peak Diode Recovery dv/dt Test Circuit
+ Circuit layout considerations
D.U.T.
• Low stray inductance
3 • Ground plane
• Low leakage inductance
current transformer
-
+
2
- - 4 +
1
Rg • dv/dt controlled by Rg +
• I• Driver same type as D.U.T.SD controlled by duty factor “D” - VDD
• D.U.T. - device under test
1 Driver gate drive
P.W.
Period D =
P.W. Period
VGS = 10 V [a]
2 D.U.T. ISD waveform
Reverse
recovery Body diode forward
current current
di/dt
3 D.U.T. VDS waveform Diode recovery
dv/dt
VDD
Re-applied
voltage
Body diode forward drop
Inductor current
4
Ripple ≤ 5 % ISD
Note
a. VGS = 5 V for logic level devices
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**Fig. 19 - For N-Channel** _Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?92375._ Document Number: 92375 S21-0062-Rev. A, 01-Feb-2021 **6** For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 **Package Information** Vishay Siliconix www.vishay.com ## **TO-247AC (High Voltage)** ## **VERSION 1: FACILITY CODE = 9** ||**MILLIMETERS**|**MILLIMETERS**||||**MILLIMETERS**|**MILLIMETERS**|| |---|---|---|---|---|---|---|---|---| |**DIM.**|**MIN.**|**MAX.**|**NOTES**||**DIM.**|**MIN.**|**MAX.**|**NOTES**| |A|4.83|5.21|||D1|16.25|16.85|5| |A1|2.29|2.55|||D2|0.56|0.76|| |A2|1.50|2.49|||E|15.50|15.87|4| |b|1.12|1.33|||E1|13.46|14.16|5| |b1|1.12|1.28|||E2|4.52|5.49|3| |b2|1.91|2.39|6||e|5.44 BSC||| |b3|1.91|2.34|||L|14.90|15.40|| |b4|2.87|3.22|6, 8||L1|3.96|4.16|6| |b5|2.87|3.18|||Ø P|3.56|3.65|7| |c|0.55|0.69|6||Ø P1|7.19 ref.||| |c1|0.55|0.65|||Q|5.31|5.69|| |D|20.40|20.70|4||S|5.54|5.74|| ## **Notes** > (1) Package reference: JEDEC® TO247, variation AC - (2) All dimensions are in mm - (3) Slot required, notch may be rounded > (4) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outermost extremes of the plastic body > (5) Thermal pad contour optional with dimensions D1 and E1 > (6) Lead finish uncontrolled in L1 > (7) Ø P to have a maximum draft angle of 1.5° to the top of the part with a maximum hole diameter of 3.91 mm > (8) Dimension b2 and b4 does not include dambar protrusion. Allowable dambar protrusion shall be 0.1 mm total in excess of b2 and b4 dimension at maximum material condition Revision: 19-Oct-2020 Document Number: 91360 **1** For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 **Package Information** **==> picture [77 x 10] intentionally omitted <==** **----- Start of picture text -----**
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## Vishay Siliconix ## **VERSION 2: FACILITY CODE = Y** **==> picture [430 x 278] intentionally omitted <==** **----- Start of picture text -----**
4 A A
B E ØP7 (Datum B)
E/2 S A2 Ø k M D B M
3 R/2 ØP1
A
D2
Q
2 x R 4 4
(2) D D1
1 2 3 D 4
Thermal pad
5 L1
C L 4
E1
See view B A 0.01 M D B M
2 x b2 C View A - A
2 x e
3 x b
b4 A1
0.10 M C A M
Planting (b1, b3, b5) Base metal
Lead Assignments
1. Gate D D E E
2. Drain
3. Source C C (c) c1
4. Drain
(b, b2, b4)
(4)
Section C - C, D - D, E - E
View B
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||**MILLIMETERS**|**MILLIMETERS**| |---|---|---| |**DIM.**|**MIN.**|**MAX.**| |A|4.58|5.31| |A1|2.21|2.59| |A2|1.17|2.49| |b|0.99|1.40| |b1|0.99|1.35| |b2|1.53|2.39| |b3|1.65|2.37| |b4|2.42|3.43| |b5|2.59|3.38| |c|0.38|0.86| |c1|0.38|0.76| |D|19.71|20.82| |D1|13.08|-| ||**MILLIMETERS**|**MILLIMETERS**|| |---|---|---|---| |**DIM.**|**MIN.**|**MAX.**|**NOTES**| |D2|0.51|1.30|| |E|15.29|15.87|| |E1|13.72|-|| |e|5.46 BSC||| |Ø k|0.254||| |L|14.20|16.25|| |L1|3.71|4.29|| |Ø P|3.51|3.66|| |Ø P1|-|7.39|| |Q|5.31|5.69|| |R|4.52|5.49|| |S|5.51 BSC||| ||||| ## **Notes** > (1) Dimensioning and tolerancing per ASME Y14.5M-1994 - (2) Contour of slot optional > (3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body > (4) Thermal pad contour optional with dimensions D1 and E1 - (5) Lead finish uncontrolled in L1 > (6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154") - (7) Outline conforms to JEDEC outline TO-247 with exception of dimension c Revision: 19-Oct-2020 Document Number: 91360 **2** For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 **Package Information** Vishay Siliconix www.vishay.com ## **VERSION 3: FACILITY CODE = N** **==> picture [251 x 280] intentionally omitted <==** **----- Start of picture text -----**
A
B E A P1
R/2 P
N A2
D
C
C
b4 E1
b2b e A1 0.01 M D B M
0.10 M C A M
b1, b3, b5
Base metal
b, b2, b4
Plating
D2
Q S
M
R D B
D1
D M
K
L1
L
c c1
**----- End of picture text -----**
||**MILLIMETERS**|**MILLIMETERS**|||**MILLIMETERS**|**MILLIMETERS**| |---|---|---|---|---|---|---| |**DIM.**|**MIN.**|**MAX.**||**DIM.**|**MIN.**|**MAX.**| |A|4.65|5.31||D2|0.51|1.35| |A1|2.21|2.59||E|15.29|15.87| |A2|1.17|1.37||E1|13.46|-| |b|0.99|1.40||e|5.46 BSC|| |b1|0.99|1.35||k|0.254|| |b2|1.65|2.39||L|14.20|16.10| |b3|1.65|2.34||L1|3.71|4.29| |b4|2.59|3.43||N|7.62 BSC|| |b5|2.59|3.38||P|3.56|3.66| |c|0.38|0.89||P1|-|7.39| |c1|0.38|0.84||Q|5.31|5.69| |D|19.71|20.70||R|4.52|5.49| |D1|13.08|-||S|5.51 BSC|| |ECN: E20-0545-Rev. F, 19-Oct-2020
DWG: 5971||||||| ECN: E20-0545-Rev. F, 19-Oct-2020 DWG: 5971 ## **Notes** > (1) Dimensioning and tolerancing per ASME Y14.5M-1994 - (2) Contour of slot optional > (3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body > (4) Thermal pad contour optional with dimensions D1 and E1 - (5) Lead finish uncontrolled in L1 > (6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154") Revision: 19-Oct-2020 Document Number: 91360 **3** For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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