# Power MOSFET, N Channel, 100 V, 104 A, 4800 µohm, PowerPAK SO-DC, Through Hole

![Product image](https://novapart.co/image/farnell:3350740/)

**URL**: https://novapart.co/products/SIDR668ADP-T1-RE3/power-mosfet-n-channel-100-v-104-a-4800-ohm
**SKU**: SIDR668ADP-T1-RE3
**Manufacturer**: VISHAY
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.9050
**Stock**: 1000+
**Lead Time**: 2 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | Lead (07-Nov-2024) |
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Product Range | TrenchFET Gen IV |
| Qualification | - |
| Power Dissipation | 125W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | PowerPAK SO-DC |
| Drain Source Voltage Vds | 100V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 104A |
| Drain Source On State Resistance | 4800µohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3350740/)

**SiDR668ADP** 

Vishay Siliconix 

~~‘~~ 

www.vishay.com 

## **N-Channel 100 V (D-S) MOSFET** 

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**----- Start of picture text -----**<br>
PowerPAK [®]  SO-8DC<br>D<br>D D6 D7 8<br>5<br>S<br>1<br>1 4 S3 S2 S<br>G<br>Top View Bottom View<br>PRODUCT SUMMARY<br>VDS (V) 100<br>RDS(on) max. (  ) at VGS = 10 V 0.0048<br>RDS(on) max. (  ) at VGS = 7.5 V 0.0070<br>Qg typ. (nC) 42<br>ID (A) 104<br>Configuration Single<br>——_——<br>5.15 mm<br>6.15 mm<br>**----- End of picture text -----**<br>


## **FEATURES** 

- TrenchFET[®] Gen IV power MOSFET 

- Very low RDS - Qg figure-of-merit (FOM) 

- Tuned for the lowest RDS - Qoss FOM 

- 100 % Rg and UIS tested 

- Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 

## **APPLICATIONS** 

D • Synchronous rectification • Primary side switch • DC/DC converters G • OR-ing • Power supplies • Motor drive control S • Battery and load switch N-Channel MOSFET 

## **ORDERING INFORMATION** 

Package PowerPAK SO-8DC Lead (Pb)-free and halogen-free SiDR668ADP-T1-RE3 

|**ABSOLUTE MAXIMUM RATINGS**(TA= 25 °C,unless otherwise noted)<br>~~Ce~~<br>~~(ORI~~|**ABSOLUTE MAXIMUM RATINGS**(TA= 25 °C,unless otherwise noted)<br>~~Ce~~<br>~~(ORI~~|**ABSOLUTE MAXIMUM RATINGS**(TA= 25 °C,unless otherwise noted)<br>~~Ce~~<br>~~(ORI~~|**ABSOLUTE MAXIMUM RATINGS**(TA= 25 °C,unless otherwise noted)<br>~~Ce~~<br>~~(ORI~~|**ABSOLUTE MAXIMUM RATINGS**(TA= 25 °C,unless otherwise noted)<br>~~Ce~~<br>~~(ORI~~|
|---|---|---|---|---|
|**PARAMETER**<br>~~Ce~~<br>~~nn~~||**SYMBOL**<br>~~Ce~~<br>~~nn~~<br>~~(ORI~~|**LIMIT**<br>~~Ce~~<br>~~nn~~<br>~~(ORI~~|**UNIT**<br>~~Ce~~<br>~~nn~~|
|Drain-source voltage<br>~~ee~~||VDS<br>~~(ORI~~<br>~~ee~~|100<br>~~(ORI~~<br>~~ee~~|V<br>~~ee~~|
|Gate-source voltage<br>~~ee~~<br>~~ES~~||VGS<br>~~ee~~|± 20<br>~~ee~~||
|Continuous drain current (TJ= 150 °C)<br>~~fCES~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~SS~~|TC= 25 °C<br>~~ES~~<br>~~|~~<br>~~SS~~|ID<br>~~Po~~<br>~~SS~~|104a<br>~~Po~~<br>~~SS~~|A<br>~~SS~~|
||TC= 70 °C<br>~~ES~~<br>~~|~~<br>~~|~~<br>~~SS~~||83a<br>~~Po~~<br>~~PO~~<br>~~SS~~||
||TA= 25 °C<br>~~ES~~<br>~~|~~<br>~~|~~<br>~~|~~<br>~~SS~~||23.3b, c<br>~~Po~~<br>~~PO~~<br>~~PO~~<br>~~SS~~||
||TA= 70 °C<br>~~ES~~<br>~~|~~<br>~~|~~<br>~~SS~~||18.3b, c<br>~~PO~~<br>~~PO~~<br>~~SS~~||
|Pulsed drain current (t = 100 μs)<br>~~ES~~<br>~~|~~<br>~~sD~~<br>~~SS~~||IDM<br>~~sD~~<br>~~SS~~|200<br>~~PO~~<br>~~sD~~<br>~~SS~~||
|Continuous source-drain diode current<br>~~SS~~|TC= 25 °C<br>~~SS~~|IS<br>~~SS~~|104<br>~~SS~~||
||TA= 25 °C<br>~~SS~~||5.6b, c<br>~~SS~~||
|Single pulse avalanche current<br>~~SS~~|L = 0.1 mH<br>~~SS~~|IAS<br>~~SS~~|35<br>~~SS~~||
|Single pulse avalanche energy<br>~~SS~~<br>~~i~~||EAS<br>~~SS~~|61.2<br>~~SS~~|mJ<br>~~SS~~|
|Maximum power dissipation<br>~~ES~~<br>~~|~~<br>~~|~~<br>~~pf~~|TC= 25 °C<br>~~|~~|PD<br>~~pf~~|125<br>~~_~~<br>~~PO~~|W<br>~~_~~|
||TC= 70 °C<br>~~|~~<br>~~|~~||80<br>~~_~~<br>~~PO~~<br>~~PO~~||
||TA= 25 °C<br>~~|~~<br>~~|~~||6.25b, c<br>~~_~~<br>~~PO~~<br>~~PO~~||
||TA= 70 °C<br>~~|~~<br>~~pf~~||4b, c<br>~~_~~<br>~~PO~~<br>~~pf~~||
|Operatingjunction and storage temperature range<br>~~pf~~<br>~~Oe~~||TJ, Tstg<br>~~pf~~<br>~~Oe~~|-55 to +150<br>~~pf~~<br>~~Oe~~|°C<br>~~Oe~~|
|Soldering recommendations (peak temperature)d, e<br>~~Oe~~||~~Oe~~|260<br>~~Oe~~||



a. Package limited 

b. Surface mounted on 1" x 1" FR4 board 

c. t = 10 s 

- d. See solder profile (www.vishay.com/doc?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection 

- e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components 

S21-0946-Rev. B, 27-Sep-2021 

Document Number: 77245 

**1** 

For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**SiDR668ADP** 

www.vishay.com 

Vishay Siliconix 

|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**||||
|---|---|---|---|---|---|
|**PARAMETER**||**SYMBOL**|**TYPICAL**|**MAXIMUM**|**UNIT**|
|Maximumjunction-to-ambienta|t10 s|RthJA|15|20|°C/W|
|Maximumjunction-to-case(drain)|Steadystate|RthJC|0.8|1||
|Maximumjunction-to-case(source)|Steadystate|RthJC|1.1|1.4||



## **Notes** 

a. Surface mounted on 1" x 1" FR4 board 

|**SPECIFICATIONS**(TJ= 25 °C,unless otherwise noted)|**SPECIFICATIONS**(TJ= 25 °C,unless otherwise noted)|**SPECIFICATIONS**(TJ= 25 °C,unless otherwise noted)|||||
|---|---|---|---|---|---|---|
|**PARAMETER**|**SYMBOL**|**TEST CONDITIONS**|**MIN.**|**TYP.**|**MAX.**|**UNIT**|
|**Static**|||||||
|Drain-source breakdown voltage|VDS|VGS= 0 V, ID= 250μA|100|-|-|V|
|VDStemperature coefficient|VDS/TJ|ID= 10 mA|-|58|-|mV/°C|
|VGS(th) temperature coefficient|VGS(th)/TJ|ID= 250μA|-|-9|-||
|Gate-source threshold voltage|VGS(th)|VDS= VGS, ID= 250μA|2|-|4|V|
|Gate-source leakage|IGSS|VDS= 0 V, VGS= ± 20 V|-|-|100|nA|
|Zero gate voltage drain current|IDSS|VDS= 100 V, VGS= 0 V|-|-|1|μA|
|||VDS= 100 V, VGS= 0 V, TJ= 70 °C|-|-|15||
|On-state drain currenta|ID(on)|VDS 10 V, VGS=10 V|40|-|-|A|
|Drain-source on-state resistancea|RDS(on)|VGS= 10 V, ID= 20 A|-|0.0040|0.0048||
|||VGS= 7.5 V, ID= 15 A|-|0.0054|0.0070||
|Forward transconductancea|gfs|VDS= 15 V, ID= 20 A|-|85|-|S|
|**Dynamicb**|||||||
|Input capacitance|Ciss|VDS= 50 V, VGS= 0 V, f = 1 MHz|-|3750|-|pF|
|Output capacitance|Coss||-|395|-||
|Reverse transfer capacitance|Crss||-|18|-||
|Total gate charge|Qg|VDS= 50 V, VGS= 10 V, ID= 10 A|-|54|81|nC|
|||VDS= 50 V, VGS= 7.5 V, ID= 10 A|-|42|63||
|Gate-source charge|Qgs||-|17.5|-||
|Gate-drain charge|Qgd||-|11.4|-||
|Output charge|Qoss|VDS= 50 V, VGS= 0 V|-|73|-||
|Gate resistance|Rg|f = 1 MHz|0.3|0.9|1.6||
|Turn-on delaytime|td(on)|VDD= 50 V, RL= 5, ID 10 A,<br>VGEN= 10 V, Rg= 1|-|21|42|ns|
|Rise time|tr||-|18|36||
|Turn-off delaytime|td(off)||-|36|72||
|Fall time|tf||-|10|20||
|Turn-on delaytime|td(on)|VDD= 50 V, RL= 5, ID 10 A,<br>VGEN= 7.5 V, Rg= 1|-|25|50||
|Rise time|tr||-|61|122||
|Turn-off delaytime|td(off)||-|34|68||
|Fall time|tf||-|11|22||
|**Drain-Source Body Diode Characteristics**|||||||
|Continuous source-drain diode current|IS|TC= 25 °C|-|-|104|A|
|Pulse diode forward current|ISM||-|-|200||
|Bodydiode voltage|VSD|IS= 5 A, VGS= 0 V|-|0.73|1.1|V|
|Bodydiode reverse recoverytime|trr|IF= 10 A, di/dt = 100 A/μs,<br>TJ= 25 °C|-|59|118|ns|
|Bodydiode reverse recoverycharge|Qrr||-|115|230|nC|
|Reverse recoveryfall time|ta||-|41|-|ns|
|Reverse recoveryrise time|tb||-|18|-||



## **Notes** 

a. Pulse test; pulse width  300 μs, duty cycle  2 % 

b. Guaranteed by design, not subject to production testing 

_Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability._ 

S21-0946-Rev. B, 27-Sep-2021 

**2** 

Document Number: 77245 

For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**SiDR668ADP** 

Vishay Siliconix 

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www.vishay.com<br>**----- End of picture text -----**<br>


## **TYPICAL CHARACTERISTICS** (25 °C, unless otherwise noted) 

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200<br>160 V GS = 10 V thru 7 V<br>120<br>VGS = 6 V<br>80<br>40<br>VGS = 5 V<br>0<br>0 1 2 3 4 5<br>VDS - Drain-to-Source Voltage (V)<br> - Drain Current (A)<br>ID<br>**----- End of picture text -----**<br>


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200<br>160<br>120<br>80 TC = 25 °C<br>TC = 125 °C<br>40<br>TC = -55 °C<br>0<br>0 2 4 6 8 10<br>VGS - Gate-to-Source Voltage (V)<br> - Drain Current (A)<br>ID<br>**----- End of picture text -----**<br>


**Output Characteristics** 

**Transfer Characteristics** 

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0.0065<br>0.0059<br>VGS = 7.5 V<br>0.0053<br>0.0047<br>VGS = 10 V<br>0.0041<br>0.0035<br>0 16 32 48 64 80<br>ID - Drain Current (A)<br>2nd line<br>On-Resistance vs. Drain Current and Gate Voltage<br>Axis Title<br>10<br>ID = 10 A<br>8<br>6<br>VDS = 25 V, 50 V, 75 V<br>4<br>2<br>0<br>0 12 24 36 48 60<br>Qg - Total Gate Charge (nC)<br> - On-Resistance (Ω)<br>DS(on)<br>R<br> - Gate-to-Source Voltage (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


**On-Resistance vs. Drain Current and Gate Voltage** 

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6000 10000<br>4800<br>Ciss 1000<br>3600<br>Coss<br>2400<br>100<br>Crss<br>1200<br>0 10<br>0 20 40 60 80 100<br>VDS - Drain-to-Source Voltage (V)<br>2nd line<br>Capacitance<br>Axis Title<br>2.5 10000<br>ID = 20 A<br>2.1 V GS = 10 V<br>1000<br>1.7<br>1.3 VGS = 7.5 V<br>100<br>0.9<br>0.5 10<br>-50 -25 0 25 50 75 100 125 150<br>TJ - Junction Temperature (°C)<br>C - Capacitance (pF)<br> - On-Resistance (Normalized)<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


**Gate Charge** 

**On-Resistance vs. Junction Temperature** 

Document Number: 77245 

S21-0946-Rev. B, 27-Sep-2021 

**3** 

For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**SiDR668ADP** 

Vishay Siliconix 

www.vishay.com 

## **TYPICAL CHARACTERISTICS** (25 °C, unless otherwise noted) 

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100<br>10<br>1 TJ = 150 °C TJ = 25 °C<br>0.1<br>0.01<br>0 0.2 0.4 0.6 0.8 1.0<br>VSD - Source-to-Drain Voltage (V)<br> - Source Current (A)<br>IS<br>**----- End of picture text -----**<br>


**Source-Drain Diode Forward Voltage** 

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**----- Start of picture text -----**<br>
0.05<br>0.04 ID = 20 A<br>0.03<br>0.02<br>TJ = 125 °C<br>0.01<br>TJ = 25 °C<br>0<br>5 6 7 8 9 10<br>VGS - Gate-to-Source Voltage (V)<br> - On-Resistance (Ω)<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


**On-Resistance vs. Gate-to-Source Voltage** 

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0.6 10000<br>0.2<br>1000<br>-0.2<br>ID = 5 mA<br>-0.6<br>100<br>ID = 250 μA<br>-1.0<br>-1.4 10<br>-50 -25 0 25 50 75 100 125 150<br>TJ - Junction Temperature (°C)<br>Threshold Voltage<br>Axis Title<br>500 10000<br>400<br>1000<br>300<br>200<br>100<br>100<br>0 10<br>0.001 0.01 0.1 1 10<br>Time (s)<br>2nd line<br> - Variance (V)<br>GS(th)<br>V<br>Power (W)<br>**----- End of picture text -----**<br>


**Single Pulse Power, Junction-to-Ambient** 

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1000 10000<br>I DM  limited<br>100 100 μs<br>ID limited<br>1000<br>10 1 ms<br>1 Limited b RDS(on) [(][1][)] y 10 ms<br>101 0  ms0<br>0.1 1 s<br>TA = 25 °C 10 s<br>Single pulse BVDSS limited DC<br>0.01 10<br>0.01 0.1 1 10 100<br>VDS - Drain-to-Source Voltage (V)<br>(1) VGS > minimum VGS at which RDS(on) is specified<br> - Drain Current (A)<br>ID<br>**----- End of picture text -----**<br>


**Safe Operating Area, Junction-to-Ambient** 

S21-0946-Rev. B, 27-Sep-2021 

Document Number: 77245 

**4** 

For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**SiDR668ADP** 

Vishay Siliconix 

www.vishay.com 

## **TYPICAL CHARACTERISTICS** (25 °C, unless otherwise noted) 

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120 10000<br>96<br>1000<br>72<br>48<br>100<br>24<br>0 10<br>0 25 50 75 100 125 150<br>TC - Case Temperature (°C)<br>Current Derating  [a]<br> - Drain Current (A)<br>ID<br>**----- End of picture text -----**<br>


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150 10000 3 10000<br>125 2.4<br>100 1000 1000<br>1.8<br>75<br>1.2<br>100<br>50 100<br>0.6<br>25<br>0 10<br>0 10 0 25 50 75 100 125 150<br>0 25 50 75 100 125 150<br>TA - Ambient Temperature (°C)<br>TC - Case Temperature (°C) 2nd line<br>Power, Junction-to-Case Power, Junction-to-Ambient<br>P - Power (W) 1st line 2nd line 2nd line Power (W)<br>**----- End of picture text -----**<br>


## **Note** 

a. The power dissipation PD is based on TJ max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit 

S21-0946-Rev. B, 27-Sep-2021 

Document Number: 77245 

**5** For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**SiDR668ADP** 

Vishay Siliconix 

**==> picture [77 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
www.vishay.com<br>**----- End of picture text -----**<br>


## **TYPICAL CHARACTERISTICS** (25 °C, unless otherwise noted) 

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1 10000<br>Duty Cycle = 0.5<br>0.2 Notes: 1000<br>PDM<br>0.1 0.1<br>t1<br>0.05 1. Duty cycle, D  t 2 = tt1 2 100<br>2. Per unit base = R thJA = 54 °C/W<br>0.02 3. TJM - TA = PDMZthJA (t)<br>Single pulse 4. Surface mounted<br>0.01 10<br>0.0001 0.001 0.01 0.1 1 10 100 1000<br>Square Wave Pulse Duration (s)<br>2nd line<br>Normalized Thermal Transient Impedance, Junction-to-Ambient<br>Axis Title<br>1 10000<br>Duty Cycle = 0.5<br>0.2<br>0.1<br>1000<br>0.05<br>0.02<br>0.1<br>Single pulse<br>100<br>0.01 10<br>0.0001 0.001 0.01 0.1 1 10<br>Square Wave Pulse Duration (s)<br>Thermal Impedance<br>Normalized Effective Transient<br>Thermal Impedance<br>Normalized Effective Transient<br>**----- End of picture text -----**<br>


## **Normalized Thermal Transient Impedance, Junction-to-Case** 

_Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see www.vishay.com/ppg?77245._ 

S21-0946-Rev. B, 27-Sep-2021 

Document Number: 77245 

**6** 

For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**Package Information** 

www.vishay.com 

## Vishay Siliconix 

## **PowerPAK[®] SO-8 Double Cooling Case Outline** 

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D<br>M4 M1 M4 K1 D1 K1<br>8 7 6 5 5 6 7 8<br>e<br>M2 M3<br>1 2 3 4 4 3 2 1<br>b<br>Back side view<br>T5<br>H<br>T2<br>E1<br>T1<br>E<br>E2<br>T3<br>K<br>L<br>T4<br>A<br>A1 c<br>**----- End of picture text -----**<br>


|**DIM.**|**MILLIMETERS**|**MILLIMETERS**|**MILLIMETERS**|**INCHES**|**INCHES**|**INCHES**|
|---|---|---|---|---|---|---|
||**MIN.**|**NOM.**|**MAX.**|**MIN.**|**NOM.**|**MAX.**|
|A|0.51|0.56|0.61|0.020|0.022|0.024|
|A1|0.00|0.02|0.05|0.000|0.001|0.002|
|b|0.36|0.41|0.46|0.014|0.016|0.018|
|c|0.15|0.20|0.25|0.006|0.008|0.010|
|D|4.90|5.00|5.10|0.193|0.197|0.201|
|D1|3.71|3.76|3.81|0.146|0.148|0.150|
|e|1.27 BSC|||0.050 BSC|||
|E|5.90|6.00|6.10|0.232|0.236|0.240|
|E1|3.60|3.65|3.70|0.142|0.144|0.146|
|E2|0.46 typ.|||0.018 typ.|||
|H|0.49|0.54|0.59|0.019|0.021|0.023|
|K|1.22|1.27|1.32|0.048|0.050|0.052|
|K1|0.64 typ.|||0.025 typ.|||
|L|0.49|0.54|0.59|0.019|0.021|0.023|
|M1|3.85|3.90|3.95|0.152|0.154|0.156|
|M2|2.74|2.79|2.84|0.108|0.110|0.112|
|M3|1.06|1.11|1.16|0.042|0.044|0.046|
|M4|0.56 typ.|||0.022 typ.|||
|N|8|||8|||
|T1|4.51|4.56|4.61|0.178|0.180|0.182|
|T2|2.58|2.63|2.68|0.102|0.104|0.106|
|T3|1.88|1.93|1.98|0.074|0.076|0.078|
|T4|0.97 typ.|||0.038 typ.|||
|T5|0.48 typ.|||0.019 typ.|||
|ECN: T21-0014-Rev. B, 08-Feb-2021<br>DWG: 6048|||||||



ECN: T21-0014-Rev. B, 08-Feb-2021 DWG: 6048 

Revison: 08-Feb-2021 **1** For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

Document Number: 75846 

**Application Note 826** 

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## Vishay Siliconix 

## **RECOMMENDED MINIMUM PADS FOR PowerPAK[®] SO-8 Single** 

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**----- Start of picture text -----**<br>
0.260<br>(6.61)<br>0.150<br>(3.81)<br>0.024<br>(0.61)<br>0.026<br>(0.66)<br>0.050 0.032 0.040<br>(1.27) (0.82) (1.02)<br>0.154 (3.91) 0.174 (4.42)<br>0.050 (1.27)<br>**----- End of picture text -----**<br>


Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index 

Return to Index 

Document Number: 72599 Revision: 21-Jan-08 

www.vishay.com 15 

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Revision: 09-Jul-2021 

Document Number: 91000 

**1** 



## Links

- [View this product on Novapart](https://novapart.co/products/SIDR668ADP-T1-RE3/power-mosfet-n-channel-100-v-104-a-4800-ohm)
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- [Supplier page](https://es.farnell.com/vishay/sidr668adp-t1-re3/mosfet-n-ch-100v-104a-150deg-c/dp/3350740)
---

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