# DC/DC Converter, 4.5 to 20 V Input, 12 A, 300mV to 12 V Output, PowerPAK MLP55, SiC454 Series

![Product image](https://novapart.co/image/farnell:4541154RL/)

**URL**: https://novapart.co/products/SIC454ED-T1-GE3/dc-converter-45-to-20-v-input-12-a-300mv-output
**SKU**: SIC454ED-T1-GE3
**Manufacturer**: VISHAY
**Category**: Power & Line Protection || Power Supplies || DC / DC Converters || DC / DC Non Isolated Board Mount Converters - Adjustable Output
**Price**: €2.0900
**Stock**: 1000+
**Lead Time**: 169 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| Product Range | micoBuck SIC454 Series |
| Output Current Max | 12A |
| Output Voltage Max | 12V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:4541154RL/)

**SiC454** 

www.vishay.com 

Vishay Siliconix 

## **4.5 V to 20 V Input, 12 A microBuck[®] DC/DC Converter With PMBus Interface** 

## **FEATURES** 

- Versatile 

- Single supply operation from 4.5 V to 20 V input voltage 

- Adjustable output voltage from 0.3 V to 12 V 

- Built in 5 V regulator for internal circuits and driver supply 

- 1 % output voltage accuracy over temperature 

- Ultrafast transient response 

- Highly efficient 

## **LINKS TO ADDITIONAL RESOURCES** 

- 98 % peak efficiency 

- Optional power save mode 

- Highly configurable 

Design Tool Evaluation Design Tools Boards 

## **DESCRIPTION** 

The SiC454 is a PMBus 1.3 compliant non-isolated DC/DC buck regulator with integrated MOSFETs. It is capable of supplying up to 12 A continuous output current. Its output voltage is digitally adjustable from 0.3 V to 12 V from a 4.5 V to 20 V input with switching frequencies up to 1.5 MHz. 

SiC454 architecture delivers ultrafast transient response with minimum output capacitance and tight regulation over a broad load range. The device has integrated internal compensation and is stable with any type of output capacitor. The device incorporates a power saving scheme that significantly increases light load efficiency. 

The SiC454 allows power block configuration programs to be stored in non volatile memory (NVM). Various operation parameters can all be locally stored and used to determine fault behavior. Operation is firmware based and is field upgradable Pinstrap option is also available for default configuration without PMBus. 

The SiC454 is available in lead (Pb)-free power enhanced MLP 5 mm x 5 mm package. 

## **TYPICAL APPLICATION CIRCUIT** 

**==> picture [204 x 109] intentionally omitted <==**

**----- Start of picture text -----**<br>
PGOOD<br>ENABLE<br>INPUT4.5 V to 20 V VIN PH VOUT<br>PVIN SW<br>j a L<br>PVVDDCC SiC45x VVSEN- SEN+ "<br>ADDR SALRT<br>RT/SYNC SDA<br>VSET SCL<br>EN GOODP BOOT<br>AGND PGND<br>**----- End of picture text -----**<br>


**Fig. 1 - Typical Application Circuit** 

- PMBus 1.3 compliant with 1 MHz bus speed 

- Internal NVM 

- VOUT adjustability and reading resolution of 2 mV 

- Supports over 50 PMBus commands 

- Supports in phase or 180° out of phase synchronization 

- Output voltage source and sink capability 

- Robust and reliable 

- PVIN, VOUT, IIN and IOUT and temperature reporting 

- Over current protection in pulse-by-pulse mode 

- Output over and under voltage protection 

- Over temperature protection with hysteresis 

- Differential output remote sensing 

## **APPLICATIONS** 

- Server, cloud, and infrastructure 

- Networking, telecom, storage applications 

- Distributed point of load power architectures 

- DDR memory 

**==> picture [187 x 160] intentionally omitted <==**

**----- Start of picture text -----**<br>
98<br>7)SSS<br>94<br>eer |<br>IM Nit VOUT = 5.0 V, Power save<br>90 V OUT = 5.0 V<br>NYS VOUT = 3.3 V, Power save<br>86 WEL VOUT = 3.3 V<br>VOUT = 2.5 V, Power save<br>WANO VOUT = 2.5 V<br>82 iin aan<br>Rees<br>78 Tee VIN = 12 V, fSW = 600kHz<br>0 2 4 6 8 10 12<br>IOUT - Output Current (A)<br>eff - Efficiency (%)<br>**----- End of picture text -----**<br>


**Fig. 2 - SiC454 Efficiency Curve** 

S23-1165-Rev. C, 25-Dec-2023 

Document Number: 63042 

**1** 

For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**SiC454** Vishay Siliconix 

~~—~~ www.vishay.com 

## **PIN CONFIGURATION** 

**==> picture [152 x 160] intentionally omitted <==**

**----- Start of picture text -----**<br>
SDA 1 20 NC<br>SCL 2 19 NC<br>EN 3 18 AGND<br>VDD 4 17 BOOT<br>VIN 5 16 GH<br>PVCC 6 15 PHASE<br>GL 7 14 PVIN<br>SW 8<br>SALRT RT/SYNC GNDA SETV ADDR GOODP SEN+V SEN-V NC<br>29 28 27 26 25 24 23 22 21<br>9 10 11 12 13<br>SW GNDP GNDP INPV INPV<br>**----- End of picture text -----**<br>


**Fig. 3 - Pin Configuration - Top View** 

|**PIN DESCRIPTION**|**PIN DESCRIPTION**|**PIN DESCRIPTION**|
|---|---|---|
|**PIN NUMBER**<br>~~a~~|**SYMBOL**<br>~~a~~|**DESCRIPTION**|
|1<br>~~a~~|SDA<br>~~a~~|PMBus data. Connect to external host interface|
|2<br>~~a~~|SCL<br>~~a~~|PMBus clock. Connect to external host interface|
|3<br>~~a~~|EN<br>~~a~~|Enablepin. Active high 5 V logic level input|
|4<br>~~a~~<br>~~a~~|VDD<br>~~a~~<br>~~a~~|Internal 5 V circuits supply voltage. VDD is a LDO output, connect a 1 μF to 4.7 μF decoupling capacitor<br>to AGND|
|5<br>~~a~~<br>~~a~~|VIN<br>~~a~~<br>~~aa ee~~|Input of internal LDO. Connect to the input of power train with a 0.1 μF MLCC decoupling capacitor to<br>AGND<br>~~ee~~|
|6<br>~~a~~<br>~~Re~~|PVCC<br>~~a~~<br>~~eG~~|Supply voltage for internal gate drive. PVCC is a LDO output. Connect a 4.7 μF decoupling capacitor to<br>PGND<br>~~eG~~|
|7<br>~~Re~~|GL<br>~~eG~~|Low side MOSFETgate monitor<br>~~eG~~|
|8, 9<br>~~Re~~<br>~~a~~|SW<br>~~eG~~<br>~~a~~|Switch node<br>~~eG~~|
|10, 11<br>~~a~~|PGND<br>~~a~~|Powerground. Common return for internal MOSFETs|
|12, 13, 14<br>~~a~~|PVIN<br>~~a~~|Input voltage forpower stage|
|15<br>~~a~~|PHASE<br>~~a~~|Phase node, returnpath of high sidegate driver|
|16<br>~~a~~|GH<br>~~a~~|High side MOSFETgate monitor|
|17<br>~~a~~|BOOT<br>~~a~~|Bootstrapvoltage for high sidegate driver(referenced to PHASE)|
|18<br>~~a~~|AGND<br>~~a~~|Analogsignal returnground|
|19, 20, 21<br>~~a~~|NC<br>~~a~~|Not internallyconnected. Leave it floating|
|22<br>~~a~~|VSEN-<br>~~a~~|Negative input of remote sense amplifier. Connect to outputground|
|23<br>~~a~~|VSEN+<br>~~a~~|Positive input of remote sense amplifier. Connect to output|
|24<br>~~a~~<br>~~ee~~|PGOOD<br>~~a~~<br>~~Ge~~|Power good. Open-drain output indicating VOUT is within set limits. Connect a pull up resistor typically<br>10 kohm to VDD<br>~~Ge~~|
|25<br>~~a~~<br>~~ee~~|ADDR<br>~~a~~<br>~~Ge~~|PMBus addressprogramming pin<br>~~Ge~~|
|26<br>~~ee~~<br>~~a~~|VSET<br>~~Ge~~<br>~~a~~|Output voltage setpoint byconnectinga resistor from VSET to AGND<br>~~Ge~~|
|27<br>~~a~~|AGND<br>~~a~~|Analogsignal returnground|
|28<br>~~a~~<br>~~ee~~|RT/SYNC<br>~~aa~~<br>|Clock synchronization pin. Frequency can be set by connecting a resistor to AGND.<br>Dependingon master / salve configuration, a clock can be send / receive via the pin<br>~~ee~~<br>|
|29<br><br>~~ee~~|SALRT<br>~~a~~<br>~~eG~~|PMBus alert. Connect to external host interface if desired<br>~~ee~~<br>~~eG~~|



S23-1165-Rev. C, 25-Dec-2023 

**2** 

For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**SiC454** 

www.vishay.com 

Vishay Siliconix 

## **PART MARKING INFORMATION** 

**==> picture [204 x 99] intentionally omitted <==**

**----- Start of picture text -----**<br>
= pin 1 indicator<br>P/N P/N = part number code<br>5 = Siliconix logo<br>F Y W W LL = ESD symbol<br>F = assembly factory code<br>Y = year code<br>WW     = week code<br>LL = lot code<br>**----- End of picture text -----**<br>


|**ABSOLUTE MAXIMUM RATINGS**(TA= 25 °C,unless otherwise noted)|**ABSOLUTE MAXIMUM RATINGS**(TA= 25 °C,unless otherwise noted)|**ABSOLUTE MAXIMUM RATINGS**(TA= 25 °C,unless otherwise noted)|**ABSOLUTE MAXIMUM RATINGS**(TA= 25 °C,unless otherwise noted)|
|---|---|---|---|
|**ELECTRICAL PARAMETER**<br>~~OO~~|**CONDITIONS**<br>~~OO~~|**LIMITS**<br>~~OO~~|**UNIT**<br>~~OO~~|
|PVIN, VIN<br>~~OO~~<br>~~=~~|Reference to PGND<br>~~OO~~<br>~~SS~~|-0.3 to +28<br>~~OO~~<br>~~SS~~|V<br>~~SS~~|
|SW / PH<br>~~=~~|Reference to PGND<br>~~SS~~|-0.3 to +28<br>~~SS~~||
|SW / PH (AC)<br>~~=~~<br>~~a~~|Reference to PGND(100 ns)<br>~~SS~~|-8 to +33<br>~~SS~~||
|BOOT<br>~~=~~<br>~~a~~<br>~~a~~<br>~~a~~|~~SS~~|-0.3 to VPH+ PVCC<br>~~SS~~||
|BOOT to SW<br>~~=~~<br>~~a~~<br>~~a~~<br>~~a~~|~~SS~~|-0.3 to +6<br>~~SS~~||
|Drive supply voltage (PVCC)<br>~~=~~<br>~~a~~<br>~~a~~<br>~~a~~|~~SS~~|-0.3 to +6<br>~~SS~~||
|Bias supply voltage (VDD)<br>~~=~~<br>~~a~~<br>~~a~~<br>~~a~~|~~SS~~<br>|-0.3 to +6<br>~~SS~~<br>||
|AGNDto PGND<br>~~=~~<br>~~a~~<br>~~a~~|~~SS~~<br>|-0.3 to +0.3<br>~~SS~~<br>||
|All other pins<br>~~= ~~<br>~~aDG~~|Reference to AGND<br> ~~SS~~<br>~~DG~~|-0.3 to VDD+ 0.3<br>~~SS~~<br>~~DG~~||
|**Temperature**||||
|Junction temperature||-40 to +150|°C|
|Storage temperature||-65 to +150||
|**Power Dissipation**||||
|Junction-to-ambient thermal impedance (RthJA)||24|°C/W<br>|
|Thermal resistance from junction to case (RthJ-C)<br>~~a~~||4.5<br>||
|Thermal resistance from junction to PCB (RthJ-PCB)<br>~~a~~||5<br>||
|**ESD Protection**<br>~~a~~||||
|Electrostatic discharge protection<br>~~+H~~|HBM<br>~~+H~~|2<br>~~+H~~|kV<br>~~+H~~|
||CDM<br>~~+H~~<br>~~es~~|750<br>~~+H~~<br>~~es~~|V<br>~~+H~~<br>~~es~~|



_Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating / conditions for extended periods may affect device reliability._ 

|**RECOMMENDED OPERATING CONDITIONS**(all voltages referenced to GND = 0 V)|**RECOMMENDED OPERATING CONDITIONS**(all voltages referenced to GND = 0 V)|**RECOMMENDED OPERATING CONDITIONS**(all voltages referenced to GND = 0 V)|**RECOMMENDED OPERATING CONDITIONS**(all voltages referenced to GND = 0 V)|**RECOMMENDED OPERATING CONDITIONS**(all voltages referenced to GND = 0 V)|
|---|---|---|---|---|
|**ELECTRICAL PARAMETER**|**MIN.**|**TYP.**|**MAX.**|**UNIT**|
|PVIN, VIN|4.5|-|20|V|
|Logic pins|0|-|5.5||
|VOUT|0.3|-|12||
|Drive supply voltage (PVCC)|4.75|5|5.25||
|Bias supply voltage (VDD)|4.75|5|5.25||
|**Temperature**|||||
|Recommended ambient temperature|-40 to +85|||°C|
|Operating junction temperature|-40 to +125||||



S23-1165-Rev. C, 25-Dec-2023 

Document Number: 63042 

**3** 

For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**SiC454** 

Vishay Siliconix 

www.vishay.com 

|**ELECTRICAL SPECIFICATIONS** (PVIN= 12 V,TJ= -40 °C to +125 °C,unless otherwise specified)|**ELECTRICAL SPECIFICATIONS** (PVIN= 12 V,TJ= -40 °C to +125 °C,unless otherwise specified)|**ELECTRICAL SPECIFICATIONS** (PVIN= 12 V,TJ= -40 °C to +125 °C,unless otherwise specified)|**ELECTRICAL SPECIFICATIONS** (PVIN= 12 V,TJ= -40 °C to +125 °C,unless otherwise specified)|**ELECTRICAL SPECIFICATIONS** (PVIN= 12 V,TJ= -40 °C to +125 °C,unless otherwise specified)|**ELECTRICAL SPECIFICATIONS** (PVIN= 12 V,TJ= -40 °C to +125 °C,unless otherwise specified)|**ELECTRICAL SPECIFICATIONS** (PVIN= 12 V,TJ= -40 °C to +125 °C,unless otherwise specified)|
|---|---|---|---|---|---|---|
|**PARAMETER**|**SYMBOL**|**TEST CONDITIONS**|**LIMITS**|||**UNIT**|
||||**MIN.**|**TYP.**|**MAX.**||
|**Power Supplies**|||||||
|PVIN, VIN|PVIN, VIN||4.5|-|20|V|
|VIN_ON,default|VIN_ON|Default setting|-|10|-||
|VIN_OFF,default|VIN_OFF|Default setting|-|9|-||
|PVCCsupply|VPVCC|VIN= 4.5 V to 20 V|4.5|5|5.5||
|VDDsupply|VDD|Logic supplyvoltage|4.5|5|5.5||
|PVCCUVLO threshold|VPVCC_UVLO_TH||3.4|3.6|3.8||
|PVCCUVLO hysteresis|VPVCC_UVLO_HYS||-|300|-|mV|
|Input current|IVIN|TJ= 25 °C, non-switching, no load, VOUT> VSET,<br>IPVCC+ IPVDD+ IPVIN|-|3.5|6|mA|
|Shutdown current|IVIN_SDN|EN = 0 V,IPVCC+ IPVDD+ IPVIN|-|2.5|6||
|**PVIN Monitoring**|||||||
|PVINmonitor accuracy|VPVIN_MON_ACC||-|3|-|%|
|PVINmin. monitor resolution|VPVIN_MON_RSO||-|70|-|mV|
|PVINmonitor full scale|VPVIN_MON_SCL||-|-|28|V|
|PVINread frequency|tPVIN_RSP||-|78|-|Hz|
|**IIN Fault Response Time**|||||||
|IINfault response time|tIIN_RSP|IIN_OC_WARN|-|78|-|Hz|
|**Pin(Inputpower)**|||||||
|Pin sense accuracy|PPVIN_SNS_ACC|5 W to 160 W|-|5|-|%|
|Pin sense resolution|PPVIN_SNS_RSO||-|0.5|-|W|
|**Output Voltage**|||||||
|VOUTdefault set-point|VOUT|VSETresistor = OPEN or SHORT|-|0.6|-|V|
|VOUTset-point accuracy|VOUT_ACC|Measured asV(VSEN+– VSEN-)|-1|-|1|%|
|VOUTset-point range|VOUT_RNG||0.3|-|12|V|
|VOUTset-point resolution|VOUT_RSO||-|2|-|mV|
|Line regulation|VOUT_REG||-|1|-|%|
|Load regulation|VOUT_REG||-|1|-||
|VOUTmin. monitor resolution|VOUT_MON_RSO|VOUTscale loop= 1|-|5|-|mV|
|VOUTstart updelayrange|tS_DLY_RNG|From PVINvalid until 1stPWMpulse|-|0|-|ms|
|VSEN+common mode range|VVSNS_RNG||-0.2|-|12|V|
|VSEN-common mode range|VVSNS_RNG||-200|-|200|mV|
|VOUTread conversion frequency|tVOUT_RSP||-|78|-|Hz|
|**Controller and Timing**|||||||
|Minimum on-time|tON_MIN||-|50|-|ns|
|Minimum off-time|tOFF_MIN||-|250|-||
|tONaccuracy|tON_ACC||-10|-|10|%|
|Frequency, default|fSW||540|600|660|kHz|
|Frequencysettingrange|fSW_RNG|CCM mode|300|-|1500||
|**VOUT Soft Start / Soft Stop**|||||||
|tONrise, default|tON_RISE|From VOUT= 0 V to VOUTsetpoint|-|5|-|ms|
|tONrise,settingrange|tON_RNG||0|-|127||
|tOFFfall, default|tSSP||-|5|-||
|tOFFfall, settingrange|tSSP,RNG||0|-|127||
|tONdelay,default|tON_DLY|From VOUT= 0 V to VOUTsetpoint|-|0|-||
|tONdelay, settingrange|tON_DLY,RNG||0|-|127||
|tOFFdelay, default|tOFF_DLY||-|0|-||
|tOFFdelay,settingrange|tOFF_DLY,RNG||0|-|127||
|tONmax. fault limit, default|tmax_FLT||-|20|-||
|tONmax. fault limit, settingrange|tmax_FLT,RNG||0|-|127||



S23-1165-Rev. C, 25-Dec-2023 

Document Number: 63042 

**4** For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**SiC454** Vishay Siliconix 

www.vishay.com 

|**ELECTRICAL SPECIFICATIONS** (PVIN= 12 V,TJ= -40 °C to +125 °C,unless otherwise specified)|**ELECTRICAL SPECIFICATIONS** (PVIN= 12 V,TJ= -40 °C to +125 °C,unless otherwise specified)|**ELECTRICAL SPECIFICATIONS** (PVIN= 12 V,TJ= -40 °C to +125 °C,unless otherwise specified)|**ELECTRICAL SPECIFICATIONS** (PVIN= 12 V,TJ= -40 °C to +125 °C,unless otherwise specified)|**ELECTRICAL SPECIFICATIONS** (PVIN= 12 V,TJ= -40 °C to +125 °C,unless otherwise specified)|**ELECTRICAL SPECIFICATIONS** (PVIN= 12 V,TJ= -40 °C to +125 °C,unless otherwise specified)|**ELECTRICAL SPECIFICATIONS** (PVIN= 12 V,TJ= -40 °C to +125 °C,unless otherwise specified)|
|---|---|---|---|---|---|---|
|**PARAMETER**|**SYMBOL**|**TEST CONDITIONS**|**LIMITS**|||**UNIT**|
||||**MIN.**|**TYP.**|**MAX.**||
|**Enable**|||||||
|EN pull down resistance|REN||-|5|-|M|
|**RT/SYNC**|||||||
|Logic high level|VRT/SYNC_HI||2|-|-|V|
|Logic low level|VRT/SYNC_LO||-|-|0.8||
|Input minimum pulse width|tIN Pulse_min||-|100|-|ns|
|Sync switching|FSYNC||300|-|1500|kHz|
|**Power Good**|||||||
|Power good output rising<br>threshold|VFB_RISING_TH|Default value respect to VOUTdefault setting = 0.6 V|-|90|-|%|
|Power good output falling<br>threshold|VFB_FALLING_TH||-|85|-||
|Powergood hysteresis|VFB_HYST||-|5|-||
|Powergood on resistance|RPG||-|5.5|-||
|Powergood delay time (rising)|tPG_RISE_DLY||-|25|-|μs|
|Powergood delay time (falling)|tPG_FALL_DLY||-|100|-||
|**Temperature Monitor and Temperature Shutdown**|||||||
|Monitoringresolution|TMON_RSO||-|1|-|°C|
|Monitoringrange|TMON_RNG||-40|-|+150||
|Monitoringaccuracy|TMON_ACC||-5|-|+5||
|Thermal shutdown|TSD||-|125|-||
|Thermal shutdown hysteresis|TSD_HYS||-|35|-||
|**Digital Inputs** **(ADDR, SALRT, SCLK, SDA, EN)**|||||||
|Input high threshold|VIH||2|-|-|V|
|Input low threshold|VIL||-|-|0.8||
|Input hysteresis|VHYST||-|0.1|-||
|Pin capacitance|CPIN||-|5|-|pF|
|**Fault Protections**|||||||
|Valley current limit, default|IOCP|SiC454, TJ= -40 °C to +85 °C|-|17|-|A|
|Output OVP threshold, default|VOVP|VOUTwith respect to VSET|-|115|-|%|
|Output UVP threshold, default|VUVP||-|80|-||
|**Telemetry**|||||||
|VIN|VIN|Load current, 20 % to 100 %<br>(TA= -40 °C to +125 °C)|-3|-|3|%|
|IIN|IIN|20 % of load current (TA= 25 °C)|-15|-|15||
|||50 % of load current (TA= 25 °C)|-6|-|6||
|||100 % of load current (TA= 25 °C)|-5|-|5||
|PIN|PIN|20 % of load current (TA= 25 °C)|-9|-|9||
|||50 % of load current (TA= 25 °C)|-4|-|4||
|||100 % of load current (TA= 25 °C)|-3|-|3||
|VOUT|VOUT|2 V < VOUT< 5.5 V, load current, 20 % to 100 %<br>(TA= -40 °C to +125 °C)|-6|-|6||
|||0.5 V < VOUT< 2 V, load current, 20 % to 100 %<br>(TA= -40 °C to +125 °C)|-7|-|7||
|IOUT|IOUT|20 % of load current (TA= 25 °C)|-12|-|12||
|||50 % of load current (TA= 25 °C)|-4|-|4||
|||100 % of load current (TA= 25 °C)|-3|-|3||
|POUT|POUT|20 % of load current (TA= 25 °C)|-9|-|9||
|||50 % of load current (TA= 25 °C)|-4|-|4||
|||100 % of load current (TA= 25 °C)|-3|-|3||



S23-1165-Rev. C, 25-Dec-2023 

**5** 

Document Number: 63042 

For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**SiC454** 

www.vishay.com 

Vishay Siliconix 

## **FUNCTIONAL BLOCK DIAGRAM** 

**==> picture [480 x 315] intentionally omitted <==**

**----- Start of picture text -----**<br>
V IN EN<br>PVCC Linear regulator UVLO PVIN<br>VDD VDD PVCC<br>UVLO<br>SW PFD Charge<br>RT / SYNC pump<br>BOOT<br>Ramp<br>VVSEN+SEN- Differentialamplifier generatorOTA comparatorPWM generatortON High sidedriver PH<br>Rcomp Minimum SW<br>Ccomp Cp tOFF Control<br>Bandgap generatorReferenceand  logic PVCC<br>DAC<br>VSET ADCVSET<br>Low side<br>ADDR ADC PEC/BUS Command  driver<br>management registers<br>SALRT PMBus<br>interface<br>SCLK 1K<br>NVM Over<br>SDA Fault protectioncurrent  PGND<br>management<br>Monitoring Zero<br>AGND compensationcalculationP   / PIN OUT ADC Monitoringcircuitssense circuitPGOOD detectorcrossing<br>PGOOD<br>**----- End of picture text -----**<br>


**Fig. 4 - Functional Block Diagram** 

S23-1165-Rev. C, 25-Dec-2023 

Document Number: 63042 

**6** For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**SiC454** 

Vishay Siliconix 

**==> picture [77 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
www.vishay.com<br>**----- End of picture text -----**<br>


## **OPERATIONAL DESCRIPTION** 

## **Device Overview** 

SiC454 is a high efficiency synchronous buck regulator capable of delivering up to 25 A continuous current. The device has programmable switching frequency of 300 kHz to 1.5 MHz. The control scheme delivers fast transient response and minimizes external components. Thanks to the internal current ramp information, no high ESR output bulk or virtual ESR network is required for the loop stability. This device also incorporates a power saving feature by enabling diode emulation mode and frequency fold back as the load decreases. 

In addition, a built in PLL allows in phase or 180° out of phase synchronization under master / slave configuration. 

SiC454 has a full set of protection and monitoring features with response that can be set with PMBus: 

- Over current protection in pulse-by-pulse mode 

- Output over voltage protection 

- Output under voltage protection 

- Over temperature protection with hysteresis 

- Dedicated enable pin for easy power sequencing 

- Power good open drain output 

This device is available in MLP34-57 package to deliver high power density and minimize PCB area. 

## **PWM Control Mechanism** 

SiC454 employs a voltage - mode COT control mechanism. During steady-state operation, feedback voltage is compared with internal reference and the amplified error signal (VCOMP) is generated in the internal comp node. An internally generated ramp signal and VCOMP are fed into a comparator. Once VRAMP crosses VCOMP, a single shot on-time pulse is generated for a fixed time, programmed by the external Rfsw. During the on-time pulse, the high side MOSFET will be turned on. Once the on-time pulse expires, the low side MOSFET will be turned on after a break-before-make period. The low side MOSFET will be on for duration of minimum off-time pulse until VRAMP crosses VCOMP. The cycle is then repeated. 

Fig. 5 illustrates the basic block diagram for VM-COT architecture. In this architecture the following is achieved: 

- The reference of a basic ripple control regulator is replaced with a high again error amplifier loop 

- This establishes two parallel voltage regulating feedback paths, a fast and slow path 

- Fast path is the ripple injection which ensures rapid correction of the transient perturbation 

- Slow path is the error amplifier loop which ensures the DC component of the output voltage follows the internal accurate reference voltage 

**==> picture [228 x 167] intentionally omitted <==**

**----- Start of picture text -----**<br>
PVIN<br>PVIN<br>SW<br>PGND Load<br>Constant on time<br>PWM generator<br>Ramp generator VSEN+<br>Comparator Differential<br>amplifier<br>OTA<br>CP Rcomp REF VSEN-<br>Ccomp<br>AGND<br>**----- End of picture text -----**<br>


**Fig. 5 - VM-COT Block Diagram** 

All components for RAMP signal generation and error amplifier compensation required for the control loop are internal to the IC, see Fig. 5. In order for the device to cover a wide range of VOUT operation, the internal RAMP signal components are automatically selected depending on the VOUT voltage and switching frequency. The error amplifier internal compensation consists of a resistor in series with a capacitor (RCOMP, CCOMP). 

Fig. 6 demonstrates the basic operational waveforms: 

## Basic operational waveforms 

**==> picture [168 x 132] intentionally omitted <==**

**----- Start of picture text -----**<br>
VRAMP<br>VCOMP<br>PWM Fixed on-time<br>**----- End of picture text -----**<br>


**Fig. 6 - VM-COT Operational Principle** 

## **Light Load Condition** 

To improve efficiency at light-load condition, SiC454 provide a set of innovative implementations to eliminate LS recirculating current and switching losses. The internal zero crossing detector monitors SW node voltage to determine when inductor current starts to flow negatively. In power saving mode, as soon as inductor valley current crosses zero, the device deploys diode emulation mode by turning off low side MOSFET. If load further decreases, switching frequency is reduced proportional to load condition to save switching losses while keeping output ripple within tolerance. The switching frequency is set by the controller to 

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Document Number: 63042 

**7** 

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## www.vishay.com 

maintain regulation. In the standard power save mode, there is no minimum switching frequency. If ultrasonic mode is selected via PMBus, the minimum switching frequency that the regulator will reduce to is > 20 kHz as the part avoids switching frequencies in the audible range. 

## **Power Stage** 

SiC454 integrates a high performance power stage with a 4 m  n-channel high side MOSFET and a 1.4 m  n-channel low side MOSFET. The MOSFETs are optimized to achieve up to 96 % efficiency. 

The power input voltage (PVIN) can go up to 20 V and down as low as 4.5 V. The output voltage must always be less than the input voltage. 

pulses in a row, secondary level OC fault is recognized and both HS and LS MOSFETs are turned off. The device continues restart attempt in a delay time until the OC fault condition no longer exists. 

The consecutive switching pulse in a row, the delay time, and other types of fault responses can be programmed via PMBus (see PMBus command section). The default number is 128 for counting consecutive switching pulse in a row. The default delay time is 20 ms. 

The OCP is enabled immediately after VDD passes UVLO level. 

## **Sequencing of Input / Output Supplies** 

SiC454 has no sequencing requirements on any of its input / output, PVIN, PVCC, VIN, VDD and EN. VIN is internal supply voltage and is used to implement on time of COT control. VIN shall be directly connected to PVIN. 

## **EN** 

The SiC454 has an EN pin to turn the part on and off. Driving this pin high enables the device, while grounding it turns it off. 

There are no sequencing requirements with respect to input / output supplies. 

## **Output Overcurrent Protection (OCP)** 

SiC454 has pulse-by-pulse overcurrent (OC) limit control. The inductor valley current is monitored during low-side (LS) FET turn-on period through RDS(on) sensing. After a pre-defined blanking time, the valley current is compared with an internal OCP threshold named IOUT_OC_FAULT_LIMIT, which can be programmed via PMBus. Once monitored valley current is larger than IOUT_OC_FAULT_LIMIT, a pulse-by-pulse over-current limit is broken, high-side (HS) turn-on pulse is skipped and LS FET is kept on until the inductor valley current returns below OCP limit as illustrated by Fig. 7. 

An equation is given in (1) to calculate IOUT_OC_FAULT_LIMIT from steady-state value of DC load current when OCP happens. 

**==> picture [183 x 101] intentionally omitted <==**

**----- Start of picture text -----**<br>
OCPthreshold<br>Iload<br>Iinductor<br>GH<br>Skipped GH pulse<br>**----- End of picture text -----**<br>


**Fig. 7 - Over-Current Protection Illustration** 

## **Output Undervoltage Protection (UVP)** 

UVP is implemented by monitoring the output voltage. If the output voltage drops below a threshold voltage VOUT_UV_FAULT_LIMIT (VUFL), the output-undervoltage (UV) fault condition is recognized and both the HS and LS MOSFETs are turned off. The device continues restart attempt in a delay time until the UV condition no longer exists. 

The VUFL and the delay time can be programmed via PMBus (see PMBus command section). The default value of VUFL is 20 % less than the target VOUT. The default delay time is 20 ms. 

The UVP is only active after the completion of soft-start sequence. 

## **Output-Overvoltage Protection (OVP)** 

IOUT_OC_FAULT_LIMIT = 

**==> picture [237 x 24] intentionally omitted <==**

where: IOUT_OC_FAULT_LIMIT is the OCP threshold to be programmed via PMBus; IOUT_OCP is the steady-state value of DC load current when pulse-by-pulse OC event happens; PVIN is the input voltage for power stage; VOUT is the output voltage for power stage; L is inductance of power inductor; and fSW is switching frequency for power stage. 

SiC454 also provides secondary level OCP protection. If the pulse-by-pulse overcurrent limit is persistently broken for more than a specific number of consecutive switching 

OVP is implemented by monitoring the output voltage. If the output voltage is above a threshold voltage VOUT_OV_FAULT_LIMIT (VOFL), the output-overvoltage (OV) fault condition is recognized and both the HS and LS MOSFETs are turned off. The device restarts when the OV fault condition no longer exists. 

The UVFL can be programmed via PMBus (see PMBus command section). The default value of VOFL is 15 % more than the target VOUT. 

The OVP is enabled immediately after VDD passes UVLO level. 

## **Input-Overvoltage Protection (VIN-OVP)** 

VIN-OVP is implemented by monitoring the input voltage. 

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When the input voltage is pulled above a threshold voltage VIN_OV_FAULT_LIMIT (VIN-OFL), the input-overvoltage (VIN-OV) fault condition is recognized and both the HS and LS MOSFETs are turned off. When the input voltage is pulled below the VIN-OFL, the VIN-OV fault condition no longer exists and the device restarts. 

The VIN-OFL can be programmed via PMBus (see PMBus command section). The default value of VIN-OFL is 15 V. The VIN-OVP is enabled immediately after VDD passes UVLO level. 

## **Input-Undervoltage Protection (VIN-UVP)** 

VIN-UVP is implemented by monitoring the input voltage. When the input voltage is pulled below a threshold VIN_OFF, the input-undervoltage (VIN-UV) fault condition is recognized and both the HS and LS MOSFETs are turned off. When the input voltage is pulled above a threshold VIN_ON, the VIN-UV fault condition no longer exists and the device restarts. 

The VIN-OFF and VIN_ON can be programmed via PMBus (see PMBus command section). The default value of VIN-OFF is 9 V. The default value of VIN_ON is 10 V. 

The VIN-UVP is enabled immediately after VDD passes   UVLO level. 

## **tON-MAX. Protection (tMP)** 

SiC454 has power up time limit control. When the device does not power up the output voltage above the VUFL in a time interval longer than tON_MAX_FAULT_LIMIT (tMFL), the tON-MAX. (tM) fault condition is recognized and both the HS and LS MOSFETs are turned off. The device continues restart attempt after the shutdown in a delay time until the tM fault no longer exists. 

The tMFL and delay time can be programmed via PMBus (see PMBus command section). The default value of tMFL is 20 ms. The default delay time is 20 ms. 

The tMP is enabled immediately after VDD passes UVLO level. 

## **Overtemperature Protection (OTP)** 

SiC454 has internal thermal monitor block to support device temperature control. When the device temperature rises above OT_FAULT_LIMIT (OFL), the overtemperature (OT) fault condition is recognized and both the HS and LS MOSFETs are turned off. When OT fault condition no longer exists, the device restarts. 

The OFL can be programmed via PMBus (see PMBus command section). The default value of OFL is 125 °C. 

The OTP is enabled immediately after VDD passes UVLO level. 

## **Pre-Bias Start-Up** 

VOUT is monitored through differential output voltage sense pins Vsen+ and Vsen-. If the sensed voltage is higher than VSET, control logic prevents HS and LS FET from switching to avoid negative output voltage spike and excessive current sinking through LS FET. 

**Fig. 8 - Pre-Bias Start-Up** 

## **Output Voltage Setting** 

Connecting a resistor from VSET to AGND will set output voltage (VOUT), eight VOUT related warning and fault voltage limits, and the value of VOUT_SCALE_LOOP as listed in the “VOUT_SCALE_LOOP look up” table. See below 2 tables for the list of supported output voltage (VOUT) set by the VSET resistor value and related warning and fault limits. 

In case the output voltage is set by PMBUS, the VSET pin needs to be shorted to AGND or left open. If so, the output voltage can be set with resolution of 1.953 mV and the related warning and fault limits can also be set independently. 

If a different voltage other than one listed in the “OUTPUT VOLTAGE SETTINGS” table is required without PMBUS, a resistor divider can be used between output voltage sense point, VSEN+ and VSEN- pins. Output voltage will be less accurate with this method. Contact Vishay to know how. 

|**OUTPUT VOLTAGE SETTINGS**|**OUTPUT VOLTAGE SETTINGS**|
|---|---|
|**VSET RESISTOR (k****)**|**VOUT (V)**|
|0.845|0.60|
|1.30|0.90|
|1.78|0.95|
|2.32|1.00|
|2.87|1.05|
|3.48|1.20|
|4.12|1.25|
|4.75|1.50|
|5.49|1.80|
|6.19|2.10|
|6.98|2.50|
|7.87|3.30|
|8.87|5.00|
|11.0|12.00|



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Document Number: 63042 

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## www.vishay.com 

|**VOUT RELATED WARNINGS AND**<br>**FAULTS**|**VOLTAGE LEVEL**|
|---|---|
|POWER_GOOD_ON|90 % VOUT|
|POWER_GOOD_OFF|85 % VOUT|
|VOUT_OV_FAULT_LIMIT|115 % VOUT|
|VOUT_OV_WARN_LIMIT|110 % VOUT|
|VOUT_UV_WARN_LIMIT|90 % VOUT|
|VOUT_UV_FAULT_LIMIT|80 % VOUT|
|VOUT_MARGIN_LOW|95 % VOUT|
|VOUT_MARGIN_HIGH|105 % VOUT|



## **RT/SYNC PIN and Mode of Switching Configuration** 

The SiC454 has an RT / SYNC pin. This pin can be used to set the switching frequency and to send or receive a clock signal for synchronization between a master and slave. SiC454 will inject less than 1 mA DC current across the RT/SYNC pin to the ground during initial power up process, and connecting a resistor from the RT/SYNC pin to ground will be used to set the switching frequency according to the table listed below. The following table shows the supported frequency settings by the RT resistor value. Please do not leave the setting resistor open or short, or contact Vishay for technical support. The frequency set by the external resistor can be overridden by a PMBus command with resolution 50 kHz (see PMBus command table). 

|**FREQUENCY SETTINGS**|**FREQUENCY SETTINGS**|
|---|---|
|**RT RESISTOR (k****)**|**FREQUENCY (kHz)**|
|0.845|300|
|1.30|400|
|1.78|500|
|2.32|550|
|2.87|600|
|3.48|650|
|4.12|700|
|4.75|750|
|5.49|800|
|6.19|850|
|6.98|900|
|7.87|950|
|8.87|1000|
|10|1250|
|11|1500|



SiC454 supports four modes of switching configuration, including standalone mode, master mode, slave mode in phase, and slave mode 180° out of phase. The master mode is default one of switching configuration and user can override it to be either standalone mode, slave mode in phase, or slave mode 180° out of phase by PMBus command INTERLEAVE (see PMBus command table). 

The following table introduces four modes of switching configuration, recommended RT/SYNC pin connections, and content of related PMBus command INTERLEAVE. 

## **MODE OF SWITCHING CONFIGURATION, PIN CONNECTION, AND INTERLEAVE PMBus** 

|**MODE OF SWITCHING CONFIGURATION, PIN CONNECTION, AND INTERLEAVE PMBus**|**MODE OF SWITCHING CONFIGURATION, PIN CONNECTION, AND INTERLEAVE PMBus**|**MODE OF SWITCHING CONFIGURATION, PIN CONNECTION, AND INTERLEAVE PMBus**|**MODE OF SWITCHING CONFIGURATION, PIN CONNECTION, AND INTERLEAVE PMBus**|**MODE OF SWITCHING CONFIGURATION, PIN CONNECTION, AND INTERLEAVE PMBus**|
|---|---|---|---|---|
|**MODE TYPE**|**MODE DESCRIPTION**|**SWITCHING FREQUENCY AND RECOMMENDED**<br>**RT/SYNC PIN CONNECTION**|**SWITCHING**<br>**PHASE**|**INTERLEAVE**<br>**COMMAND**|
|Standalone|Chip works individually|Cross a resistor RRTfrom RT / SYNC pin to ground. During<br>power up, less than 1 mA DC current will be injected into<br>resistor RRTto determine default switching frequency. The<br>default switching frequency can be overridden by PMBus<br>command. After power up, RT / SYNC pin is released and<br>connected toground via RRT.|Self determined|0x0000|
|Master|Chip works as a master<br>chip outputting a clock<br>signal in phase with its<br>switching to drive an<br>external slave chip’s<br>switching frequency and<br>phase|Cross a resistor RRTfrom RT / SYNC pin to ground. During<br>power up, less than 1 mA DC current will be injected into<br>resistor RRTto determine default switching frequency. The<br>default switching frequency can be overridden by PMBus<br>command. After power up, RT / SYNC pin outputs a 50 %<br>duty cycle pulse signal toggling between 0 and VDD, which<br>is in phase with the chip’s switchingnode.|Self determined|0x0100|
|Slave in phase|Chip works as a slave<br>chip receiving an external<br>clock signal and<br>synchronize its switching<br>in phase with the clock<br>signal|Cross a resistor RRTfrom RT / SYNC pin to ground. During<br>power up, less than 1 mA DC current will be injected into<br>resistor RRTto determine default switching frequency. The<br>default switching frequency can be overridden by PMBus<br>command. When there is an external clock signal<br>presented at the RT / SYNC pin, the switching frequency<br>will be overridden and the chip’s switching node is in<br>phase with the external clock signal. If the external clock<br>signal comes from a SiC454 working in master mode<br>switching configuration, the resistor RRTshall be same to<br>the RRTused by the master chip.|In phase with the<br>external clock, or<br>self determined<br>when individually<br>works|0x0120|



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Document Number: 63042 

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## **MODE OF SWITCHING CONFIGURATION, PIN CONNECTION, AND INTERLEAVE PMBus** 

|**MODE OF SWITCHING CONFIGURATION, PIN CONNECTION, AND INTERLEAVE PMBus**|**MODE OF SWITCHING CONFIGURATION, PIN CONNECTION, AND INTERLEAVE PMBus**|**MODE OF SWITCHING CONFIGURATION, PIN CONNECTION, AND INTERLEAVE PMBus**|**MODE OF SWITCHING CONFIGURATION, PIN CONNECTION, AND INTERLEAVE PMBus**|**MODE OF SWITCHING CONFIGURATION, PIN CONNECTION, AND INTERLEAVE PMBus**|
|---|---|---|---|---|
|**MODE TYPE**|**MODE DESCRIPTION**|**SWITCHING FREQUENCY AND RECOMMENDED**<br>**RT/SYNC PIN CONNECTION**|**SWITCHING**<br>**PHASE**|**INTERLEAVE**<br>**COMMAND**|
|Slave 180 °<br>out of phase|Chip works as a slave<br>chip receiving an external<br>clock signal and<br>synchronize its switching<br>180 ° out of phase with<br>the clock signal|Cross a resistor RRTfrom RT / SYNC pin to ground. During<br>power up, less than 1 mA DC current will be injected into<br>resistor RRTto determine default switching frequency. The<br>default switching frequency can be overridden by PMBus<br>command. When there is an external clock signal<br>presented at the RT / SYNC pin, the switching frequency<br>will be overridden and the chip’s switching node is 180°<br>out of phase with the external clock signal. If the external<br>clock signal comes from a SiC454 working in master mode<br>switching configuration, the resistor RRTshall be same to<br>the RRTused by the master chip|180° out of phase<br>with the external<br>clock, or self<br>determined when<br>individually<br>works|0x0121|



## **PMBus ADDRESS (ADDR pin)** 

The SiC454 has a 7-bit register that are used to set the base PMBus address of the device. A resistor assembled between ADDR pin and ground sets an offset from the default pre-configured MFR base address in the memory. Up to 15 different offsets can be set allowing 15 SiC454 devices with unique addresses in a single system. This offset and therefore the device address is read by the ADC during the initialization sequence. The table below provides the resistor values needed to set the 15 offsets from the base address. Please do not leave the setting resistor open or short, or contact Vishay for technical support. 

## **MFR_BASE_ADDRESS** 

|**MFR_BASE_ADDRESS**|**MFR_BASE_ADDRESS**|**MFR_BASE_ADDRESS**|**MFR_BASE_ADDRESS**|**MFR_BASE_ADDRESS**|
|---|---|---|---|---|
|**CONNECTION**|**ADDRESS**|**HEX**<br>**[3 : 0]**|**NVM**<br>**[6 : 4]**|**BIN**<br>**[6 : 0]**|
|0.845K|1|0|001b|0010 000b|
|1.3K|2|1|001b|0010 001b|
|1.78K|3|2|001b|0010 010b|
|2.32K|4|3|001b|0010 011b|
|2.87K|5|4|001b|0010 100b|
|3.48K|6|5|001b|0010 101b|
|4.12K|7|6|001b|0010 110b|
|4.75K|8|7|001b|0010 111b|
|5.49K|9|8|001b|0011 000b|
|6.19K|10|9|001b|0011 001b|
|6.98K|11|A|001b|0011 010b|
|7.87K|12|B|001b|0011 011b|
|8.87K|13|C|001b|0011 100b|
|10K|14|D|001b|0011 101b|
|11K|15|E|001b|0011 110b|



Vishay provides another 15 options of PMBus address listed in table of MFR_BASE_ADDRESS_2. Please contact Vishay for technical support. 

## **MFR_BASE_ADDRESS_2** 

|**MFR_BASE_ADDRESS_2**|**MFR_BASE_ADDRESS_2**|**MFR_BASE_ADDRESS_2**|**MFR_BASE_ADDRESS_2**|**MFR_BASE_ADDRESS_2**|
|---|---|---|---|---|
|**CONNECTION**|**ADDRESS**|**HEX**<br>**[3 : 0]**|**NVM**<br>**[6 : 4]**|**BIN**<br>**[6 : 0]**|
|0.845K|1|0|101b|1010 000b|
|1.3K|2|1|101b|1010 001b|
|1.78K|3|2|101b|1010 010b|
|2.32K|4|3|101b|1010 011b|
|2.87K|5|4|101b|1010 100b|
|3.48K|6|5|101b|1010 101b|
|4.12K|7|6|101b|1010 110b|
|4.75K|8|7|101b|1010 111b|
|5.49K|9|8|101b|1011 000b|
|6.19K|10|9|101b|1011 001b|
|6.98K|11|A|101b|1011 010b|
|7.87K|12|B|101b|1011 011b|
|8.87K|13|C|101b|1011 100b|
|10K|14|D|101b|1011 101b|
|11K|15|E|101b|1011 110b|



S23-1165-Rev. C, 25-Dec-2023 

Document Number: 63042 

**11** For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

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|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|
|---|---|---|---|---|---|---|
|**ADDRESS**|**PMBus COMMAND NAME**|**TYPE**|**DATA**<br>**FORMAT**<br>**(UNITS)**|**DEFAULT**<br>**VALUE IN**<br>**NVM**|**DEFAULT**|**VALID**<br>**RANGE**|
|01h|OPERATION|R/W|Byte|88h<br>(1000,1000)|[7] 1: PMBus unit output is on<br>[6] 0: output is turned off<br>immediately and any power down<br>sequencing commads are ignored<br>[5 : 4] 00: VOUTset by<br>VOUT_COMMAND<br>[3 : 2] 10: faults caused by selecting<br>VOUT_MARGIN_HIGH or<br>VOUT_MARGIN_LOW<br>as the nominal output voltage<br>source are acted upon according to<br>the settings of the<br>VOUT_OV_FAULT_RESPONSE and<br>VOUT_IV_FAULT_RESPONSE data<br>bytes<br>[1] 0: not used<br>[0]: reserved 02h|-|
|02h|ON_OFF_CONFIGURATION|R/W|Byte|1Fh<br>(0001,1111)|[7 : 5] 000: reserved<br>[4] 1: no power up until commanded<br>by the CONTROL and OPERATION<br>[3] 1: to start, the unit requires on/off<br>portion of the OPERATION<br>command<br>[2] 1: to start, the unit requires<br>CONTROL asserted<br>[1] 1: active high to start the unit<br>[0] 1: turn off VOUTas fast as<br>possible, ignore TOFF_DELAY and<br>TOFF_FALL|-|
|03h|CLEAR_FAULTS|Write|-|-|-|-|
|10h|WRITE_PROTECT|Write|Byte|00h<br>(0000,0000)|[7 : 0]: 0000,0000:<br>allows write to all registers|-|
|15h|STORE_USER_ALL|Write|-|-|-|-|
|16h|RESTORE_USER_ALL|Write|-|-|-|-|
|19h|CAPABILITY|Read|Byte|D0h<br>(1101,0000)|[7] 1: packet error checking is<br>supported<br>[6 : 5] 10: maximum supported<br>bus speed is 1 MHz<br>[4] 1: the unit has SMBALERT# pin<br>and supports SMBus alert response<br>protocol<br>[3] 0: numeric data is in LINEAR11,<br>LINEAR16, or DIRECT format<br>[2] 0: AVSBUS not supported<br>[1 : 0] 00: reserved|-|
|1Bh|SMBALERT_MASK|R/W|Block|0x0000<br>(0000,0000,<br>0000,0000)|-|-|
|20h|VOUT_MODE|Read|LINEAR16<br>(V)|17h<br>(0001,0111)|[7 : 5] 000: the unit uses<br>LINEAR16 format for<br>VOUTrelated commands<br>[4 : 0] 1,0111: five bit two is<br>complement exponent<br>equals -9 for VOUTrelated<br>commands|-|
|21h|VOUT_COMMAND|R/W|LINEAR16<br>(V)|0133h<br>(0000,0001,<br>0011,0011)|0.6 V|0.3 V to 14 V,<br>1.953 mV<br>resolution|



Document Number: 63042 

S23-1165-Rev. C, 25-Dec-2023 

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|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|
|---|---|---|---|---|---|---|
|**ADDRESS**|**PMBus COMMAND NAME**|**TYPE**|**DATA**<br>**FORMAT**<br>**(UNITS)**|**DEFAULT**<br>**VALUE IN**<br>**NVM**|**DEFAULT**|**VALID**<br>**RANGE**|
|22h|VOUT_TRIM|R/W|LINEAR16<br>(V)|xxxxh<br>(xxxx,xxxx,x<br>xxx,xxxx)|This command deviates from<br>standard PMBus 1.3 specifications;<br>a factory trim value varying by<br>devices|-2 V to 2 V,<br>1.953 mV<br>resolution|
|24h|VOUT_MAX|R/W|LINEAR16<br>(V)|1C00h<br>(0001,1100,<br>0000,0000)|14 V|0.3 V to 14 V,<br>1.953 mV<br>resolution|
|25h|VOUT_MARGIN_HIGH|R/W|LINEAR16<br>(V)|0142h<br>(0000,0001,<br>0100,0010)|0.63 V|0.3 V to 14 V,<br>1.953 mV<br>resolution|
|26h|VOUT_MARGIN_LOW|R/W|LINEAR16<br>(V)|0123h<br>(0000,0001,<br>0010,0011)|0.57 V|0.3 V to 14 V,<br>1.953 mV<br>resolution|
|27h|VOUT_TRANSITION_RATE|R/W|LINEAR11<br>(mV/μs)|E002h<br>(1110,0000,<br>0000,0010)|0.125 mV/μs|0.0625 mV/μs<br>to2 mV/μs,<br>0.0625 mV/μs<br>resolution|
|29h|VOUT_SCALE_LOOP|R/W|LINEAR11<br>(V/V)|E808h<br>(1110,1000,<br>0000,1000)|This command deviates from<br>standard PMBus 1.3 specifications;<br>1 V/V|0.125 V/V,<br>0.25 V/V,<br>0.5 V/V, 1 V/V|
|33h|FREQUENCY_SWITCH|R/W|LINEAR11<br>(kHz)|0258h<br>(0000,0010,<br>0101,1000)|600 kHz|300 kHz to<br>1500 kHz,<br>50 kHz<br>resolution|
|35h|VIN_ON|R/W|LINEAR11<br>(V)|F814h<br>(1111,1000,<br>0001,0100)|10 V|1 V to 80 V,<br>0.5 V<br>resolution|
|36h|VIN_OFF|R/W|LINEAR11<br>(V)|F812h<br>(1111, 1000,<br>0001, 0010)|9 V|1 V to 80 V,<br>0.5 V<br>resolution|
|37h|INTERLEAVE|R/W|Word|0100h<br>(0000,0001,<br>0000,0000)|[15 : 12] 0000: reserved<br>[11 : 8] 0001: sets unit as<br>Master or Slave<br>[7 : 4] 0000: sets unit as master<br>[3 : 0] 0000: not used|Standalone,<br>master, slave<br>in phase,<br>slave<br>180° out of<br>phase|
|40h|VOUT_OV_FAULT_LIMIT|R/W|LINEAR16<br>(V)|0161h<br>(0000,0001,<br>0011,0011)|0.69 V|0.3 V to 14 V,<br>1.953 mV<br>resolution|
|41h|VOUT_OV_FAULT_RESPONSE|R/W|Byte|F8h<br>(1111,1000)|The device’s output is disabled<br>while the fault is present. Operation<br>resumes and the output is enabled<br>when the fault condition no longer<br>exists. It attempts to restart<br>continuously, without limitation, until<br>it is commanded off (by the<br>CONTROL pin or OPERATION<br>command or both), bias power is<br>removed, or another fault condition<br>causes the unit to shut down|00h, 16h,<br>22h,<br>36h, C0h,<br>D6h,<br>E2h, F6h,<br>F8h|
|42h|VOUT_OV_WARN_LIMIT|R/W|LINEAR16<br>(V)|0151h<br>(0000,0001,<br>0101,0001)|0.66 V|0.3 V to 14 V,<br>1.953 mV<br>resolution|
|43h|VOUT_UV_WARN_LIMIT|R/W|LINEAR16<br>(V)|0114h<br>(0000,0001,<br>0001,0100)|0.54 V|0 V to 14 V,<br>1.953 mV<br>resolution|



S23-1165-Rev. C, 25-Dec-2023 

Document Number: 63042 

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**SiC454** 

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|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|
|---|---|---|---|---|---|---|
|**ADDRESS**|**PMBus COMMAND NAME**|**TYPE**|**DATA**<br>**FORMAT**<br>**(UNITS)**|**DEFAULT**<br>**VALUE IN**<br>**NVM**|**DEFAULT**|**VALID**<br>**RANGE**|
|44h|VOUT_UV_FAULT_LIMIT|R/W|LINEAR16<br>(V)|00F5h<br>(0000,0000,<br>1111,0101)|0.48 V|0 V to 14 V,<br>1.953 mV<br>resolution|
|45h|VOUT_UV_FAULT_RESPONSE|R/W|Byte|B9h<br>(1011,1001)|The device shuts down (disables the<br>output) and attempts to restart<br>continuously, without limitation, until<br>it is commanded off (by the EN pin<br>or<br>OPERATION command or both),<br>bias power is removed, or another<br>fault condition causes the unit to<br>shut down. 20 ms delay|00h, 16h,<br>22h, 36h,<br>B9h, C0h,<br>D6h, E2h,<br>F6h|
|46h|IOUT_OC_FAULT_LIMIT|R/W|LINEAR11<br>(A)|SiC450:F87<br>0h<br>(1111,1000,<br>0111,0000)<br>SiC451:<br>F846h<br>(1111,1000,<br>0100,0110)<br>SiC453:<br>F82Ah<br>(1111,1000,<br>0010,1010)<br>SiC454:<br>F821h<br>(1111,1000,<br>0010,0001)|SiC450: 56 A<br>SiC451: 35 A<br>SiC453: 21 A<br>SiC454: 17A|0 A to 127 A,<br>0.5 A<br>resolution|
|47h|IOUT_OC_FAULT_RESPONSE|R/W|Byte|A1h<br>(1010,0001)|This command deviates from<br>standard PMBus 1.3 specifications.<br>The device continues operation for<br>128 consecutive OC cycles and then<br>shut down. Waiting for 20 ms, it<br>hiccups until the fault condition no<br>longer exists|00h, 16h,<br>22h, 36h,<br>A1h, C0h,<br>D6h, E2h,<br>F6h,<br>F8h|
|4Ah|IOUT_OC_WARN_LIMIT|R/W|LINEAR11<br>(A)|SiC450:<br>F868h<br>(1111,1000,<br>0110,1000)<br>SiC451:<br>F841h<br>(1111,1000,<br>0100,0010)<br>SiC453:<br>F827h<br>(1111,1000,<br>0001,1111)<br>SiC454:<br>F81Fh<br>(1111,1000,<br>0001,1111)|SiC450: 52 A<br>SiC451: 32.5 A<br>SiC453: 19.5 A<br>SiC454: 15.5 A|0 A to 127 A,<br>0.5 A<br>resolution|
|4Fh|OT_FAULT_LIMIT|R/W|LINEAR11<br>(°)|007Dh<br>(0000,0000,<br>0111,1101)|125 °C|0 °C to 150<br>°C, 1 °C<br>resolution|



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Document Number: 63042 

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|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|
|---|---|---|---|---|---|---|
|**ADDRESS**|**PMBus COMMAND NAME**|**TYPE**|**DATA**<br>**FORMAT**<br>**(UNITS)**|**DEFAULT**<br>**VALUE IN**<br>**NVM**|**DEFAULT**|**VALID**<br>**RANGE**|
|50h|OT_FAULT_RESPONSE|R/W|Byte|F9h<br>(1111,1001)|The device’s output is disabled<br>while the fault is present. Operation<br>resumes and the output is enabled<br>when the fault condition no longer<br>exists. It attempts to restart<br>continuously, without limitation, until<br>it is commanded off (by the EN pin<br>or OPERATION command or both),<br>bias power is removed, or another<br>fault condition causes the unit to<br>shut down|00h, 16h,<br>22h, 36h,<br>C0h, D6h,<br>E2h, F6h,<br>F9h|
|51h|OT_WARN_LIMIT|R/W|LINEAR11<br>(°)|0069h<br>(0000,0000,<br>0110,1001)|105 °C|0 °C to 150<br>°C, 1 °C<br>resolution|
|55h|VIN_OV_FAULT_LIMIT|R/W|LINEAR11<br>(V)|F81Eh<br>(1111,1000,<br>0001,1110)|15 V|1 V to 80 V,<br>0.5 V<br>resolution|
|56h|VIN_OV_FAULT_RESPONSE|R/W|Byte|B8h<br>(1011,1000)|This command deviates from<br>standard PMBus 1.3<br>specifications.The device’s output is<br>disabled while the fault is present.<br>Operation resumes and the output is<br>enabled when the fault condition no<br>longer exists. It does not attempt to<br>restart. The output remains disabled<br>until the fault is cleared|00h, 16h,<br>22h, 36h,<br>B8h, C0h,<br>D6h, E2h,<br>F6h|
|58h|VIN_UV_WARN_LIMIT|R/W|LINEAR11<br>(V)|F812h<br>(1111,1000,<br>0001,0010)|9 V|1 V to 80 V,<br>0.5 V<br>resolution|
|5Dh|IIN_OC_WARN_LIMIT|R/W|LINEAR11<br>(A)|F80Ah<br>(1111,1000,<br>0000,1010)|5 A|0 A to 127 A,<br>0.5 A<br>resolution|
|5Eh|POWER_GOOD_ON|R/W|LINEAR16<br>(V)|0114h<br>(0000,0001,<br>0001,0100)|0.54 V|0.24 V to 14 V,<br>1.953 mV<br>resolution|
|5Fh|POWER_GOOD_OFF|R/W|LINEAR16<br>(V)|0105h<br>(0000,0001,<br>0000,0101)|0.51 V|0.24 V to 14 V,<br>1.953 mV<br>resolution|
|60h|TON_DELAY|R/W|LINEAR11<br>(ms)|0000h<br>(0000,0000,<br>0000,0000)|0 ms|0 ms to<br>127 ms, 1 ms<br>resolution|
|61h|TON_RISE|R/W|LINEAR11<br>(ms)|0005h<br>(0000,0000,<br>0000,0101)|5 ms|0 ms to<br>127 ms, 1 ms<br>resolution|
|62h|TON_MAX_FAULT_LIMIT|R/W|LINEAR11<br>(mS)|0014h<br>(0000,0000,<br>0001,0100)|20 ms|0 ms to<br>127 ms, 1 ms<br>resolution|
|63h|TON_MAX_FAULT_RESPONSE|R/W|Byte|B9h<br>(1011,1001)|The device shuts down (disables the<br>output). It attempts to restart<br>continuously, without limitation, until<br>it is commanded off (by the EN pin<br>or OPERATION command or both),<br>bias power is removed, or another<br>fault condition causes the unit to<br>shut down. 20 ms delay|80h, 83h,<br>86h, 88h,<br>89h, 8Ah,<br>8Bh, B9h|
|64h|TOFF_DELAY|R/W|LINEAR11<br>(ms)|0000h<br>(0000,0000,<br>0000,0000)|0 ms|0 ms to<br>127 ms, 1 ms<br>resolution|



Document Number: 63042 

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|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|**PMBus COMMAND LIST**|
|---|---|---|---|---|---|---|
|**ADDRESS**|**PMBus COMMAND NAME**|**TYPE**|**DATA**<br>**FORMAT**<br>**(UNITS)**|**DEFAULT**<br>**VALUE IN**<br>**NVM**|**DEFAULT**|**VALID**<br>**RANGE**|
|65h|TOFF_FALL|R/W|LINEAR11<br>(ms)|0005h<br>(0000,0000,<br>0000,0101)|5 ms|0 ms to<br>127 ms, 1 ms<br>resolution|
|66h|TOFF_MAX_WARN_LIMIT|R/W|LINEAR11<br>(ms)|003Ch<br>(0000,0000,<br>0011,1100)|60 ms|0 ms to<br>127 ms, 1 ms<br>resolution|
|78h|STATUS_BYTE|Read|Byte|00h<br>(0000,0000)|No faults|-|
|79h|STATUS_WORD|Read|Word|0000h<br>(0000,0000,<br>0000,0000)|No faults|-|
|7Ah|STATUS_VOUT|Read|Byte|00h<br>(0000,0000)|No faults|-|
|7Bh|STATUS_IOUT|Read|Byte|00h<br>(0000,0000)|No faults|-|
|7Ch|STATUS_INPUT|Read|Byte|00h<br>(0000,0000)|No faults|-|
|7Dh|STATUS_TEMPERATURE|Read|Byte|00h<br>(0000,0000)|No faults|-|
|7Eh|STATUS_CML|Read|Byte|00h<br>(0000,0000)|No faults|-|
|80h|STATUS_MFR_SPECIFIC|Read|Byte|00h<br>(0000,0000)|No faults|-|
|88h|READ_VIN|Read|LINEAR11<br>(V)|n/a|n/a|0 V to 80 V|
|89h|READ_IIN|Read|ULINEAR<br>11 (A)|n/a|n/a|exp:<br>(-4) to (-16)|
|8Bh|READ_VOUT|Read|LINEAR16<br>(V)|n/a|n/a|0 V to 48 V|
|8Ch|READ_IOUT|Read|ULINEAR<br>11 (A)|n/a|n/a|exp:<br>(-4 ) to (-10)|
|8Dh|READ_TEMPERATURE|Read|LINEAR11<br>(°)|n/a|n/a|(-50)° to 150°|
|94h|READ_DUTY_CYCLE|Read|LINEAR11<br>(%)|n/a|n/a|0 % to 100 %|
|96h|READ_POUT|Read|ULINEAR<br>11 (W)|n/a|n/a|exp:<br>(-4) to (-16)|
|97h|READ_PIN|Read|ULINEAR<br>11 (W)|n/a|n/a|exp:<br>(-4) to (-16)|
|98h|PMBUS_REVISION|Read|Byte|33h<br>(0011,0011)|[7  :4] 0011: part I revision 1.3<br>[3 : 0] 0011: part II revision 1.3||
|9Eh|MFR_SERIAL|R/W|Block|n/a|For user to store customized<br>information||
|ADh|IC_DEVICE_ID|R/W|Block|0104h|-||
|D7h|MFR_BASE_ADDRESS|Pins<br>program|7-bit|10h|-||
|E2h|MFR_BASE_ADDRESS_2|Pins<br>program|7-bit|50h|-||



S23-1165-Rev. C, 25-Dec-2023 

Document Number: 63042 

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## **PMBus COMMAND DETAILS** 

## **OPERATION (01 h)** 

The OPERATION command sets the operational state of the regulator. It is used for the following functions: 

- Turn the regulator output on and off in conjunction with the input from EN signal 

- Set the output voltage with upper or lower margins 

- Select the fault handling behavior when fault is caused by margining state 

|**COMMAND**|**COMMAND**|**COMMAND**|**OPERATION**|**OPERATION**|**OPERATION**|**OPERATION**|**OPERATION**|**OPERATION**|**OPERATION**|**OPERATION**|**OPERATION**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|Bitposition|||7||6|5|4|3|2|1|0|
|Function|||On/off||Off B|Margin||MRGNFLT||Nouse|RSV|
|Default(88 h)|||1||0|0|0|1|0|0|0|
|**Bit Description (default setting in bold)**||||||||||||
|**BITS**|**SYMBOL**|**VALUE**||**ACTION**||||||||
|7|On/off|0b||Output is disabled||||||||
|||**1b**||**Output is enabled**||||||||
|6|Off B|**0b**||**Output is turned off immediately andpower off sequence commands ignored**||||||||
|||1b||Regulator turns off following the TOFF_DELAY and TOFF_FALL command||||||||
|5 : 4|Margin|**00b**||**Output voltage is set by the PMBus VOUT_COMMAND data**||||||||
|||01b||Output voltage is set bythe PMBus VOUT_MARGIN_LOW data||||||||
|||10b||Output voltage is set bythe PMBus VOUT_MARGIN_HIGH data||||||||
|||11b||Not supported||||||||
|3 : 2|MRGNFLT|00b||Not supported||||||||
|||01b||Faults caused by selecting VOUT_MARGIN_HIGH or VOUT_MARGIN_LOW as the nominal<br>output voltage source are ignored||||||||
|||**10b**||**Faults caused by selecting VOUT_MARGIN_HIGH or VOUT_MARGIN_LOW as the**<br>**nominal output voltage source are acted upon according to the settings of the**<br>**VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_RESPONSE**||||||||
|||11b||Not supported||||||||
|1|Nouse|x||Not used||||||||
|0|RSV|x||Reserved||||||||



## **ON_OFF_CONFIGURATION (02 h)** 

The ON_OFF_CONFIG command configures the combination of EN pin input and PMBus commands needed to turn the unit on and off. This includes how the unit responds when power is applied. 

|**COMMAND**|**ON/OFF_CONFIGURATION**|**ON/OFF_CONFIGURATION**|**ON/OFF_CONFIGURATION**|**ON/OFF_CONFIGURATION**|**ON/OFF_CONFIGURATION**|**ON/OFF_CONFIGURATION**|**ON/OFF_CONFIGURATION**|**ON/OFF_CONFIGURATION**|
|---|---|---|---|---|---|---|---|---|
|Bitposition|7|6|5|4|3|2|1|0|
|Function|RSV|||PU|CMD|EN|ENPOL|Off B1|
|Default(1Fh)|0|0|0|1|1|1|1|1|



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## **Bit Description (default setting in bold)** 

|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|---|---|---|---|
|7 : 5|RSV|000b|Reserved|
|4|PU|0b|Regulatorpowers upanytimepower ispresent regardless of state of the EN signalpin|
|||**1b**|**Regulator does not power up until commanded by the CONTROLEN**<br>**pin and OPERATION command**|
|3|CMD|0b|Regulator ignores the “on” bit in the OPERATION command|
|||**1b**|**Regulator responds the “on” bit in the OPERATION command**|
|2|EN|0b|Regulator ignores the EN pin. Power conversion is controlled only by the OPERATION<br>command|
|||**1b**|**Regulator requires the ENpin to be asserted to start the unit**|
|1|ENPOL|0b|EN signal is active low|
|||**1b**|**EN signal is active high**|
|0|OFFB1|0b|Regulator turns off following the tOFF_DELAYand tOFF_FALLcommand when EN signal is used<br>to turn off|
|||**1b**|**Regulator turns off immediately**|



## **CLEAR_FAULTS (03 h)** 

The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all status registers simultaneously. At the same time, the device negates (clears, releases) its SALRT ALERT# signal output if the device is asserting the SALRT ALERT# signal. 

## **WRITE_PROTECT (10 h)** 

The WRITE_PROTECT command is used to control writing to the PMBus device. The intent of this command is to provide protection against accidental changes. This command is not intended to provide protection against deliberate or malicious changes to a device’s configuration or operation. 

|**COMMAND**|**WRITE_PROTECT**|**WRITE_PROTECT**|**WRITE_PROTECT**|**WRITE_PROTECT**|**WRITE_PROTECT**|**WRITE_PROTECT**|**WRITE_PROTECT**|**WRITE_PROTECT**|
|---|---|---|---|---|---|---|---|---|
|Bit position|7|6|5|4|3|2|1|0|
|Function|WTPRT|||Nouse|||||
|Default (00h)|0|0|0|0|0|0|0|0|



## **Bit Description (default setting in bold)** 

|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|---|---|---|---|
|7 : 5|WTPRT|**000b**|**Enable writes to all commands**|
|||100b|Disable all writes except to the WRITE_PROTECT command|
|||010b|Disable all writes except to the WRITE_PROTECT and OPERATION commands|
|||001b|Disable all writes except to the WRITE_PROTECT, OPERATION, ON_OFF_CONFIG and<br>VOUT_COMMANDcommands|
|4 : 0|Nouse|00000b|Not used|



## **STORE_USER_ALL (15 h)** 

The STORE_USER_ALL command instructs the PMBus device to copy the entire contents of the operating memory to the matching locations in the non-volatile User Store memory. Any items in operating memory that do not have matching locations in the User Store are ignored. 

## **RESTORE_USER_ALL (16 h)** 

The RESTORE_USER_ALL command instructs the PMBus device to copy the entire contents of the nonvolatile user store memory (NVM) to the matching locations in the operating memory. The values in the operating memory are overwritten by the value retrieved from the user store. This feature is protected by the EEPROM_PASSWORD (DBh) command, see the section below for more information. Any items in user store that do not have matching locations in the operating memory are ignored, see the summary table for details. 

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## **CAPABILITY (19 h)** 

The CAPABILITY command provides a way for a host system to determine some key capabilities of the PMBus device. This is a read only register. 

|**COMMAND**|**WRITE_PROTECT**|**WRITE_PROTECT**|**WRITE_PROTECT**|**WRITE_PROTECT**|**WRITE_PROTECT**|**WRITE_PROTECT**|**WRITE_PROTECT**|**WRITE_PROTECT**|
|---|---|---|---|---|---|---|---|---|
|Bit position|7|6|5|4|3|2|1|0|
|Function|PEC|SPD||ALRT|NFMT|AVS|RSV||
|Default (D0h)|1|1|0|1|0|0|0|0|



## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|7|PEC|1b|Packet error checkingis supported|
|6 : 5|SPD|10b|Maximum supported bus speed is 1 MHz|
|4|ALRT|1b|The unit has ALERT#pin and supports PMBus alert responseprotocol|
|3|NFMT|0b|Numeric data is in LINEAR11, LINEAR16, or DIRECT format|
|2|AVS|0b|AVSBUS not supported|
|1 : 0|RSV|00b|Reserved|



## **SMBALERT_MASK (1Bh)** 

The SMBALERT_MASK command may be used to prevent a warning or fault condition from asserting the SMBALERT# signal. The command format used to block a status bit or bits from causing the SMBALERT# signal to be asserted is shown in Fig. 9. The bits in the mask byte align with the bits in the corresponding status register. For example, if the STATUS_TEMPERATURE command code were sent with the mask byte 01000000b, then an over temperature warning OT_WARNING (overtemperature warning) condition would be blocked from asserting SMBALERT#. 

**==> picture [468 x 37] intentionally omitted <==**

**----- Start of picture text -----**<br>
7 1 1 8 1 8 1 8 1<br>Slave  SMBalert_mask    Status_x<br>S  W  A  A  A  Mask BYTE  A P<br>  Address  Command_code         Command code<br>**----- End of picture text -----**<br>


**Fig. 9 - SMBALSER_MASK Command Packet Format** 

The command format used by the host to determine the SMALER_MASK setting for a given status register is shown in Fig. 10. 

**==> picture [468 x 92] intentionally omitted <==**

**----- Start of picture text -----**<br>
7 1 1 8 1 8 1 8 1<br>Slave  SMBalert_Mask         Block count  Status_x<br>S  W A  A  A  A<br>  address  Command_code  (=1)  Command code   �<br>7 1 1 8 1 8 1<br>S Slave Block count  N<br>R  A  A  Mask byte  P<br>r    address  (=1)  A<br>**----- End of picture text -----**<br>


**Fig. 10 - Retrieving the SMBALSER_MASK Setting for a Given Status Register** 

## **VOUT_MODE (20 h)** 

The PMBus specification dictates that the data word for the VOUT_MODE command is one byte that consists of a 3-bit mode and 5-bit exponent parameter, as shown below. The 3-bit mode sets whether the device uses the linear or direct modes for output voltage related commands. The 5-bit parameter sets the exponent value for the linear data mode. The mode and exponent parameters are fixed and do not permit the user to change the values. 

This is a read only register 

|**COMMAND**|**WRITE_PROTECT**|**WRITE_PROTECT**|**WRITE_PROTECT**|**WRITE_PROTECT**|**WRITE_PROTECT**|**WRITE_PROTECT**|**WRITE_PROTECT**|**WRITE_PROTECT**|
|---|---|---|---|---|---|---|---|---|
|Bit position|7|6|5|4|3|2|1|0|
|Function|Mode|||EXP|||||
|Default (D0h)|0|0|0|1|0|1|1|1|



Document Number: 63042 

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## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|7 : 5|Mode|000b|The unit uses ULINEAR16 format for VOUTrelated commands|
|4 : 0|EXP|10111b|5-bit two’s complement binary integer equals -9 for VOUTrelated commands|



## **VOUT_COMMAND (21 h)** 

The VOUT_COMMAND is used to directly set the output voltage using the ULINEAR16 format, which is a 16- bit unsigned integer. This is a read and write register. The output voltage, in volts, is calculated from the equation: 

VOUT_SET = VOUT_COMMAND x 2[N] 

## Where: 

VOUT_SET is the set output voltage in volt 

VOUT_COMMAND is the 16- bit unsigned binary integer specified in the command 

N is a 5- bit two’s complement binary integer specified in VOUT mode [4 : 0] 

|**COMMAND**|**VOUT COMMAND**|**VOUT COMMAND**|**VOUT COMMAND**|**VOUT COMMAND**|**VOUT COMMAND**|**VOUT COMMAND**|**VOUT COMMAND**|**VOUT COMMAND**|**VOUT COMMAND**|**VOUT COMMAND**|**VOUT COMMAND**|**VOUT COMMAND**|**VOUT COMMAND**|**VOUT COMMAND**|**VOUT COMMAND**|**VOUT COMMAND**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Bit position|7|6|5|4|3|2|1|0|7|6|5|4|3|2|1|0|
|Function|Data byte high||||||||Data byte low||||||||
|Default (133h)|0|0|0|0|0|0|0|1|0|0|1|1|0|0|1|1|



## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**FORMAT**|**VALUE**|**ACTION**|
|15 : 0|ULINEAR 16|0133h|VOUT_COMMAND is specified as 307 x 2-9= 0.6 V|



The output voltage’s range is 0.3 V to 14 V, resolution is 1.953 mV, and its NVM register default store value is 0133h equivalent to 0.6 V. 

## **VOUT_TRIM (22 h)** 

The VOUT_TRIM command is used to apply a fixed offset voltage to the output voltage command value. This is a read and write register. The VOUT_TRIM has two data bytes formatted as a two’s complement binary integer (SLINEAR16 format). It is most typically used by the end user to trim the output voltage at the time the PMBus device is assembled into the end user’s system. 

The VOUT_TRIM command deviates from standard PMBus 1.3 specifications, at which it requires adding an integer calculating from the expected offset voltage and the VOUT_SCALE_LOOP to VOUT_TRIM’s NVM register default store value varying by devices. The effect of this command on the output voltage, in volts, is calculated from the equation: 

**==> picture [141 x 23] intentionally omitted <==**

## Where: 

- voltage is the fixed offset voltage to the output voltage in volt 

 V is the 16-bit two’s complement integer specified in VOUT_TRIM 

VOUT_SCALE_LOOP is the dimensionless scale factor specified in VOUT_SCALE_LOOP command N is a 5-bit two’s complement binary integer specified in VOUT_MODE [4:0]. 

|**COMMAND**|**VOUT TRIM**|**VOUT TRIM**|**VOUT TRIM**|**VOUT TRIM**|**VOUT TRIM**|**VOUT TRIM**|**VOUT TRIM**|**VOUT TRIM**|**VOUT TRIM**|**VOUT TRIM**|**VOUT TRIM**|**VOUT TRIM**|**VOUT TRIM**|**VOUT TRIM**|**VOUT TRIM**|**VOUT TRIM**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Bit position|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|Function|sign|data|||||||||||||||
|Default (0000h)|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|0|



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## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**FORMAT**|**VALUE**|**ACTION**|
|15 : 0|ULINEAR 16|0000h|V is 0 V|



The offset voltage’s range is -2 V to 2 V, resolution is 1.953 mV, and its NVM register default store value is a factory trim value varying by devices. The users need to calculate a 16-bit two’s complement integer number following the above equation and add the number to the factory trim value, so as to achieve the expected offset voltage to the output voltage. 

## **VOUT_MAX (24 h)** 

The VOUT_MAX command sets an upper limit on the output voltage the unit can command regardless of any other commands or combinations. The intent of this command is to provide a safeguard against a user accidentally setting the output voltage to a possibly destructive level rather than to be the primary output overvoltage protection. This is a read and write register. 

The VOUT_MAX uses ULINEAR16 format, which is a 16- bit unsigned integer according to the setting of the VOUT_MAX command. 

## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**FORMAT**|**VALUE**|**ACTION**|
|15 : 0|Ulinear 16|1C00h|The VOUT_MAX is specified as 14 V|



The VOUT_MAX range is 0.3 V to 14 V, resolution is 1.953 mV, and its NVM register default store value is 1C00h equivalent to 14 V. 

## **VOUT_MARGIN_HIGH (25 h)** 

The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed when the OPERATION command is set to “margin high”. This is a read and write register. 

The VOUT_MARGIN_HIGH uses ULINEAR16 format, which is a 16-bit unsigned integer according to the setting of the VOUT_MODE command. 

## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**FORMAT**|**VALUE**|**ACTION**|
|15 : 0|Ulinear 16|0142h|The VOUT_MARGIN_HIGH is specified as 0.63 V|



The VOUT_MARGIN_HIGH range is 0.3 V to 14 V, resolution is 1.953 mV, and its NVM register default store value is 0142h equivalent to 0.63 V. 

## **VOUT_MARGIN_LOW (26 h)** 

The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed when the OPERATION command is set to margin low. This is a read and write register. 

The VOUT_MARGIN_LOW uses ULINEAR16 format, which is a 16-bit unsigned integer according to the setting of the VOUT_MODE command. 

## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**FORMAT**|**VALUE**|**ACTION**|
|15 : 0|Ulinear 16|0123h|The VOUT_MARGIN_LOW is specified as 0.57 V|



The VOUT_MARGIN_LOW range is 0.3 V to 14 V, resolution is 1.953 mV, and its NVM register default store value is 0123h equivalent to 0.57 V. 

## **VOUT_TRANSITION_RATE (27 h)** 

The VOUT_TRANSITION_RATE command sets the rate in mV/μs at which the output voltage should change voltage when a PMBus device receives either a VOUT_COMMAND or OPERATION (margin high, margin low) that causes the output voltage to change. This commanded rate of change does not apply when the unit is commanded to turn on or to turn off. This is a read and write register. 

The VOUT_TRANSITION_RATE uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the VOUT_TRANSITION_RATE command is constant as 5’b11100, that is, -4 in decimal. The LINEAR11 format of the two data bytes is illustrated in table below. 

Document Number: 63042 

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**==> picture [77 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
www.vishay.com<br>**----- End of picture text -----**<br>


**Table - LINEAR11 Numeric Format Data Bytes** 

|**COMMAND**|**VOUT_TRANSITION_RATE**|**VOUT_TRANSITION_RATE**|**VOUT_TRANSITION_RATE**|**VOUT_TRANSITION_RATE**|**VOUT_TRANSITION_RATE**|**VOUT_TRANSITION_RATE**|**VOUT_TRANSITION_RATE**|**VOUT_TRANSITION_RATE**|**VOUT_TRANSITION_RATE**|**VOUT_TRANSITION_RATE**|**VOUT_TRANSITION_RATE**|**VOUT_TRANSITION_RATE**|**VOUT_TRANSITION_RATE**|**VOUT_TRANSITION_RATE**|**VOUT_TRANSITION_RATE**|**VOUT_TRANSITION_RATE**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Bit position|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|Function|EXP|||||MAN|||||||||||
|Default (E002h)|1|1|1|0|0|0|0|0|0|0|0|0|0|0|1|0|



## **Bit Description** 

|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|---|---|---|---|
|15|EXP SGN|1b|Exponent value with negative sign|
|14 : 11|EXP|1100b|Five 5-bit two’s complement exponent equals -4 for VOUT_TRANSITION_RATE command|
|10|MAN SGN|0b|Mantissa value with positive sign|
|19 : 0|MAN DATA|00, 0000, 0010b|Eleven 11-bit two’s complement mantissa equals 2 for VOUT_TRANSITION_RATE<br>command|



The VOUT_TRANSITION_RATE range is 0.0625 - 2 mV/μs, resolution is 0.0625 mV/μs, and its NVM register default store value is E002h equivalent to 0.125 mV/μs. Any commands out of the valid range or with incorrect resolution will be ignored and reported. 

## **VOUT_SCALE_LOOP (29 h)** 

The VOUT_SCALE_LOOP command deviates from standard PMBus 1.3 specifications. The VOUT_SCALE_LOOP  command is used to scale down both the VOUT_COMMAND and the sense differential output voltage at the unit input, so as to extend operational range of the PMBus unit to reach the maximum output voltage 12 V without the requirement of external resistor divider on board. This is a read and write register. 

The VOUT_SCALE_LOOP uses LINEAR11 format, which has two data bytes with an 11- bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the VOUT_SCALE_LOOP command is constant as 5’b11101, that is, -3 in decimal. 

The LINEAR11 format of the two data bytes is illustrated in Table “LINEAR11 Numeric Format Data Bytes”. 

## **Table - VOUT_SCALE_LOOP Look Up** 

|**Table - VOUT_SCALE_LOOP Look Up**|||
|---|---|---|
|**SET OUTPUT VOLTAGE (V)**|**SCALE DOWN FACTOR (V/V)**|**VOUT_SCALE_LOOP BITS [15 : 0]**|
|0.3 V < VOUT< 1.8 V|1.0|E808h|
|1.8 VVOUT< 3.3 V|0.5|E804h|
|3.3 VVOUT 5.0 V|0.25|E802h|
|5.0 VVOUT 12.0 V|0.125|E801h|



## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|15 to 0|Linear 11|E808h|The VOUT_SCALE_LOOP is specified as 1 V/V|



The VOUT_SCALE_LOOP offers four options of scale down factor: 1.0 V/V, 0.5 V/V, 0.25 V/V, and 0.125 V/V. When VOUT is set by a resistor between VSET pin and ground, the value of VOUT_SCALE_LOOP is automatically chosen according to the “VOUT_SCALE_LOOP look up” table. When VOUT is set by PMBus VOUT_COMMAND, the value of the VOUT_SCALE_LOOP shall be updated according to the “VOUT_SCALE_LOOP look up” table. 

The VOUT_SCALE_LOOP NVM register default store value is E808h equivalent to 1.0 V/V. Any commands out of the valid options will be ignored and reported. 

## **FREQUENCY_SWITCH (33 h)** 

The FREQUENCY_SWITCH command sets the switching frequency, in kHz, of the PMBus unit. This is a read and write register. The FREQUENCY_SWITCH uses LINEAR11 format, which has two data bytes with an 11- bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the FREQUENCY_SWITCH command is constant as 5’b00000, that is, 0 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. 

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## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|15 : 0|Linear 11|0258h|FREQUENCY_SWITCH is specified 600 kHz.|



The FREQUENCY_SWITCH range is 300 kHz to 1500 kHz, resolution is 50 kHz, and its NVM register default store value is 0258h equivalent to 600 kHz. Any commands out of the valid range or with incorrect resolution will be ignored and reported. 

## **VIN_ON (35 h)** 

The VIN_ON command sets the value of the input voltage, in volt, at which the PMBus unit should start power conversion. This is a read and write register. The VIN_ON uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the VIN_ON command is constant as 5’b11111, that is, -1 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. 

## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|15 : 0|Linear 11|F814h|The VIN_ON is specified as 10 V|



The VIN_ON range is 1 V to 80 V, resolution is 0.5 V, and its NVM register default store value is F814h equivalent to 10 V. Any commands out of the valid range or with incorrect resolution will be ignored and reported. 

## **VIN_OFF (36 h)** 

The VIN_OFF command sets the value of the input voltage, in volt, at which the PMBus unit, once operation has started, should stop power conversion. This is a read and write register. The VIN_OFF uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the VIN_OFF command is constant as 5’b11111, that is, -1 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. 

## **Bit Description** 

|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|---|---|---|---|
|15 : 0|Linear 11|F812h|The VIN_OFF is specified as 9 V|



The VIN_OFF range is 1 V to 80 V, resolution is 0.5 V, and its NVM register default store value is F812h equivalent to 9 V. Any commands out of the valid range or with incorrect resolution will be ignored and reported. 

## **INTERLEAVE (37 h)** 

The INTERLEAVE command deviates from standard PMBus 1.3 specifications. The INTERLEAVE command is used to sets the mode of switching frequency and phase, at which the PMBus unit, once operation has started, should use to generate switching frequency and phase angle. This is a read and write register. 

The INTERLEAVE commands offer four modes of switching configuration: STANDALONE, MASTER, SLAVE in phase, and SALVE 180° out of phase. 

The description of all four modes and the corresponding INTERLEAVE command is listed in the table below. 

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## **INTERLEAVE COMMAND AND MODE OF SWITCHING FREQUENCY GENERATION** 

|**INTERLEAVE COMMAND AND MODE OF SWITCHING FREQUENCY GENERATION**|**INTERLEAVE COMMAND AND MODE OF SWITCHING FREQUENCY GENERATION**|**INTERLEAVE COMMAND AND MODE OF SWITCHING FREQUENCY GENERATION**|**INTERLEAVE COMMAND AND MODE OF SWITCHING FREQUENCY GENERATION**|**INTERLEAVE COMMAND AND MODE OF SWITCHING FREQUENCY GENERATION**|**INTERLEAVE COMMAND AND MODE OF SWITCHING FREQUENCY GENERATION**|
|---|---|---|---|---|---|
|||**DESCRIPTION**|||**INTERLEAVE BITS**<br>**[15 : 0]**|
|STANDALONE||The value of unit switching frequency is set by resistance of a resistor connected to RT/SYNC<br>unit designated pin. The setting value of the switching frequency will be overridden after the<br>PMBus unit receiving the PMBus command FREQUENCY_SWITCH command. The RT/SYNC pin<br>shall not be used for other purposes|||0000h|
|MASTER||The value of unit switching frequency is set by resistance of a resistor connected to RT/SYNC<br>pin. The setting value of the switching frequency will be overridden after the PMBus unit receiving<br>the PMBus command FREQUENCY_SWITCH command. After inside power VDDof the unit is<br>above its under voltage level, the RT/SYNC pin will output a 50% duty cycle pulse signal in phase<br>with the switching frequency, which may be used to drive other units set as the SLAVE mode by<br>INTERLEAVE command. The RT/SYNC pin shall not be used for other purposes|||0100h|
|SLAVE in phase||The value of unit switching frequency is set by resistance of a resistor connected to RT/SYNC<br>pin. The setting value of the switching frequency will be overridden after the PMBus unit receiving<br>the PMBus command FREQUENCY_SWITCH command. When an external pulse switching<br>signal is connected to the /SYNC pin, the unit will synchronize its switching frequency to the<br>external pulse switching signal with 0º phase difference. The RT/SYNC pin shall not be used for<br>other purpose|||0120h|
|SLAVE 180º out of<br>phase||The value of unit switching frequency is set by resistance of a resistor connected to RT/SYNC<br>pin. The setting value of the switching frequency will be overridden after the PMBus unit receiving<br>the PMBus command FREQUENCY_SWITCH command. When an external pulse switching<br>signal is connected to the /SYNC pin, the unit will synchronize its switching frequency to the<br>external pulse switching signal with 180º phase difference. The RT/SYNC pin shall not be used<br>for other purposes|||0121h|
|**Bit Description**||||||
|**BITS**|**SYMBOL**||**VALUE**|**ACTION**||
|15:0|Linear 11||0100h|The INTERLEAVE is specified as MASTER mode||



The INTERLEAVE NVM register default store value is 0100h equivalent to MASTER mode. Any commands out of the options will be ignored and reported. 

## **VOUT_OV_FAULT_LIMIT (40 h)** 

The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured at the sense of output pins that causes an output overvoltage fault. This is a read and write register. 

The VOUT_OV_FAULT_LIMIT uses ULINEAR16 format, which is a 16-bit unsigned integer according to the setting of the VOUT_MODE command. 

## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|15:0|Ulinear 16|0161h|The VOUT_OV_FAULT_LIMIT is specified as 0.69 V|



The VOUT_OV_FAULT_LIMIT range is 0.3 V to 14 V, resolution is 1.953 mV, and its NVM register default store value is 0161h equivalent to 0.69 V. 

## **VOUT_OV_FAULT_RESPONSE (41h)** 

The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output overvoltage fault. This is a read and write register and the NVM register default store value is F8h. 

|**COMMAND**|**VOUT_OV_FAULT_RESPONSE**|**VOUT_OV_FAULT_RESPONSE**|**VOUT_OV_FAULT_RESPONSE**|**VOUT_OV_FAULT_RESPONSE**|**VOUT_OV_FAULT_RESPONSE**|**VOUT_OV_FAULT_RESPONSE**|**VOUT_OV_FAULT_RESPONSE**|**VOUT_OV_FAULT_RESPONSE**|
|---|---|---|---|---|---|---|---|---|
|Bit position|7|6|5|4|3|2|1|0|
|Function|OVRSP||OVRTY|||OVDLY|||
|Default (F8h)|1|1|1|1|1|0|0|0|



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## **Supported Commands** 

|**OVRSP**|**OVRSP**|**OVRTY**|**OVRTY**|**OVRTY**|**OVDLY**|**OVDLY**|**OVDLY**|**DESCRIPTIONS**|
|---|---|---|---|---|---|---|---|---|
|1|1|1|1|1|0|0|0|The device’s output is disabled while the fault is present. Operation resumes<br>and the output is enabled when the fault condition no longer exists. It<br>attempts to restart continuously, without limitation, until it is commanded off<br>(by the CONTROL pin or OPERATION command or both), bias power is<br>removed, or another fault condition causes the unit to shut down|
|0|0|0|0|0|0|0|0|The device continues operation|
|0|0|0|1|0|1|1|0|The device continues operation|
|0|0|1|0|0|0|1|0|The device continues operation|
|0|0|1|1|0|1|1|0|The device continues operation|
|1|1|0|0|0|0|0|0|The device’s output is disabled while the fault is present. Operation resumes<br>and the output is enabled when the fault condition no longer exists|
|1|1|0|1|0|1|1|0|The device’s output is disabled while the fault is present. Operation resumes<br>and the output is enabled when the fault condition no longer exists|
|1|1|1|0|0|0|1|0|The device’s output is disabled while the fault is present. Operation resumes<br>and the output is enabled when the fault condition no longer exists|
|1|1|1|1|0|1|1|0|The device’s output is disabled while the fault is present. Operation resumes<br>and the output is enabled when the fault condition no longer exists|



## **VOUT_OV_WARN_LIMIT (42h)** 

The VOUT_OV_WARN_LIMIT command sets the value of the output voltage measured at the sense of output pins that causes an output voltage high warning. This is a read and write register. 

The VOUT_OV_WARN_LIMIT uses ULINEAR16 format, which is a 16-bit unsigned integer according to the setting of the VOUT_MODE command. 

## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|15:0|Ulinear 16|0151h|The VOUT_OV_WARN_LIMIT is specified as 0.66 V|



The VOUT_OV_WARN_LIMIT range is 0.3 V to 14 V, resolution is 1.953 mV, and its NVM register default store value is 0151h equivalent to 0.66 V. 

## **VOUT_UV_WARN_LIMIT (43h)** 

The VOUT_UV_WARN_LIMIT command sets the value of the output voltage measured at the sense of output pins that causes an output voltage low warning. This is a read and write register. 

The VOUT_UV_WARN_LIMIT uses ULINEAR16 format, which is a 16-bit unsigned integer according to the setting of the VOUT_MODE command. 

## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|15:0|Ulinear 16|0114h|The VOUT_UV_WARN_LIMIT is specified as 0.54 V|



The VOUT_UV_WARN_LIMIT range is 0 V to 14 V, resolution is 1.953 mV, and its NVM register default store value is 0114h equivalent to 0.54 V. 

## **VOUT_UV_FAULT_LIMIT (44h)** 

The VOUT_UV_FAULT_LIMIT command sets the value of the output voltage measured at the sense of output pins that causes an output undervoltage fault. This is a read and write register. 

The VOUT_UV_FAULT_LIMIT uses ULINEAR16 format, which is a 16-bit unsigned integer according to the setting of the VOUT_MODE command. 

## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|15:0|Ulinear 16|00F5h|The VOUT_UV_FAULT_LIMIT is specified as 0.48 V|



The VOUT_UV_FAULT_LIMIT range is 0 V to 14 V, resolution is 1.953 mV, and its NVM register default store value is 00F5h equivalent to 0.48 V. 

Document Number: 63042 

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## **VOUT_UV_FAULT_RESPONSE (45h)** 

The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an output undervoltage fault. This is a read and write register and the NVM register default store value is B9h. 

|**COMMAND**|**VOUT_UV_FAULT_RESPONSE**|**VOUT_UV_FAULT_RESPONSE**|**VOUT_UV_FAULT_RESPONSE**|**VOUT_UV_FAULT_RESPONSE**|**VOUT_UV_FAULT_RESPONSE**|**VOUT_UV_FAULT_RESPONSE**|**VOUT_UV_FAULT_RESPONSE**|**VOUT_UV_FAULT_RESPONSE**|
|---|---|---|---|---|---|---|---|---|
|Bit position|7|6|5|4|3|2|1|0|
|Function|UVRSP||UVRTY|||UVDLY|||
|Default (B9h)|1|0|1|1|1|0|0|1|



## **Supported Commands** 

|**UVRSP**|**UVRSP**|**UVRTY**|**UVRTY**|**UVRTY**|**UVDLY**|**UVDLY**|**UVDLY**|**DESCRIPTIONS**|
|---|---|---|---|---|---|---|---|---|
|1|0|1|1|1|0|0|1|The device shuts down (disables the output) and attempts to restart continuously,<br>without limitation, until it is commanded off (by the EN pin or OPERATION<br>command or both), bias power is removed, or another fault condition causes the<br>unit to shut down. 20 ms delay|
|0|0|0|0|0|0|0|0|The device continues operation|
|0|0|0|1|0|1|1|0|The device continues operation|
|0|0|1|0|0|0|1|0|The device continues operation|
|0|0|1|1|0|1|1|0|The device continues operation|
|1|1|0|0|0|0|0|0|The device’s output is disabled while the fault is present. Operation resumes and<br>the output is enabled when the fault condition no longer exists. The device does<br>not attempt to restart. The output remains disabled until the fault is cleared|
|1|1|0|1|0|1|1|0|The device’s output is disabled while the fault is present. Operation resumes and<br>the output is enabled when the fault condition no longer exists. The device does<br>not attempt to restart. The output remains disabled until the fault is cleared|
|1|1|1|0|0|0|1|0|The device’s output is disabled while the fault is present. Operation resumes and<br>the output is enabled when the fault condition no longer exists. The device does<br>not attempt to restart. The output remains disabled until the fault is cleared|
|1|1|1|1|0|1|1|0|The device’s output is disabled while the fault is present. Operation resumes and<br>the output is enabled when the fault condition no longer exists. The device does<br>not attempt to restart. The output remains disabled until the fault is cleared|



## **IOUT_OC_FAULT_LIMIT (46h)** 

The IOUT_OC_FAULT_LIMIT command sets the value of the output current, in Amperes, that causes the overcurrent detector to indicate an overcurrent fault condition. This is a read and write register. The IOUT_OC_FAULT_LIMIT uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the IOUT_OC_FAULT_LIMIT command is constant as 5’b11111, that is, -1 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. 

## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|15:0|Linear 11|F870h|The IOUT_OC_FAULT_LIMIT is 56 A for SiC450|
|||F846h|The IOUT_OC_FAULT_LIMIT is 35 A for SiC451|
|||F82Ah|The IOUT_OC_FAULT_LIMIT is 21 A for SiC453|
|||F822h|The IOUT_OC_FAULT_LIMIT is 17 A for SiC454|



The IOUT_OC_FAULT_LIMIT range is 0 A to 127 A, resolution is 0.5 A, and its NVM register default store value is F846h for SiC451 equivalent to 35 A. Any commands out of the valid range or with incorrect resolution will be ignored and reported. 

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## **IOUT_OC_FAULT_RESPONSE (47h)** 

The IOUT_OC_FAULT_RESPONSE is used to set device over current protection response (OCP) when valley inductor current is higher than IOUT_OC_FAULT_LIMIT. This is a read and write register and the NVM register default store value is A1h. 

|**COMMAND**|**IOUT_OC_FAULT_RESPONSE**|**IOUT_OC_FAULT_RESPONSE**|**IOUT_OC_FAULT_RESPONSE**|**IOUT_OC_FAULT_RESPONSE**|**IOUT_OC_FAULT_RESPONSE**|**IOUT_OC_FAULT_RESPONSE**|**IOUT_OC_FAULT_RESPONSE**|**IOUT_OC_FAULT_RESPONSE**|
|---|---|---|---|---|---|---|---|---|
|Bitposition|7|6|5|4|3|2|1|0|
|Function|OCRSP||OCCYCL|||OCDLY|||
|Default(0xA1h)|1|0|1|0|0|0|0|1|



This command deviates from standard PMBus 1.3 specifications. It provides users 3-bit [5 : 3] setting to generate  OC fault based on total number of consecutive pulse-by-pulse OC counts. It also provides users 3-bit [2 : 0] delay time option between shutdown and next restart attempt. In case of bits [5 : 3] = 111b, the device does not report OC fault and continues to operate indefinitely while maintaining the output current at the value set by IOUT_OC_FAULT_LIMIT without regard to the output voltage. 

## **Supported Commands** 

|**OCRSP**|**OCRSP**|**OCRTY**|**OCRTY**|**OCRTY**|**OCDLY**|**OCDLY**|**OCDLY**|**DESCRIPTIONS**|
|---|---|---|---|---|---|---|---|---|
|1|0|1|0|0|0|0|1|The device continues operation for 128 consecutive OC cycles and then shut down.<br>Waitingfor 20 ms,it hiccups until the fault condition no longer exists|
|0|0|0|0|0|0|0|0|The device continues operation|
|0|0|0|1|0|1|1|0|The device continues operation|
|0|0|1|0|0|0|1|0|The device continues operation|
|0|0|1|1|0|1|1|0|The device continues operation|
|1|1|0|0|0|0|0|0|The device continues operation for 8 consecutive OC cycles and then shut down<br>without delay|
|1|1|0|1|0|1|1|0|The device continues operation for 32 consecutive OC cycles and then shut down<br>without delay|
|1|1|1|0|0|0|1|0|The device continues operation for 128 consecutive OC cycles and then shut down<br>without delay.|
|1|1|1|1|0|1|1|0|The device continues operation for 512 consecutive OC cycles and then shut down<br>without delay|
|1|1|1|1|1|0|0|0|The device continues operation and never shut down when OCP happens|



## **IOUT_OC_WARN_LIMIT (4Ah)** 

The IOUT_OC_WARN_LIMIT command sets the value of the output current, in ampere, that causes an output overcurrent warning. This is a read and write register. The  IOUT_OC_WARN_LIMIT uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the IOUT_OC_WARN_LIMIT command is constant as 5’b11111, that is, -1 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. 

## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|1 5: 0|Linear 11|F868h|The IOUT_OC_WARN_LIMIT is 52 A SiC450|
|||F841h|The IOUT_OC_WARN_LIMIT is 32.5 A for SiC451|
|||F827h|The IOUT_OC_WARN_LIMIT is 19.5 A for SiC453|
|||F81Fh|The IOUT_OC_WARN_LIMIT is 15.5 A for SiC454|



The IOUT_OC_WARN_LIMIT range is 0 A to 127 A, resolution is 0.5 A, and its NVM register default store value is F841h for SiC451 equivalent to 32.5 A. Any commands out of the valid range or with incorrect resolution will be ignored and reported. 

## **OT_FAULT_LIMIT (4Fh)** 

The OT FAULT LIMIT command sets the temperature of the unit, in degree celsius, at which it should indicate an overtemperature fault. This is a read and write register. The OT_FAULT_LIMIT uses LINEAR11 format, which has two data bytes with an 11- bit two’s complement mantissa and a 5- bit two’s complement exponent (scaling factor). The 5- bit two’s complement exponent of the OT_FAULT_LIMIT command is constant as 5’b00000, that is, 0 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. 

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## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|15:0|Linear 11|007Dh|The OT_FAULT_LIMIT is specified as 125 °C|



The OT_FAULT_LIMIT range is 0 °C to 150 °C, resolution is 1 °C, and its NVM register default store value is 007Dh equivalent to 125 °C. Any commands out of the valid range or with incorrect resolution will be ignored and reported. 

## **OT_FAULT_RESPONSE (50h)** 

The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an overtemperature fault. This is a read and write register and the NVM register default store value is F9h. 

|**COMMAND**|**OT FAULT RESPONSE**|**OT FAULT RESPONSE**|**OT FAULT RESPONSE**|**OT FAULT RESPONSE**|**OT FAULT RESPONSE**|**OT FAULT RESPONSE**|**OT FAULT RESPONSE**|**OT FAULT RESPONSE**|
|---|---|---|---|---|---|---|---|---|
|Bit position|7|6|5|4|3|2|1|0|
|Function|OTRSP||OTRTY|||OTDLY|||
|Default (F9h)|1|1|1|1|1|0|0|1|



## **Supported Commands** 

|**OTRSP**|**OTRSP**|**OTRTY**|**OTRTY**|**OTRTY**|**OTDLY**|**OTDLY**|**OTDLY**|**DESCRIPTIONS**|
|---|---|---|---|---|---|---|---|---|
|1|1|1|1|1|0|0|1|The device’s output is disabled while the fault is present. Operation resumes and<br>the output is enabled when the fault condition no longer exists. It attempts to<br>restart continuously, without limitation, until it is commanded off (by the EN pin<br>or OPERATION command or both), bias power is removed, or another fault<br>condition causes the unit to shut down|
|0|0|0|0|0|0|0|0|The device continues operation|
|0|0|0|1|0|1|1|0|The device continues operation|
|0|0|1|0|0|0|1|0|The device continues operation|
|0|0|1|1|0|1|1|0|The device continues operation|
|1|1|0|0|0|0|0|0|The device’s output is disabled while the fault is present. Operation resumes and<br>the output is enabled when the fault condition no longer exists. It does not<br>attempt to restart. The output remains disabled until the fault is cleared|
|1|1|0|1|0|1|1|0|The device’s output is disabled while the fault is present. Operation resumes and<br>the output is enabled when the fault condition no longer exists|
|1|1|1|0|0|0|1|0|The device’s output is disabled while the fault is present. Operation resumes and<br>the output is enabled when the fault condition no longer exists|
|1|1|1|1|0|1|1|0|The device’s output is disabled while the fault is present. Operation resumes and<br>the output is enabled when the fault condition no longer exists|



## **OT_WARN_LIMIT (51h)** 

The OT_WARN_LIMIT command sets the temperature of the unit, in degree celsius, at which it should indicate an overtemperature warning alarm. This is a read and write register. The OT_WARN_LIMIT uses LINEAR11 format, which has two data bytes with an 11- bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the OT WARN LIMIT command is constant as 5’b00000, that is, 0 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. 

## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|15 : 0|Linear 11|0069h|The OT_WARN_LIMIT is specified as 105 °C|



The OT_WARN_LIMIT range is 0 °C to 150 °C, resolution is 1 °C, and its NVM register default store value is 0069h equivalent to 105 °C. Any commands out of the valid range or with incorrect resolution will be ignored and reported. 

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## **VIN_OV_FAULT_LIMIT (55h)** 

The VIN_OV_FAULT_LIMIT command sets the value of the input voltage, in volt, that causes an input overvoltage fault. This is a read and write register. The VIN_OV_FAULT_LIMIT uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5 bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the VIN_OV_FAULT_LIMIT command is constant as 5’b11111, that is, -1 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. 

## **Bit Description** 

|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|---|---|---|---|
|15 : 0|Linear 11|F81Eh|The VIN_OV_FAULT_LIMIT is specified as 15 V|



The VIN_OV_FAULT_LIMIT range is 1 V to 80 V, resolution is 0.5 V, and its NVM register default store value is F81Eh equivalent to 15 V. Any commands out of the valid range or with incorrect resolution will be ignored and reported. 

## **VIN_OV_FAULT_RESPONSE (56h)** 

The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input overvoltage fault. This is a read and write register and the NVM register default store value is B8h. 

|**COMMAND**|**COMMAND**|**COMMAND**|**COMMAND**|**COMMAND**|**COMMAND**|**VIN_OV_FAULT_RESPONSE**|**VIN_OV_FAULT_RESPONSE**|**VIN_OV_FAULT_RESPONSE**|**VIN_OV_FAULT_RESPONSE**|**VIN_OV_FAULT_RESPONSE**|**VIN_OV_FAULT_RESPONSE**|**VIN_OV_FAULT_RESPONSE**|**VIN_OV_FAULT_RESPONSE**|**VIN_OV_FAULT_RESPONSE**|**VIN_OV_FAULT_RESPONSE**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Bit position||||||7||6||5|4|3|2|1|0|
|Function||||||VIOVRSP||||VIOVRTY|||VIOVDLY|||
|Default (B8h)||||||1||0||1|1|1|0|0|0|
|**Supported Commands**||||||||||||||||
|**OTRSP**||**OTRTY**|||**OTDLY**||||**DESCRIPTIONS**|||||||
|1|0|1|1|1|0||0|0|This command deviates from standard PMBus 1.3 specifications. The device’s<br>output is disabled while the fault is present. Operation resumes and the output<br>is enabled when the fault condition no longer exists. It does not attempt to<br>restart. The output remains disabled until the fault is cleared|||||||
|0|0|0|0|0|0||0|0|The device continues operation|||||||
|0|0|0|1|0|1||1|0|The device continues operation|||||||
|0|0|1|0|0|0||1|0|The device continues operation|||||||
|0|0|1|1|0|1||1|0|The device continues operation|||||||
|1|1|0|0|0|0||0|0|The device’s output is disabled while the fault is present. Operation resumes and<br>the output is enabled when the fault condition no longer exists. It does not<br>attempt to restart. The output remains disabled until the fault is cleared|||||||
|1|1|0|1|0|1||1|0|The device’s output is disabled while the fault is present. Operation resumes and<br>the output is enabled when the fault condition no longer exists|||||||
|1|1|1|0|0|0||1|0|The device’s output is disabled while the fault is present. Operation resumes and<br>the output is enabled when the fault condition no longer exists|||||||
|1|1|1|1|0|1||1|0|The device’s output is disabled while the fault is present. Operation resumes and<br>the output is enabled when the fault condition no longer exists|||||||



## **VIN_UV_WARN_LIMIT (58h)** 

The VIN_UV_WARN_LIMIT command sets the value of the input voltage, in volt, that causes an input voltage low warning. This is a read and write register. The VIN_UV_WARN_LIMIT uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the VIN_UV_WARN_LIMIT command is constant as 5’b11111, that is, -1 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. 

## **Bit Description** 

|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|---|---|---|---|
|15 : 0|Linear 11|F812h|The VIN_UV_WARN_LIMIT is specified as 9 V|



The VIN_UV_WARN_LIMIT range is 1 V to 80 V, resolution is 0.5 V, and its NVM register default store value is F812h equivalent to 9 V. Any commands out of the valid range or with incorrect resolution will be ignored and reported. 

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## **IIN_OC_WARN_LIMIT (5Dh)** 

The IIN_OC_WARN_LIMIT command sets the value of the input current, in ampere, that causes an input current overcurrent Warning. This is a read and write register. The IIN_OC_WARN_LIMIT uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the IIN_OC_WARN_LIMIT command is constant as 5’b11111, that is, -1 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. 

## **Bit Description** 

|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|---|---|---|---|
|15 : 0|Linear 11|F80Ah|The IIN_OC_WARN_LIMIT is specified as 5 A|



The IIN_OC_WARN_LIMIT range is 0 A to 127 A, resolution is 0.5 A, and its NVM register default store value is F80Ah equivalent to 5 A. Any commands out of the valid range or with incorrect resolution will be ignored and reported. 

## **POWER_GOOD_ON (5Eh)** 

The POWER_GOOD_ON command sets the value of the output voltage at which an optional power good signal should be asserted, indicating that the output voltage is valid. This is a read and write register. The POWER_GOOD_ON uses ULINEAR16 format, which is a 16-bit unsigned integer according to the setting of the VOUT_MODE command. 

## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|15 : 0|Ulinear 16|0114h|The POWER_GOOD_ON is specified as 0.54 V|



The POWER_GOOD_ON range is 0.24 V to 14 V, resolution is 1.953 mV, and its NVM register default store value is 0114h equivalent to 0.54 V. 

## **POWER_GOOD_OFF (5Fh)** 

The POWER_GOOD_OFF command sets the value of the output voltage at which an optional power good signal should be negated, indicating that the output voltage is not valid. This is a read and write register. The POWER_GOOD_OFF uses ULINEAR16 format, which is a 16-bit unsigned integer according to the setting of the VOUT_MODE command. 

## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|15 : 0|Ulinear 16|0105h|The POWER_GOOD_OFF is specified as 0.51 V|



The POWER_GOOD_OFF range is 0.24 V to 14 V, resolution is 1.953 mV, and its NVM register default store value is 0105h equivalent to 0.51 V. 

## **TON_DELAY(60h)** 

The TON_DELAY command sets the time, in millisecond, from which a start condition is received (as programmed by the ON_OFF_CONFIG command) until the output voltage starts to rise. This is a read and write register. The TON_DELAY uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5 bit two’s complement exponent of the TON_DELAY command is constant as 5’b0000, that is, 0 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. 

## **Bit Description** 

|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|---|---|---|---|
|15 : 0|Linear 11|0000h|The TON_DELAY is specified as 0 ms|



The TON_DELAY range is 0 ms to 127 ms, resolution is 1 ms, and its NVM register default store value is 0000h equivalent to 0 ms. Any commands out of the valid range or with incorrect resolution will be ignored and reported. 

## **TON_RISE (61h)** 

The TON_RISE command sets the time, in millisecond, from when the output starts to rise until the voltage has entered the regulation band. This is a read and write register. The TON_RISE uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the TON_RISE command is constant as 5’b0000, that is, 0 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. 

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## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|15 : 0|Linear 11|0005h|The TON_RISE is specified as 5 ms|



The TON_RISE range is 0 ms to 127 ms, resolution is 1 ms, and its NVM register default store value is 0005h equivalent to 5 ms. Any commands out of the valid range or with incorrect resolution will be ignored and reported. 

## **TON_MAX_FAULT_LIMIT (62h)** 

The TON_MAX_FAULT_LIMIT command sets an upper limit, in millisecond, on how long the unit can attempt to power up the output without reaching the output undervoltage fault limit. This is a read and write register. The TON_MAX_FAULT_LIMIT uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the TON_MAX_FAULT_LIMIT command is constant as 5’b0000, that is, 0 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. 

## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|15 : 0|Linear 11|0014h|The TON_MAX_FAULT_LIMIT is specified as 20 ms|



The TON_MAX_FAULT_LIMIT range is 0 ms to 127 ms, resolution is 1 ms, and its NVM register default store value is 0014h equivalent to 20 ms. Any commands out of the valid range or with incorrect resolution will be ignored and reported. 

## **TON_MAX_FAULT_RESPONSE (63h)** 

The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to an input overcurrent fault. This is a read and write register and the NVM register default store value is B9h. 

|**COMMAND**|**TON_MAX_FAULT_RESPONSE**|**TON_MAX_FAULT_RESPONSE**|**TON_MAX_FAULT_RESPONSE**|**TON_MAX_FAULT_RESPONSE**|**TON_MAX_FAULT_RESPONSE**|**TON_MAX_FAULT_RESPONSE**|**TON_MAX_FAULT_RESPONSE**|**TON_MAX_FAULT_RESPONSE**|
|---|---|---|---|---|---|---|---|---|
|Bit position|7|6|5|4|3|2|1|0|
|Function|ONMXRSP||ONMXRTY|||ONMXDLY|||
|Default (0xB9h)|1|0|1|1|1|0|0|1|



## **Supported Commands** 

|**ONMXRSP**|**ONMXRSP**|**ONMXRTY**|**ONMXRTY**|**ONMXRTY**|**ONMXDLY**|**ONMXDLY**|**ONMXDLY**|**DESCRIPTIONS**|
|---|---|---|---|---|---|---|---|---|
|1|0|1|1|1|0|0|1|The device shuts down (disables the output). It attempts to restart continuously,<br>without limitation, until it is commanded off (by the EN pin or OPERATION command<br>or both), bias power is removed, or another fault condition causes the unit to shut<br>down. 20 ms delay|
|1|0|0|0|0|0|0|0|The device shuts down (disables the output). It does not attempt to restart. The<br>output remains disabled until the fault is cleared|
|1|0|0|0|0|0|1|1|The device shuts down (disables the output). It does not attempt to restart. The<br>output remains disabled until the fault is cleared|
|1|0|0|0|0|1|1|0|The device shuts down (disables the output). It does not attempt to restart. The<br>output remains disabled until the fault is cleared|
|1|0|0|0|1|0|0|0|The device shuts down (disables the output). It attempts to restart 1 time. No delay|
|1|0|0|0|1|0|0|1|The device shuts down (disables the output). It attempts to restart 1 time. 20 ms delay|
|1|0|0|0|1|0|1|0|The device shuts down (disables the output). It attempts to restart 1 time. 30 ms delay|
|1|0|0|0|1|0|1|1|The device shuts down (disables the output). It attempts to restart 1 time. 40 ms delay|



## **TOFF_DELAY (64h)** 

The TOFF_DELAY command sets the time, in millisecond, from when a stop condition is received until the unit stops transferring energy to the output. This is a read and write register. The TOFF_DELAY uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the TOFF_DELAY command is constant as 5’b0000, that is, 0 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. 

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## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|15 : 0|Linear 11|0000h|The TOFF_DELAY is specified as 0 ms|



The TOFF_DELAY range is 0 ms to 127 ms, resolution is 1 ms, and its NVM register default store value is 0000h equivalent to 0 ms. Any commands out of the valid range or with incorrect resolution will be ignored and reported. 

## **TOFF_FALL (65h)** 

The TOFF_FALL command sets the time, in millisecond, from the end of the turn-off delay time until the voltage is commanded to zero. Note that this command can only be used with a device whose output can sink enough current to cause the output voltage to decrease at a controlled rate. This is a read and write register. The TOFF_FALL uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5-bit two’s complement exponent of the TOFF_FALL command is constant as 5’b0000, that is, 0 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. 

## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|15 : 0|Linear 11|0005h|The TOFF_FALL is specified as 5 ms|



The TOFF_FALL range is 0 ms to 127 ms, resolution is 1 ms, and its NVM register default store value is 0005h equivalent to 5 ms. Any commands out of the valid range or with incorrect resolution will be ignored and reported. 

## **TOFF_MAX_WARN_LIMIT (66h)** 

The TOFF_MAX_WARN_LIMIT command sets an upper limit, in millisecond, on how long the unit can attempt to power down the output without reaching 12.5 % of the output voltage programmed at the time the unit is turned off. This is a read and write register. The TOFF_MAX_WARN_LIMIT uses LINEAR11 format, which has two data bytes with an 11-bit two’s complement mantissa and a 5-bit two’s complement exponent (scaling factor). The 5- bit two’s complement exponent of the TOFF_MAX_WARN_LIMIT command is constant as 5’b0000, that is, 0 in decimal. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. 

## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|15 : 0|Linear 11|003Ch|The TOFF_MAX_WARN_LIMIT is specified as 60 ms|



The TOFF_MAX_WARN_LIMIT range is 0 ms to 127 ms, resolution is 1 ms, and its NVM register default store value is 003Ch equivalent to 60 ms. Any commands out of the valid range or with incorrect resolution will be ignored and reported. 

## **STATUS_BYTE (78h)** 

The STATUS_BYTE command returns one byte of information with a summary of the most critical faults. The STATUS_BYTE message content is described in the table below. This is a read register. 

**Table - STATUS_BYTE Message Contents** 

|**BIT**|**STATUS BIT NAME**|**MEANING**|
|---|---|---|
|7|BUSY|A fault was declared because the device was busy and unable to respond|
|6|OFF|This bit is asserted if the unit is not providing power to the output, regardless of the reason,<br>includingsimply not beingenabled|
|5|VOUT_OV_FAULT|An output overvoltage fault has occurred|
|4|IOUT_OC_FAULT|An output overcurrent fault has occurred|
|3|VIN_UV_FAULT|An input undervoltage fault has occurred|
|2|Temperature|A temperature fault or warninghas occurred|
|1|CML|A communications, memory or logic fault has occurred|
|0|None of the above|A fault or warningnot listed in bits (7 to 1) has occurred|



## **STATUS_WORD (79h)** 

The STATUS_WORD command returns two bytes of information with a summary of the unit’s fault condition. Based on the information in these bytes, the host can get more information by reading the appropriate status registers. The low byte of the status word is the same register as the STATUS_BYTE command. The STATUS_WORD message content is described in the following table. This is a read register. 

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|**BYTE**|**BIT**|**STATUS BIT NAME**|**MEANING**|
|---|---|---|---|
|Low|7|Busy|A fault was declared because the device was busy and unable to respond|
||6|OFF|This bit is asserted if the unit is not providing power to the output, regardless of the<br>reason, includingsimply not beingenabled|
||5|VOUT_OV_FAULT|An output overvoltage fault has occurred|
||4|IOUT_OC_FAULT|An output overcurrent fault has occurred|
||3|VIN_UV_FAULT|An input undervoltage fault has occurred|
||2|Temperature|A temperature fault or warninghas occurred|
||1|CML|A communications, memory or logic fault has occurred|
||0|None of the above|A fault or warning not listed in bits [7 : 1] has occurred|
|High|7|VOUT|An output voltage fault or warninghas occurred|
||6|IOUT/ POUT|An output current or output power fault or warninghas occurred|
||5|Input|An input voltage, input current, or input power fault or warning has occurred|
||4|MFR specific|A manufacturer specific fault or warninghas occurred|
||3|PGstatus #|The powergood signal, if present, is negated|
||2|Fans|Not available|
||1|Other|Not available|
||0|Unknown|Not available|



## **STATUS_VOUT (7Ah)** 

The STATUS_VOUT command returns one byte with contents described in the following table. This is a read register. 

|**BIT**|**MEANING**|
|---|---|
|7|VOUTOV fault (output overvoltage fault)|
|6|VOUTOV warning(output overvoltage warning)|
|5|VOUTUV warning(output undervoltage warning)|
|4|VOUTOV fault (output undervoltage fault)|
|3|VOUTmax. min. (an attempt has been made to set the output voltage toa value higher than allowed by the VOUTmax. or<br>lower than the limited allowed by the VOUTmin.)|
|2|tONmax. fault (output overvoltage fault)|
|1|tOFFmax. warning(output overvoltage fault)|
|0|Not available|



## **STATUS_IOUT (7Bh)** 

The STATUS_IOUT command returns one byte with contents described in the following table. This is a read register. 

|**BIT**|**MEANING**|
|---|---|
|7|IOUTOC fault (output overcurrent fault)|
|6|Not available|
|5|IOUTOC warning(output overcurrent warning)|
|4|Not available|
|3|Not available|
|2|Not available|
|1|Not available|
|0|Not available|



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## **STATUS_INPUT (7Ch)** 

The STATUS_INPUT command returns one byte with contents described in the following table. This is a read register. 

|**BIT**|**MEANING**|
|---|---|
|7|VINOV fault (input overvoltage fault)|
|6|Not available|
|5|VINUV warning(input undervoltage warning)|
|4|Not available|
|3|Unit off for insufficient input voltage|
|2|Not available|
|1|IINOC warning(input overcurrent warning)|
|0|Not available|



## **STATUS_TEMPERATURE (7Dh)** 

The STATUS_TEMPERATURE command returns one byte with contents described in the following table. This is a read register. 

|**BIT**|**MEANING**|
|---|---|
|7|OT fault (overtemperature fault)|
|6|OT warning (overtemperature warning)|
|5 to 0|Not available|



## **STATUS_CML (7Eh)** 

The STATUS_CML command returns one byte with contents described in the following table. This is a read register. 

|**BIT**|**MEANING**|
|---|---|
|7|Invalid or unsupported command received|
|6|Invalid or unsupported data received|
|5|Packet error check failed|
|4|Memory fault detected|
|3|Not available|
|2|Reserved|
|1|A communication fault other than the ones listed in this table has occurred|
|0|Not available|



## **STATUS_MFR Specific (80h)** 

The STATUS_MFR specific command returns one byte with contents described in the following table. This is a read register. 

|**BIT**|**MEANING**|
|---|---|
|7 to 4|Not available|
|3|IL master fault|
|2|YF verify fault|
|1|YF erase fault|
|0|YF PGM fault|



## **READ_VIN (88h)** 

The READ_VIN command returns the input voltage in volt. The two data bytes are encoded in LINEAR11 format. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. This is a read register. 

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## **READ_IIN (89h)** 

The READ_IIN command returns the input current in ampere. The two data bytes in this register are encoded in unsigned LINEAR11 format, ULINEAR11. The ULINEAR11 has the format shown in “Table - ULINEAR11 Format” Table - ULINEAR11 Format 

|Table - ULINEAR11 Format|||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**COMMAND EXAMPLE**|**READ_IIN**||||||||||||||||
|Bitposition|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|Function|Two’s compliment exponent,N||||||Integer,M||||||||||



The relation between N, M and real-world value, X is: 

X = M x 2[N] 

For example, an input current of 0.501 A will return a value of AC03h in ULINEAR11 format when READ_IIN is implemented. 

|Bitposition|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Data|1|0|1|0|1|1|0|0|0|0|0|0|0|0|1|1|
|Function|Two’s compliment exponent,N||||||Integer,M||||||||||



In this case, M = 1027, N = -11 and X = 0.50146 

## **READ_VOUT (8Bh)** 

The read VOUT command returns the actual, measured output voltage in volt. The two data bytes are encoded in ULINEAR16 format, which is a 16 bit unsigned integer according to the setting of the VOUT_MODE command. This is a read register. 

## **READ_IOUT (8Ch)** 

The READ_IOUT command returns the output current in ampere. The two data bytes are encoded in ULINEAR11 format. The ULINEAR11 format of the two data bytes is illustrated in Table - “ULINEAR11 Format”. This is a read register. 

## **READ_TEMPERATURE (8Dh)** 

The READ_TEMPERATURE command returns the measured temperature of the PMBus unit in degree celsius. The two data bytes are encoded in LINEAR11 format. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. This is a read register. 

## **READ_DUTY_CYCLE (94h)** 

The READ_DUTY_CYCLE command returns the duty of the PMBus unit’s power conversion in percent. The two data bytes are encoded in LINEAR11 format. The LINEAR11 format of the two data bytes is illustrated in Table - “LINEAR11 Numeric Format Data Bytes”. This is a read register. 

## **READ_POUT (96h)** 

The READ_POUT command returns the output power in watt. The two data bytes are encoded in ULINEAR11 format. The ULINEAR11 format of the two data bytes is illustrated in Table - “ULINEAR11 Format”. This is a read register. 

## **READ_PIN (97h)** 

The READ_PIN command returns the input power in watt. The two data bytes are encoded in ULINEAR11 format. The ULINEAR11 format of the two data bytes is illustrated in Table - “ULINEAR11 Format”. This is a read register. 

## **PMBus_REVISION (98h)** 

The PMBUS_REVISION command stores or reads the revision of the PMBus to which the device is compliant. The command has one data byte. Bits (7 to 4) indicate the revision of PMBus specification Part I to which the device is compliant. Bits (3 to 0) indicate the revision of PMBus specification part II to which the device is compliant. The permissible values are shown in the table below. This is a read register. 

## **Table - PMBUS_REVISION DATA Byte Contents** 

|**BITS (7 TO 4)**|**PART I REVISION**|**BIT (3 TO 0)**|**PART II REVISION**|
|---|---|---|---|
|0000b|1.0|0000b|1.0|
|0001b|1.1|0001b|1.1|
|0010b|1.2|0010b|1.2|
|0011b|1.3|0011b|1.3|



## **MFR_SERIAL (9Eh)** 

The MFR_SERIAL command is used to store user’s customized information. This is a read and write 16-bit block register. 

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**==> picture [78 x 17] intentionally omitted <==**

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VISHAY, —<br>**----- End of picture text -----**<br>


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## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|15 to 0|Block|0000h|A block register to store user’s customized information|



## **IC_DEVICE_ID (ADh)** 

The IC_DEVICE_ID command is used to either set or read the type or part number of an IC embedded within a PMBus that is used for the PMBus interface. Each manufacturer uses the format of their choice for the IC device identification. IC_DEVICE_ID is typically only set once, at the time of manufacture. 

## **Bit Description** 

|**BITS**|**SYMBOL**|**VALUE**||**ACTION**|
|---|---|---|---|---|
|15 to 0|Block|0000h|Thepart number of the unit||



## **EEPROM_PASSWORD (DBh)** 

The EEPROM_PASSWORD command will unlock write access to the internal NVM. This command must be sent before the STORE_USER_ALL command. Access to the NVM can be disabled by sending any other data and will be automatically disabled on each power-cycle. 

## **Bit Description** 

|**Bit Description**||||
|---|---|---|---|
|**BITS**|**SYMBOL**|**VALUE**|**ACTION**|
|15 to 0|Block|1234h|Defaultpassword for unlockingaccess to the NVM before the STORE_USER_ALL command|



## **MFR_BASE_ADDRESS (D7h) and MFR_BASE_ADDRESS_2 (E2h)** 

The data in either the MFR_BASE_ADDRESS (D7h) or MFR_BASE_ADDRESS_2 (E2h) register is used along with data from ADDR resistor and VSET setting to generate the device’s PMBUS address, which consists of 7 bits. Its most significant 3 bits are contributed by bits 6 to 4 of either MFR_BASE_ADDRESS register or MFR_BASE_ADDRESS_2 register, and its least significant 4 bits come from the data determined by the resistor connected to ADDR pin. When VSET pin is shorted or connected to AGND via a resistor, MFR_BASE_ADRESS register will be used to set bits 6 - 4. MFR_BASE_ADDRESS register has a default value of 10 h and MFR_BASE:ADDRESS_” register 50 h. Both register can be READ or WRITTEN. 

## Here shows 2 examples. 

1. Assume VSET pin is shorted or connected to AGND via a resistor, and a 4.75 k  resistor is connected between ADDR pin and AGND, which corresponds to an address offset of 07 h, then MFR_BASE_ADDRESS register will be used to set the PBMBUS address, which is 17 h. 

2. Assume VSET pin is floating, and a 7.87 k  resistor is connected between ADDR pin and AGND, which corresponds to an address offset of 0 Bh, then MFR_BASE_ADRESS_2 register will be used to set the PMBUS address, which is 5 Bh. 

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**ELECTRICAL CHARACTERISTICS** (VIN = 12 V, VOUT = 3.3 V, fsw = 600 kHz, unless otherwise noted) 

**==> picture [176 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
 Fig. 11 - Startup with VIN, No Load (10 ms/div)<br>**----- End of picture text -----**<br>


**Fig. 12 - Startup with EN, No Load (1 ms/div)** 

**==> picture [178 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
 Fig. 13 - Startup with VIN, 12 A Load (5 ms/div)<br>**----- End of picture text -----**<br>


Document Number: 63042 

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**==> picture [78 x 17] intentionally omitted <==**

**----- Start of picture text -----**<br>
VISHAY, —<br>**----- End of picture text -----**<br>


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**Fig. 14 - Startup with EN, 12 A Load (5 ms/div)** 

**Fig. 15 - 1.5 V Pre-biased Startup with VIN, No Load (5 ms/div)** 

**==> picture [190 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
 Fig. 16 - Shutdown with VIN, No Load (500 ms/div)<br>**----- End of picture text -----**<br>


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**ELECTRICAL CHARACTERISTICS** (VIN = 12 V, VOUT = 3.3 V, fsw = 600 kHz, unless otherwise noted) 

**Fig. 17 - Shutdown with EN, No Load (20 ms/div)** 

**Fig. 18 - Shutdown with VIN, 12 A Load (100 ms/div)** 

**==> picture [190 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
 Fig. 19 - Shutdown with EN, 12 A Load (50 μs/div)<br>**----- End of picture text -----**<br>


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**Fig. 20 - Overcurrent Protection (10 ms/div)** 

**Fig. 21 - Overcurrent Protection (100 μs/div)** 

Document Number: 63042 

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**==> picture [79 x 17] intentionally omitted <==**

**----- Start of picture text -----**<br>
VISHAY, —<br>**----- End of picture text -----**<br>


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**ELECTRICAL CHARACTERISTICS** (VIN = 12 V, VOUT = 3.3 V, fsw = 600 kHz, unless otherwise noted) 

**Fig. 22 - Load Step between 0 A and 6 A in CCM (20 μs/div)** 

**Fig. 23 - Load Step between 6 A and 12 A in CCM (20 μs/div)** 

**==> picture [226 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
 Fig. 24 - Load Step between 0 A and 6 A in DCM (20 μs/div)<br>**----- End of picture text -----**<br>


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**Fig. 25 - Steady State, No Load in CCM (2 μs/div)** 

**Fig. 26 - Steady State, No Load in DCM (2 μs/div)** 

**Fig. 27 - Steady State, No Load in DCM (20 ms/div)** 

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**Fig. 28 - Steady State, 12 A Load (2 μs/div)** 

**==> picture [188 x 175] intentionally omitted <==**

**----- Start of picture text -----**<br>
98<br>>se<br>88<br>ES<br>VOUT = 1.8 V, Power save<br>(AZ<br>LY LY | VOUT = 1.8 V<br>78 V OUT = 1.2 V, Power save<br>Vif ] VOUT = 1.2 V<br>VOUT = 1.0 V, Power save<br>68 VOUT = 1.0 V<br>Pee Eee<br>VIN = 12 V, fSW = 600kHz<br>58<br>0 2 4 6 8 10 12<br>IOUT - Output Current (A)<br> Fig. 29 - SiC454 Efficiency Curve<br>eff - Efficiency (%)<br>**----- End of picture text -----**<br>


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## **PCB LAYOUT RECOMMENDATIONS** 

## **Step 1: VIN/GND Planes and Decoupling** 

**==> picture [149 x 155] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN plane<br>VIN<br>sah<br>PGND plane<br>VSWH<br>**----- End of picture text -----**<br>


## **Step 3: VSWH Plane** 

**==> picture [105 x 82] intentionally omitted <==**

**----- Start of picture text -----**<br>
oh PGND plane<br>VSWH<br>Snubber<br>**----- End of picture text -----**<br>


**Fig. 30** 

1. Layout VIN and PGND planes as shown above 

2. Ceramic capacitors should be placed right between VIN and PGND, and very close to the device for best decoupling effect 

3. Difference values / packages of ceramic capacitors should be used to cover entire decoupling spectrum e.g. 1210 and 0603 

4. Smaller capacitance value, closer to device VIN pin(s) - better high frequency noise absorbing 

## **Step 2: VIN Pin** 

**Fig. 32** 

1. Connect output inductor to SiC454 with large plane to lower the resistance 

2. If any snubber network is required, place the components on the bottom side as shown above 

**==> picture [165 x 12] intentionally omitted <==**

**----- Start of picture text -----**<br>
AGND plane VIN decouple cap<br>**----- End of picture text -----**<br>


**Fig. 31** 

1. VIN (pin 23) is the input pin for both internal LDO and tON block. tON time varies based on input voltage. It is necessary to put a decouple cap close to this pin 

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## **Step 4: VDD/PVCC Input Filter** 

**==> picture [16 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
GND<br>**----- End of picture text -----**<br>


## **Step 6: Signal Routing** 

**==> picture [188 x 67] intentionally omitted <==**

**----- Start of picture text -----**<br>
VOUT sense signals<br>PGND<br>AGND<br>plane<br>**----- End of picture text -----**<br>


**Fig. 35** 

**Fig. 33** 

1. CVDD and CPVCC caps should be placed close to the IC to filter noise and provide maximum instantaneous driver current for low side MOSFET during switching cycle 

**Step 5: BOOT Resistor and Capacitor Placement** 

1. Separate the small analog signal from high current path. As shown above, the high current paths with high dv/dt, di/dt are placed on the right side of the IC, while the small control signals are placed on the left side of the IC. All the components for small analog signal should be placed closer to IC with minimum trace length 

2. Pin 16 is considered as IC analog ground, which should have single connection to power ground. The AGND ground plane connected with pin 16 helps to keep AGND quite and improve noise immunity 

3. Vsen+ / Vsen- differential analog signal pair should layout using minimum clearance. Also, the differential pair should be far away from VSWH node and other signals throughout the length of the trace. Ground shield is highly recommended 

**Fig. 34** 

1. These components need to be placed very close to SiC454, right between PHASE (pin 4) and BOOT (pin 6) 

2. To reduce parasitic inductance, chip size 0402 can be used 

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## **Step 7: Adding Thermal Relief Vias and Duplicate Power Path Plane** 

**==> picture [84 x 217] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN plane<br>|<br>PGND plane<br>VSWH<br>**----- End of picture text -----**<br>


**Fig. 36** 

1. Thermal relief Vias can be added on the VIN and PGND pads to utilize inner layers for high current and thermal dissipation 

## **Step 8: Ground Layer** 

**==> picture [138 x 18] intentionally omitted <==**

**----- Start of picture text -----**<br>
PGND plane<br>A GND plane<br>**----- End of picture text -----**<br>


**Fig. 37** 

   1. It is recommended to make the whole inner 1 layer (next to top layer) ground plane 

   2. This ground plane provides shielding between noise source on top layer and signal trace within inner layer 

   3. The ground plane can be broken into two section as power ground and analogue ground 

2. To achieve better thermal performance, additional Vias can be put on VIN plane and PGND plane. It is also necessary to duplicate the VIN and ground plane at bottom layer to maximize the power dissipation capability from PCB 

3. VSWH pad is a noise source and not recommended to put Vias on this pad 

4. 8 mil drill for pads and 10 mils drill for plane can be the optional Via size. The Vias on pad may drain solder during assembly and cause assembly issue. Please consult with the assembly house for guideline 

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|**PRODUCT SUMMARY**|**PRODUCT SUMMARY**|
|---|---|
|Part number|SiC454|
|Description|4.5 V to 20 V input 12 A microBUCK DC/DC converter with PMBus|
|Input voltage min. (V)|4.5|
|Input voltage max. (V)|20|
|Output voltage min. (V)|0.3|
|Output voltage max. (V)|12|
|Continuous current (A)|12|
|Switch frequency min. (kHz)|300|
|Switch frequency max. (kHz)|1500|
|Pre-bias operation (yes / no)|Yes|
|Internal bias reg. (yes / no)|Yes|
|Compensation|Internal|
|Enable (yes / no)|Yes|
|PGOOD(yes / no)|Yes|
|Over current protection|Yes|
|Protection|OVP, OCP, UVP/SCP, OTP, UVLO|
|Light load mode|Yes|
|Peak efficiency (%)|98|
|Package type|PowerPAK MLP29-55|
|Package size (W, L, H) (mm)|5.0 x 5.0 x 0.75|
|Status code|1|
|Product type|microBUCK|
|Applications|Datacenter, cloud computing, industrial, telecom|



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## **Disclaimer** 

ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 

Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 

Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability. 

Statements regarding the suitability of products for certain types of applications are based on Vishay's knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer's responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer's technical experts. Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited to the warranty expressed therein. 

Hyperlinks included in this datasheet may direct users to third-party websites. These links are provided as a convenience and for informational purposes only. Inclusion of these hyperlinks does not constitute an endorsement or an approval by Vishay of any of the products, services or opinions of the corporation, organization or individual associated with the third-party website. Vishay disclaims any and all liability and bears no responsibility for the accuracy, legality or content of the third-party website or for that of subsequent links. 

Vishay products are not designed for use in life-saving or life-sustaining applications or any application in which the failure of the Vishay product could result in personal injury or death unless specifically qualified in writing by Vishay. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. 

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. 

Document Number: 91000 

_**© 2024 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED**_ 

Revision: 01-Jul-2024 

**1** 

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 



## Links

- [View this product on Novapart](https://novapart.co/products/SIC454ED-T1-GE3/dc-converter-45-to-20-v-input-12-a-300mv-output)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/vishay/sic454ed-t1-ge3/dc-dc-converter-12v-powerpak-mlp55/dp/4541154RL)
---

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