# Power MOSFET, N Channel, 8 V, 10 A, 0.02 ohm, MICRO FOOT, Surface Mount

![Product image](https://novapart.co/image/farnell:2646397RL/)

**URL**: https://novapart.co/products/SI8424CDB-T1-E1/power-mosfet-n-channel-8-v-10-a-002-ohm-micro-foot
**SKU**: SI8424CDB-T1-E1
**Manufacturer**: VISHAY
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.2000
**Stock**: 1000+
**Lead Time**: 344 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:10A; Drain Source Voltage Vds:8V; On Resistance Rds(on):0.015ohm; Rds(on) Test Voltage Vgs:4.5V; Threshold Voltage Vgs:800mV;

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 4Pins |
| Channel Type | N Channel |
| Product Range | TrenchFET |
| Qualification | - |
| Power Dissipation | 2.7W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 4.5V |
| Transistor Case Style | MICRO FOOT |
| Drain Source Voltage Vds | 8V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 10A |
| Drain Source On State Resistance | 0.02ohm |
| Gate Source Threshold Voltage Max | 800mV |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2646397RL/)

**Si8424CDB** 

Vishay Siliconix 

www.vishay.com 

## **N-Channel 8 V (D-S) MOSFET** 

|**PRODUCT SUMMARY**|**PRODUCT SUMMARY**|**PRODUCT SUMMARY**|**PRODUCT SUMMARY**|
|---|---|---|---|
|**VDS (V)**|**RDS(on) (****) MAX.**|**ID (A)a, e**|**Qg (TYP.)**|
|8|**DS(on)**<br>0.020 at VGS= 4.5 V|10|**g**<br>25 nC|
||0.021 at VGS= 2.5 V|9.7||
||0.023 at VGS= 1.8 V|9.3||
||0.028 at VGS= 1.5 V|8.4||
||0.045 at VGS= 1.2 V|5||



## **FEATURES** 

- TrenchFET[®] power MOSFET 

- Low-on resistance 

- Ultra-small 1.6 mm x 1.6 mm maximum outline 

- Ultra-thin 0.6 mm maximum height 

- Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 

## **APPLICATIONS** 

## **MICRO FOOT[®] 1.6 x 1.6** 

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D<br>2<br>D<br>3<br>1<br>4 G<br>1 S<br>Backside View Bump Side View<br>8424C<br>xxx<br>1.6 mm<br>1.6 mm<br>**----- End of picture text -----**<br>


## **Marking Code** : 8424C 

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D<br>G<br>S<br>**----- End of picture text -----**<br>


- Mobile computing, smart phones, tablet PCs 

- Load switch 

- Low voltage drop switch 

N-Channel MOSFET 

**Ordering Information** : Si8424CDB-T1-E1 (Lead (Pb)-free and halogen-free) 

|**ABSOLUTE MAXIMUM RATINGS**(TA= 25 °C,unless otherwise noted)<br>~~CC~~|**ABSOLUTE MAXIMUM RATINGS**(TA= 25 °C,unless otherwise noted)<br>~~CC~~|**ABSOLUTE MAXIMUM RATINGS**(TA= 25 °C,unless otherwise noted)<br>~~CC~~|**ABSOLUTE MAXIMUM RATINGS**(TA= 25 °C,unless otherwise noted)<br>~~CC~~|**ABSOLUTE MAXIMUM RATINGS**(TA= 25 °C,unless otherwise noted)<br>~~CC~~|
|---|---|---|---|---|
|**PARAMETER**<br>~~CC~~<br>~~eG~~||**SYMBOL**<br>~~CC~~<br>~~eG~~|**LIMIT**<br>~~CC~~<br>~~eG~~|**UNIT**<br>~~CC~~<br>~~eG~~|
|Drain-Source Voltage<br>~~OC~~<br>~~ee~~||VDS<br>~~OC~~<br>~~ee~~|8<br>~~OC~~<br>~~ee~~|V<br>~~ee~~|
|Gate-Source Voltage<br>~~ee~~||VGS<br>~~ee~~|± 5<br>~~ee~~||
|Continuous Drain Current (TJ= 150 °C)<br>~~|~~<br>~~|~~<br>~~Po~~<br>~~Pp~~|TA= 25 °C<br>~~|~~<br>~~Pp~~|ID|10a<br>~~Po~~<br>~~=f~~|A<br>~~=f~~|
||TA= 70 °C<br>~~|~~<br>~~|~~<br>~~Pp~~||8a<br>~~Po~~<br>~~Po~~<br>~~=f~~||
||TA= 25 °C<br>~~|~~<br>~~|~~<br>~~Po~~<br>~~Pp~~||6.3b<br>~~Po~~<br>~~Po~~<br>~~Po~~<br>~~=f~~||
||TA= 70 °C<br>~~|~~<br>~~Po~~<br>~~Pp~~||5.1b<br>~~Po~~<br>~~Po~~<br>~~=f~~||
|Pulsed Drain Current (t = 300 μs)<br>~~Po~~<br>~~Pp~~||IDM|25<br>~~Po~~<br>~~=f~~||
|Continuous Source-Drain Diode Current<br>~~Pp~~|TA= 25 °C<br>~~Pp~~|IS|2.3a<br>~~=f~~||
||TA= 25 °C<br>~~Pp~~||0.92b<br>~~=f~~||
|Maximum Power Dissipation<br>~~po~~<br>~~Po~~<br>~~|~~|TA= 25 °C<br>~~po~~|PD|2.7a<br>~~Po~~|W|
||TA= 70 °C<br>~~po~~<br>~~Po~~||1.8a<br>~~Po~~<br>~~Po~~||
||TA= 25 °C<br>~~po~~<br>~~Po~~<br>~~|~~||1.1b<br>~~Po~~<br>~~Po~~<br>~~PO~~||
||TA= 70 °C<br>~~Po~~<br>~~|~~||0.73b<br>~~Po~~<br>~~PO~~||
|OperatingJunction and Storage Temperature Range<br>~~|~~<br>~~GO~~<br>~~rr~~||TJ, Tstg<br>~~GO~~<br>~~rr~~|-55 to +150<br>~~PO~~<br>~~GO~~<br>~~rr~~|°C<br>~~rr~~|
|Package Reflow Conditionsc<br>~~rr~~|VPR<br>~~rr~~<br>~~ee~~|~~rr~~<br>~~ee~~|260<br>~~rr~~||
||IR / convection<br>~~rr~~<br>~~ee~~|~~rr~~<br>~~ee~~|260<br>~~rr~~||



- b. Surface mounted on 1" x 1" FR4 board with minimum copper, t = 5 s. 

- c. Refer to IPC / JEDEC[®] (J-STD-020), no manual or hand soldering. 

- d. In this document, any reference to case represents the body of the MICRO FOOT device and foot is the bump. 

- e. Based on TA = 25 °C. 

S15-1692-Rev. C, 20-Jul-15 

Document Number: 63894 

**1** 

For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**Si8424CDB** 

**==> picture [59 x 48] intentionally omitted <==**

www.vishay.com 

Vishay Siliconix 

|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**||
|---|---|---|---|---|---|
|**PARAMETER**||**SYMBOL**|**TYPICAL**|**MAXIMUM**|**UNIT**|
|Maximum Junction-to-Ambienta, b|t = 5 s|RthJA|35|45|°C/W|
|Maximum Junction-to-Ambientc, d|t = 5 s|RthJA|85|110||



## **Notes** 

a. Surface mounted on 1" x 1" FR4 board with full copper, t = 5 s. b. Maximum under steady state conditions is 85 °C/W. 

c. Surface mounted on 1" x 1" FR4 board with minimum copper, t = 5 s. d. Maximum under steady state conditions is 175 °C/W. 

|**SPECIFICATIONS**(TJ= 25 °C,unless otherwise noted)|**SPECIFICATIONS**(TJ= 25 °C,unless otherwise noted)|**SPECIFICATIONS**(TJ= 25 °C,unless otherwise noted)|||||
|---|---|---|---|---|---|---|
|**PARAMETER**|**SYMBOL**|**TEST CONDITIONS**|**MIN.**|**TYP.**|**MAX.**|**UNIT**|
|**Static**|||||||
|Drain-Source Breakdown Voltage|VDS|VGS= 0 V, ID= 250 μA|8|-|-|V|
|VDSTemperature Coefficient|VDS/TJ|ID= 250 μA|-|3|-|mV/°C|
|VGS(th)Temperature Coefficient|VGS(th)/TJ||-|-2.6|-||
|Gate-Source Threshold Voltage|VGS(th)|VDS= VGS, ID= 250 μA|0.35|-|0.8|V|
|Gate-Source Leakage|IGSS|VDS= 0 V, VGS= ± 5 V|-|-|± 100|nA|
|Zero Gate Voltage Drain Current|IDSS|VDS= 8 V, VGS= 0 V|-|-|1|μA|
|||VDS= 8 V, VGS= 0 V, TJ= 70 °C|-|-|10||
|On-State Drain Currenta|ID(on)|VDS5 V, VGS= 4.5 V|5|-|-|A|
|Drain-Source On-State Resistancea|RDS(on)|VGS= 4.5 V, ID= 2 A|-|0.015|0.020||
|||VGS= 2.5 V, ID= 1 A|-|0.016|0.021||
|||VGS= 1.8 V, ID= 1 A|-|0.017|0.023||
|||VGS= 1.5 V, ID= 1 A|-|0.018|0.028||
|||VGS= 1.2 V, ID= 0.5 A|-|0.022|0.045||
|Forward Transconductancea|gfs|VDS= 4 V, ID= 2 A|-|30|-|S|
|**Dynamicb**|||||||
|Input Capacitance|Ciss|VDS= 4 V, VGS= 0 V, f = 1 MHz|-|2340|-|pF|
|Output Capacitance|Coss||-|870|-||
|Reverse Transfer Capacitance|Crss||-|600|-||
|Total Gate Charge|Qg|VDS= 4 V, VGS= 4.5 V, ID= 2 A|-|25|40|nC|
|Gate-Source Charge|Qgs||-|3.3|-||
|Gate-Drain Charge|Qgd||-|3.6|-||
|Gate Resistance|Rg|VGS= 0.1 V, f = 1 MHz|-|3.5|-||
|Turn-On Delay Time|td(on)|VDD= 4 V, RL= 2<br>ID @2 A, VGEN= 4.5 V, Rg= 1|-|13|30|ns|
|Rise Time|tr||-|19|40||
|Turn-Off Delay Time|td(off)||-|73|150||
|Fall Time|tf||-|20|40||
|**Drain-Source Body Diode Characteristics**|||||||
|Continuous Source-Drain Diode|IS|TA= 25 °C|-|-|2.3c|A|
|Pulse Diode Forward Current|ISM||-|-|25||
|Body Diode Voltage|VSD|IS= 2 A, VGS= 0 V|-|0.7|1.2|V|
|Body Diode Reverse Recovery Time|trr|IF= 2 A, dI/dt = 100 A/μs, TJ= 25 °C|-|40|80|ns|
|Body Diode Reverse Recovery Charge|Qrr||-|20|40|nC|
|Reverse Recovery Fall Time|ta||-|15|-|ns|
|Reverse Recovery Rise Time|tb||-|25|-||



## **Notes** 

a. Pulse test; pulse width  300 μs, duty cycle  2 %. 

b. Guaranteed by design, not subject to production testing. 

c. Surface mounted on 1" x 1" FR4 board with full copper, t = 5 s 

_Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability._ 

S15-1692-Rev. C, 20-Jul-15 

Document Number: 63894 

**2** For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**Si8424CDB** 

Vishay Siliconix 

**==> picture [59 x 48] intentionally omitted <==**

www.vishay.com 

## **TYPICAL CHARACTERISTICS** (25 °C, unless otherwise noted) 

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25<br>VGS = 5 V thru 1.5 V<br>20<br>15<br>10<br>VGS = 1 V<br>5<br>0<br>0.0   0.5   1.0   1.5   2.0   2.5<br>VDS - Drain-to-Source Voltage (V)<br>Output Characteristics<br>0.05<br>0.04  VGS = 1.2 V<br>0.03<br>VGS = 1.5 V<br>0.02  VGS = 1.8 V<br>0.01<br>VGS = 2.5 V  VGS = 4.5 V<br>0<br>0  5  10  15  20  25<br>ID - Drain Current (A)<br>On-Resistance vs. Drain Current<br>5<br>4  ID = 2 A  VDS = 4 V<br>3  V DS  = 2 V<br>2  VDS = 6.4 V<br>1<br>0<br>0  5  10  15  20  25  30<br>Qg - Total Gate Charge (nC)<br> - Drain Current (A)<br>ID<br> - On-Resistance (Ω)<br>DS(on)<br>R<br> - Gate-to-Source Voltage (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


**Gate Charge** 

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**----- Start of picture text -----**<br>
10<br>8<br>6<br>4   TC = 25  ° C<br>2   TC = 125 °C<br>TC = - 55 °C<br>0<br>0.0   0.2   0.4   0.6   0.8   1.0   1.2<br>VGS - Gate-to-Source Voltage (V)<br> - Drain Current (A)<br>ID<br>**----- End of picture text -----**<br>


**Transfer Characteristics** 

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3500<br>3000<br>2500  C iss<br>2000<br>1500<br>Coss<br>1000<br>Crss<br>500<br>0<br>0  2  4  6  8<br>VDS - Drain-to-Source Voltage (V)<br>C - Capacitance (pF)<br>**----- End of picture text -----**<br>


**Capacitance** 

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**----- Start of picture text -----**<br>
1.4<br>1.3<br>VGS = 4.5 V, 2.5 V, 1.8 V, 1.5 V;<br>ID = 1.5 A<br>1.2<br>1.1<br>VGS  = 1.2 V; I D = 0.5 A<br>1.0<br>0.9<br>0.8<br>0.7<br>0.6<br>- 50   - 25   0  25  50  75  100  125  150<br>TJ - Junction Temperature (°C)<br>On-Resistance vs. Junction Temperature<br> - On-Resistance (Normalized)<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


S15-1692-Rev. C, 20-Jul-15 

Document Number: 63894 

**3** 

For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**Si8424CDB** 

Vishay Siliconix 

**==> picture [59 x 48] intentionally omitted <==**

www.vishay.com 

## **TYPICAL CHARACTERISTICS** (25 °C, unless otherwise noted) 

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**----- Start of picture text -----**<br>
100<br>TJ = 150 °C<br>10<br>TJ = 25 °C<br>1<br>0.1<br>0.0  0.2  0.4  0.6  0.8  1.0  1.2<br>VSD - Source-to-Drain Voltage (V)<br> - Source Current (A) IS<br>**----- End of picture text -----**<br>


## **Source-Drain Diode Forward Voltage** 

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**----- Start of picture text -----**<br>
0.7<br>0.6<br>0.5<br>0.4<br>ID = 250 μA<br>0.3<br>0.2<br>0.1<br>- 50  - 25  0  25  50  75  100  125  150<br>TJ - Temperature (°C)<br> (V)<br>GS(th)<br>V<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
Threshold Voltage<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
0.05<br>0.04   I D  = 2 A<br>0.03<br>0.02   TJ = 125 °C<br>0.01   TJ = 25 °C<br>0<br>0 1 2 3 4 5<br>VGS - Gate-to-Source Voltage (V)<br>On-Resistance vs. Gate-to-Source Voltage<br>80<br>60<br>40<br>20<br>0<br>0.001 0.01 0.1 1 10 100 600<br>Time (s)<br> - On-Resistance (Ω)<br>DS(on)<br>R<br>Power  (W)<br>**----- End of picture text -----**<br>


**Single Pulse Power, Junction-to-Ambient** 

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**----- Start of picture text -----**<br>
100<br>Limited by RDS(on)*<br>10<br>1 ms<br>10 ms<br>1<br>100 ms<br>1 s<br>10 s<br>DC<br>0.1<br>TA = 25 °C<br>BVDSS Limited<br>0.01<br>0.1 1 10 100<br>VDS - Drain-to-Source Voltage (V)<br>* VGS > minimum VGS at which RDS(on) is specified<br> - Drain Current (A)<br>ID<br>**----- End of picture text -----**<br>


**Safe Operating Area, Junction-to-Ambient** 

S15-1692-Rev. C, 20-Jul-15 

Document Number: 63894 

**4** 

For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**Si8424CDB** 

Vishay Siliconix 

**==> picture [59 x 48] intentionally omitted <==**

**==> picture [77 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
www.vishay.com<br>**----- End of picture text -----**<br>


## **TYPICAL CHARACTERISTICS** (25 °C, unless otherwise noted) 

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**----- Start of picture text -----**<br>
8  1.5<br>1.2<br>6<br>0.9<br>4<br>0.6<br>2<br>0.3<br>0  0.0<br>0  25  50  75  100  125  150  25 50 75 100 125 150<br>TA - Ambient Temperature (°C)  TA - Ambient Temperature (°C)<br>Current Derating  [a] Power Derating<br>Power (W)<br> - Drain Current (A)<br>ID<br>**----- End of picture text -----**<br>


## **Notes** 

- When mounted on 1" x 1" FR4 with full copper. 

- a. The power dissipation PD is based on TJ (max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. 

S15-1692-Rev. C, 20-Jul-15 

Document Number: 63894 

**5** For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**Si8424CDB** 

Vishay Siliconix 

**==> picture [59 x 48] intentionally omitted <==**

www.vishay.com 

## **TYPICAL CHARACTERISTICS** (25 °C, unless otherwise noted) 

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**----- Start of picture text -----**<br>
2<br>1<br>Duty Cycle = 0.5<br>0.2<br>Notes:<br>0.1<br>0.1 PDM<br>0.05<br>t 1<br>0.02 1. Duty Cycle, D =t2 tt12<br>2. Per Unit Base = RthJA = 85 °C/W<br>3. TJM - TA = PDMZthJA [(t)]<br>Single Pulse 4. Surface Mounted<br>0.01<br>10 [-4] 10 [-3] 10 [-2] 10 [-1] 1 10 100 600<br>Square Wave Pulse Duration (s)<br>Normalized Thermal Transient Impedance, Junction-to-Ambient (1" x 1" FR4 Board with Full Copper)<br>1<br>Duty Cycle = 0.5<br>0.2<br>Notes:<br>0.1<br>0.1 PDM<br>0.05<br>t1<br>0.02 1. Duty Cycle, D =t2 t t1 2<br>2. Per Unit Base = RthJA = 175 °C/W<br>3. T JM  -   T A  = P DM Z thJA [(t)]<br>Single Pulse 4. Surface Mounted<br>0.01<br>10 [-3] 10 [-2] 10 [-1] 1 10 100 1000<br>Square Wave Pulse Duration (s)<br>Thermal Impedance<br>Normalized Effective Transient<br>Thermal Impedance<br>Normalized Effective Transient<br>**----- End of picture text -----**<br>


**Normalized Thermal Transient Impedance, Junction-to-Ambient (1" x 1" FR4 Board with Minimum Copper)** 

_Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?63894._ 

S15-1692-Rev. C, 20-Jul-15 

Document Number: 63894 

**6** 

For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**Package Information** Vishay Siliconix 

www.vishay.com 

**==> picture [59 x 48] intentionally omitted <==**

## **MICRO FOOT[®] : 4-Bumps (1.6 mm x 1.6 mm, 0.8 mm Pitch, 0.290 mm Bump Height)** 

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**----- Start of picture text -----**<br>
Mark on backside of die 4x Ø b1<br>4x 0.30 to .31<br>(Note 3)<br>Solder mask-0.4<br>D D<br>XXXX<br>XXX<br>e<br>S G<br>Recommended land pattern<br>S e S<br>D<br>b<br>b1<br>Note 5<br>K<br>S<br>E e e<br>S<br>A2<br>A<br>A1<br>**----- End of picture text -----**<br>


## **Notes** 

1. Bumps are 95.5/3.8/0.7 Sn/Ag/Cu. 

2. Backside surface is coated with a Ti/Ni/Ag layer. 

3. Non-solder mask defined copper landing pad. 

4. Laser marks on the silicon die back. 

5. “b1” is the diameter of the solderable substrate surface, defined by an opening in the solder resist layer solder mask defined. 

6. • is the location of pin 1 

|**DIM.**|**MILLIMETERS**|**MILLIMETERS**|**MILLIMETERS**|**INCHES**|**INCHES**|**INCHES**|
|---|---|---|---|---|---|---|
||**MIN.**|**NOM.**|**MAX.**|**MIN.**|**NOM.**|**MAX.**|
|A|0.550|0.575|0.600|0.0217|0.0226|0.0236|
|A1|0.260|0.275|0.290|0.0102|0.0108|0.0114|
|A2|0.290|0.300|0.310|0.0114|0.0118|0.0122|
|b|0.370|0.390|0.410|0.0146|0.0153|0.0161|
|b1|0.300|||0.0118|||
|e|0.800|||0.0314|||
|s|0.360|0.380|0.400|0.0141|0.0150|0.0157|
|D|1.520|1.560|1.600|0.0598|0.0614|0.0630|
|E|1.520|1.560|1.600|0.0598|0.0614|0.0630|
|K|0.155|0.185|0.215|0.0061|0.0073|0.0085|



## **Note** 

- Use millimeters as the primary measurement. 

ECN: T15-0175-Rev. A, 27-Apr-15 DWG: 6038 

Revision: 27-Apr-15 

Document Number: 69378 

**1** 

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**AN824 Vishay Siliconix** 

# **PCB Design and Assembly Guidelines For MICRO FOOT Products** 

_Johnson Zhao_ 

## INTRODUCTION 

Vishay Siliconix’s MICRO FOOT product family is based on a wafer-level chip-scale packaging (WL-CSP) technology that implements a solder bump process to eliminate the need for an outer package to encase the silicon die. MICRO FOOT products include power MOSFETs, analog switches, and power ICs. 

For battery powered compact devices, this new packaging technology reduces board space requirements, improves thermal performance, and mitigates the parasitic effect typical − of leaded packaged products.  For example, the 6 bump MICRO FOOT Si8902EDB common drain power MOSFET, which measures just 1.6 mm x 2.4 mm, achieves the same − performance as TSSOP 8 devices in a footprint that is 80% smaller and with a 50% lower height profile (Figure 1). A − MICRO FOOT analog switch, the 6 bump DG3000DB, offers − low charge injection and 1.4 W on resistance in a footprint measuring just 1.08 mm x 1.58 mm (Figure 2). 

Vishay Siliconix MICRO FOOT products can be handled with the same process techniques used for high-volume assembly of packaged surface-mount devices. With proper attention to PCB and stencil design, the device will achieve reliable performance without underfill. The advantage of the device’s small footprint and short thermal path make it an ideal option for space-constrained applications in portable devices such as battery packs, PDAs, cellular phones, and notebook computers. 

This application note discusses the mechanical design and reliability of MICRO FOOT, and then provides guidelines for board layout, the assembly process, and the PCB rework process. 

**FIGURE 1.** 3D View of MICRO FOOT  Products Si8902DB and Si8900EDB 

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3 2 1<br>0.18  ~ 0.25<br>A<br>0.5 1.08<br>B<br>0.285<br>L- s i+od-6tssi l |<br>0.5<br>0.285<br>1.58<br>ee<br>FIGURE 2.  Outline of MICRO FOOT CSP & Analog<br>Switch DG3000DB<br>**----- End of picture text -----**<br>


Document Number:  71990 06-Jan-03 

www.vishay.com 

**1** 

**AN824** 

**Vishay Siliconix** TABLE 1 ÁÁÁÁÁÁÁÁÁ **Main Parameters of Solder Bumps in MICRO FOOT Designs Á** ÁÁÁÁ **Á** ÁÁÁÁÁ **Á** ÁÁÁÁ **Á** ÁÁÁÁÁÁ **ÁÁÁÁÁÁÁÁÁÁ MICRO FOOT CSP ÁÁÁÁÁ Bump Material ÁÁÁÁÁÁ Bump Pitch* Bump Diameter* ÁÁÁÁÁÁÁÁÁÁÁ Bump Height*** MICRO FOOT  CSP MOSFET 0.8 0.37-0.41 0.26-0.29 **ÁÁÁÁÁÁÁÁÁÁ** MICRO FOOT CSP Analog Switch **ÁÁÁÁÁEutectic Solder:63Sm/37Pb ÁÁÁÁÁÁ** 0.5 **ÁÁÁÁÁ** 0.18-0.25 **ÁÁÁÁÁÁ** 0.14-0.19 **ÁÁÁÁÁÁÁÁÁÁ** ~~a~~ MICRO FOOT UCSP Analog Switch **ÁÁÁÁÁÁÁÁÁÁÁ** 0.5 **ÁÁÁÁÁ** 0.32-0.34 **ÁÁÁÁÁÁ** 0.21-0.24 * All measurements in millimeters **ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ** MICRO FOOT’S DESIGN AND RELIABILITY BOARD LAYOUT GUIDELINES 

_**Board materials**_ . Vishay Siliconix MICRO FOOT products are designed to be reliable on most board types, including organic boards such as FR-4 or polyamide boards. The package qualification information is based on the test on 0.5-oz. FR-4 and polyamide boards with NSMD pad design. 

As a mechanical, electrical, and thermal connection between the device and PCB, the solder bumps of MICRO FOOT products are mounted on the top active surface of the die. Table 1 shows the main parameters for solder bumps used in MICRO FOOT products. A silicon nitride passivation layer is applied to the active area as the last masking process in fabrication,ensuring that the device passes the pressure pot test. A green laser is used to mark the backside of the die without damaging it. Reliability results for MICRO FOOT products mounted on a FR-4 board without underfill are shown in Table 2. TABLE 2 **MICRO FOOT Reliability Results** ÁÁÁÁÁTest Condition C: − 65 to 150Á C **Á** ÁÁÁÁÁÁ>500 Cycles **ÁÁÁÁÁ** Test condition B: − 40 to 125 **ÁÁ** C **ÁÁÁÁÁÁ** >1000 Cycles 121 C @ 15PSI 100% Humidity Test 96 Hours ~~———~~ Á ÁÁÁÁÁÁ **Á** ÁÁÁÁÁÁ 

_**Land patterns.**_ Two types of land patterns are used for surface-mount packages. Solder mask defined (SMD) pads have a solder mask opening smaller than the metal pad (Figure 3), whereas on-solder mask defined (NSMD) pads have a metal pad smaller than the solder-mask opening (Figure 4). 

NSMD is recommended for copper etch processes, since it provides a higher level of control compared to SMD etch processes. A small-size NSMD pad definition provides more area (both lateral and vertical) for soldering and more room for escape routing on the PCB. By contrast, SMD pad definition introduces a stress ~~c~~ oncentration point near the solder mask on the PCB side that may result in solder joint cracking under extreme fatigue conditions. 

The main failure mechanism associated with wafer-level chip-scale packaging is fatigue of the solder joint. The results shown in Table 2 demonstrate that a high level of reliability can be achieved with proper board design and assembly techniques. 

Copper pads should be finished with an organic solderability preservative (OSP) coating. For electroplated nickel-immersion gold finish pads, the gold thickness must be less than 0.5 m to avoid solder joint embrittlement. Solder Mask Solder Mask ~~x =~~ Copper Copper ~~6 ©~~ 

**FIGURE 3.** SMD 

**FIGURE 4.** NSMD 

Document Number:  71990 06-Jan-03 

www.vishay.com 

**2** 

**AN824** 

**Vishay Siliconix** 

_**Board pad design.**_ The landing-pad size for MICRO FOOT products is determined by the bump pitch as shown in Table 3. The pad pattern is circular to ensure a symmetric, barrel-shaped solder bump. 

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TABLE 3<br>Dimensions of Copper Pad and Solder Mask<br>Opening in PCB and Stencil Aperture<br>ÁÁ Á ÁÁÁ Á Solder Mask ÁÁÁ Á ÁÁÁÁ Stencil<br>ÁÁ Pitch Á Copper Pad ÁÁÁ Á ÁÁÁ Opening Á ÁÁÁÁ Aperture<br>0.33   0.01 mm<br>ÁÁÁ 0.80 mm 0.30  Á  0.01 mm ÁÁ 0.41  Á  0.01 mm ÁÁÁ ÁÁ<br>in ciircle aperture<br>ÁÁÁÁÁÁÁÁÁÁÁÁ 0.30   0.01 mm ÁÁ<br>0.50 mm 0.17   0.01 mm 0.27   0.01 mm<br>ÁÁ Á Á Á Á Á Á Á in square apertureÁÁÁÁ<br>**----- End of picture text -----**<br>


## ASSEMBLY PROCESS 

MICRO FOOT products’ surface-mount-assembly operations include solder paste printing, component placement, and solder reflow as shown in the process flow chart (Figure 5). 

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Stencil Design<br>IIncoming Tape and Reel Inspection<br>Solder Paste Printing<br>|<br>Chip Placement<br>|<br>Reflow<br>|<br>Solder Joint Inspection<br>|<br>Pack and Ship<br>**----- End of picture text -----**<br>


**FIGURE 5.** SMT Assembly Process Flow 

_**Stencil design**_ . Stencil design is the key to ensuring maximum solder paste deposition without compromising the assembly yield from solder joint defects (such as bridging and extraneous solder spheres). The stencil aperture is dependent on the copper pad size, the solder mask opening, and the quantity of solder paste. 

In MICRO FOOT products, the stencil is 0.125 ~~-m~~ m (5-mils) thick. The recommended apertures are shown in Table 3 and are fabricated by laser cut. 

_**Solder-paste printing.**_ The solder-paste printing process involves transferring solder paste through pre-defined apertures via application of pressure. 

In MICRO FOOT products, the solder paste used is UP78 No-clean eutectic 63 Sn/37Pb type3 or finer solder paste. 

_**Chip pick-and-placement.**_ MICRO FOOT products can be picked and placed with standard pick-and-place equipment. The recommended pick-and-place force is 150 g. Though the part will self-center during solder reflow, the maximum placement offset is 0.02 mm. 

_**Reflow Process**_ .  MICRO FOOT products can be assembled using standard SMT reflow processes. Similar to any other package, the thermal profile at specific board locations must be determined. Nitrogen purge is recommended during reflow operation. Figure 6 shows a typical reflow profile. 

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Thermal Profile<br>250<br>200<br>— 150100 NXA\<br>50<br>feo™~<br>0 A<br>0 100 200 300 400<br>Time (Seconds<br>C)<br>Temperature (<br>**----- End of picture text -----**<br>


**FIGURE 6.** Reflow Profile 

## PCB REWORK 

To replace MICRO FOOT products on PCB, the rework procedure is much like the rework process for a standard BGA or CSP, as long as the rework process duplicates the original reflow profile. The key steps are as follows: 

1. Remove the MICRO FOOT device using a convection nozzle to create localized heating similar to the original reflow profile. Preheat from the bottom. 

2. Once the nozzle temperature is +190 C, use tweezers to remove the part to be replaced. 

3. Resurface the pads using a temperature-controlled soldering iron. 

4. Apply gel flux to the pad. 

5. Use a vacuum needle pick-up tip to pick up the replacement part, and use a placement jig to placed it accurately. 

6. Reflow the part using the same convection nozzle, and preheat from the bottom, matching the original reflow profile. 

Document Number:  71990 06-Jan-03 

www.vishay.com 

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**Legal Disclaimer Notice** Vishay 

www.vishay.com 

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## **Disclaimer** 

ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 

Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 

Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product.  To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability. 

Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications.  Such statements are not binding statements about the suitability of products for a particular application.  It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application.  Parameters provided in datasheets and/or specifications may vary in different applications and performance may vary over time.  All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein. 

Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk.  Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. 

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay.  Product names and markings noted herein may be trademarks of their respective owners. 

## **Material Category Policy** 

**Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (EEE) - recast, unless otherwise specified as non-compliant.** 

**Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.** 

**Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards.  Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition.  We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards.** 

Revision: 02-Oct-12 

Document Number: 91000 

**1** 



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