# Power MOSFET, P Channel, 60 V, 7.8 A, 0.28 ohm, TO-252 (DPAK), Surface Mount ![Product image](https://novapart.co/image/farnell:1505547/) **URL**: https://novapart.co/products/SFR9024TM/power-mosfet-p-channel-60-v-78-a-028-ohm-to-252 **SKU**: SFR9024TM **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.2090 **Stock**: 10+ ## Description Transistor Polarity:P Channel; Continuous Drain Current Id:-7.8A; Drain Source Voltage Vds:-60V; On Resistance Rds(on):0.28ohm; Rds(on) Test Voltage Vgs:-10V; Threshold Voltage Vgs:-4V; Power Dissip ## Specifications | Parameter | Value | |---|---| | No. Of Pins | 3Pins | | Channel Type | P Channel | | Product Range | - | | Qualification | - | | Power Dissipation | 32W | | Transistor Mounting | Surface Mount | | Rds(On) Test Voltage | 10V | | Transistor Case Style | TO-252 (DPAK) | | Drain Source Voltage Vds | 60V | | Operating Temperature Max | 150°C | | Continuous Drain Current Id | 7.8A | | Drain Source On State Resistance | 0.28ohm | | Gate Source Threshold Voltage Max | 4V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:1505547/) ## **Advanced Power MOSFET** ## **SFR/U9024** ## **FEATURES** - n Avalanche Rugged Technology - n Rugged Gate Oxide Technology - n Lower Input Capacitance - n Improved Gate Charge - n Extended Safe Operating Area - n Lower Leakage Current : 10 µA (Max.) @ VDS = -60V - n Lower RDS(ON) : 0.206 Ω (Typ.) **==> picture [93 x 145] intentionally omitted <==** **----- Start of picture text -----**
BVDSS = -60 V
R = 0.28 Ω
DS(on)
ID = -7.8 A
D-PAK I-PAK
2
1 1
3 23
1. Gate 2. Drain 3. Source
**----- End of picture text -----**
## **Absolute Maximum Ratings** |**Symbol**|**Characteristic**|**Value**|**Units**| |---|---|---|---| |**Symbol**
VDSS|Drain-to-Source Voltage|-60|V| |ID|Continuous Drain Current (TC=25
oC)
Continuous Drain Current (TC=100
oC)|-7.8
-5.5|A| |IDM|Drain Current-Pulsed
O1|31|A| |VGS|Gate-to-Source Voltage|±30|V| |EAS|Single Pulsed Avalanche Energy
O
2|155|mJ| |IAR|Avalanche Current
O1|-7.8|A| |EAR|Repetitive Avalanche Energy
O1|3.2|mJ| |dv/dt|Peak Diode Recovery dv/dt
O
3|-5.5|V/ns| |PD|Total Power Dissipation(TA=25
oC)
*|2.5|W| ||Total Power Dissipation (TC=25
oC)
Linear Derating Factor|32
0.26|W
W/
oC| |TJ, TSTG
TL|Operating Junction and
Storage Temperature Range
Maximum Lead Temp. for Soldering
Purposes, 1/8” from case for 5-seconds|- 55 to +150
300|oC| ## **Thermal Resistance** |RθJC
**Symbol**|Junction-to-Case
**Characteristic**|--
**Typ.**|3.91
**Max.**|oC/W
**Units**| |---|---|---|---|---| |RθJA|Junction-to-Ambient
*|--|50|| |RθJA|Junction-to-Ambient|--|110|| * When mounted on the minimum pad size recommended (PCB Mount). Rev. C **P-CHANNEL POWER MOSFET** ## **SFR/U9024** ## **Electrical Characteristics** (TC=25[o] C unless otherwise specified) |**Electri**|**cal Characteristics**(TC=25oC|unle|ss ot|herwi|se sp|ecified)| |---|---|---|---|---|---|---| |**Symbol**|**Characteristic**|**Min.**|**Typ.**|**Max. **|**Units**|**Test Condition**| |BVDSS|Drain-Source Breakdown Voltage|-60|--|--|V|VGS=0V,ID=-250µA| |∆BV/∆TJ|
Breakdown Voltage Temp. Coeff.|--|-0.04|--|V/
oC|ID=-250µA**_See Fig 7_**| |VGS(th)|Gate Threshold Voltage|-2.0|--|-4.0|V|VDS=-5V,ID=-250µA| |IGSS|Gate-Source Leakage , Forward|--|--|-100|nA|VGS=-20V| ||
Gate-Source Leakage , Reverse|--|--|100||VGS=20V| |IDSS|Drain-to-Source Leakage Current|--|--|-10|µA|VDS=-60V| |||--|--|-100||VDS=-48V,TC=125
oC| |RDS(on)|Static Drain-Source
On-State Resistance|--|--|0.28|Ω|VGS=-10V,ID=-3.9A
O
4| |gfs|Forward Transconductance|--|3.7|--|S|VDS=-30V,ID=-3.9A
O
4| |Ciss
Coss|Input Capacitance
Output Capacitance|--
--|140
465|600
215|pF|VGS=0V,VDS=-25V,f =1MHz
**_See Fig 5_**| |Crss|Reverse Transfer Capacitance|--|40|60||| |td(on)|Turn-On Delay Time|--|11|30|ns|VDD=-30V,ID=-9.7A,
RG=18
**_See Fig 13_**
Ω
O
5
O
4| |tr|Rise Time|--|21|50||| |td(off)|Turn-Off Delay Time|--|29|65||| |tf|Fall Time|--|20|50||| |Qg|Total Gate Charge|--|15|19|nC|VDS=-48V,VGS=-10V,
ID=-9.7A
**_See Fig 6 & Fig 12_**
O
5
O
4| |Qgs|Gate-Source Charge|--|2.9|--||| |Qgd|Gate-Drain(“Miller”) Charge|--|6.0|--||| ## **Source-Drain Diode Ratings and Characteristics** |**Symbol**|**Characteristic**|**Min.**|**Typ.**|**Max. **|**Units**|**Test Condition**| |---|---|---|---|---|---|---| |IS|Continuous Source Current|--|--|-7.8|A|Integral reverse pn-diode
in the MOSFET| |ISM|Pulsed-Source Current
O1|--|--|-31||| |VSD|Diode Forward Voltage
O
4|--|--|-3.8|V|TJ=25
oC,IS=-7.8A,VGS=0V| |trr|Reverse Recovery Time|--|80|--|ns|TJ=25
oC,IF=-9.7A
diF/dt=100A/µs
O
4| |Qrr|Reverse Recovery Charge|--|0.22|--|µC|| ## **Notes ;** O[1] Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature O2 L=3.0mH, IAS=-7.8A, VDD=-25V, RG=27Ω*, Starting TJ =25[o] C O3 ISD _< -9.7A, di/dt _< 250A/µs, VDD _< BVDSS , Starting TJ =25[o] C O4 Pulse Test : Pulse Width = 250µs, Duty Cycle 2%_< O5 Essentially Independent of Operating Temperature **SFR/U9024** ## **P-CHANNEL POWER MOSFET** **Fig 1. Output Characteristics** **==> picture [196 x 147] intentionally omitted <==** **----- Start of picture text -----**
VGS
Top : - 15 V
- 10 V
- 8.0 V
10 [1] - 7.0 V
- 6.0 V
- 5.5 V
- 5.0 V
Bottom : - 4.5 V
10 [0]
@ Notes :
1. 250 µ s Pulse Test
2. TC = 25 oC
10 [-1]
10 [-1] 10 [0] 10 [1]
-VDS , Drain-Source Voltage [V]
, Drain Current [A]-ID
**----- End of picture text -----**
**Fig 2. Transfer Characteristics** **==> picture [202 x 147] intentionally omitted <==** **----- Start of picture text -----**
10 [1]
150 oC
10 [0]
25 oC @ Notes :
1. VGS = 0 V
2. VDS = -30 V
- 55 oC 3. 250 µ s Pulse Test
10 [-1]
2 4 6 8 10
-VGS , Gate-Source Voltage [V]
, Drain Current [A]-ID
**----- End of picture text -----**
**Fig 3. On-Resistance vs. Drain Current** **Fig 4. Source-Drain Diode Forward Voltage** **==> picture [431 x 340] intentionally omitted <==** **----- Start of picture text -----**
0.40
0.35
10 [[1]]
0.30
VGS = -10 V
0.25
10 [[0]]
0.20
150 oCoCC
@ Notes :
0.15 VGS = -20 V @ Note : TJ = 25 [o] C 25 oCoCC 1. V 2. 250 GS = 0 V 2. 250 GS = 0 V µ s Pulse Test
0.10 10 [[-1]]
0 5 10 15 20 25 30 35 40 0.5 1.0 1.5 2.0 2.5 3.0 3.5
-ID , Drain Current [A] -VSD , Source-Drain Voltage [V]SD , Source-Drain Voltage [V] , Source-Drain Voltage [V]
Fig 5. Capacitance vs. Drain-Source Voltage Fig 6. Gate Charge vs. Gate-Source Voltage
800
Ciss= Cgs+ Cgd ( Cds= shorted )
Coss= Cds+ Cgd 10 VDS = -12 V
600 C iss Crss= Cgd VDSV = -48 VDS = -30 V
C oss
400
@ Notes : 5
1. VGS = 0 V
2. f = 1 MHz
200 C rss
@ Notes : ID =-9.7 A
0 0
10 [0] 10 [1] 0 4 8 12 16
-VDS , Drain-Source Voltage [V] QG , Total Gate Charge [nC]
]
Ω
, [
DS(on)
R
Drain-Source On-Resistance
, Reverse Drain Current [A]
DR
-I
Capacitance [pF]
, Gate-Source Voltage [V]
GS
-V
**----- End of picture text -----**
**==> picture [203 x 141] intentionally omitted <==** **----- Start of picture text -----**
10 [[1]]
10 [[0]]
150 oCoCC
@ Notes :
GS = 0 V = 0 V
25 oCoCC 1. V 2. 250 GS = 0 V 2. 250 GS = 0 V µ s Pulse Test
10 [[-1]]
0.5 1.0 1.5 2.0 2.5 3.0 3.5
-VSD , Source-Drain Voltage [V]SD , Source-Drain Voltage [V] , Source-Drain Voltage [V]
, Reverse Drain Current [A]
DR
-I
**----- End of picture text -----**
**P-CHANNEL POWER MOSFET** ## **SFR/U9024** **Fig 8. On-Resistance vs. Temperature** **==> picture [432 x 160] intentionally omitted <==** **----- Start of picture text -----**
Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature
1.2 2.5
2.0
1.1
1.5
1.0
1.0
0.9 @ Notes : @ Notes :
1. V 2. IGSD = -250 = 0 V µ A 0.5 1. V 2. IGSD = -4.9 A = -10 V
0.8 0.0
-75 -50 -25 0 25 50 75 100 125 150 175 -75 -50 -25 0 25 50 75 100 125 150 175 200
TJ , Junction Temperature [ [o] C] TJ , Junction Temperature [ [o] C]
, (Normalized) , (Normalized)
-BVDSS RDS(on)
Drain-Source On-Resistance
Drain-Source Breakdown Voltage
**----- End of picture text -----**
**Fig 9. Max. Safe Operating Area** **Fig 10. Max. Drain Current vs. Case Temperature** **==> picture [425 x 335] intentionally omitted <==** **----- Start of picture text -----**
8
Operation in This Area
10 [2] is Limited by R DS(on)
6
0.1 ms
10 [1] 1 ms
4
10 ms
DC
@ Notes :
10 [0] 1. TC = 25 [o] C
2. TJ = 150 [o] C 2
3. Single Pulse
10 [-1] 0
10 [0] 10 [1] 10 [2] 25 50 75 100 125 150
-VDS , Drain-Source Voltage [V] Tc , Case Temperature [ [o] C]
Fig 11. Thermal Response
D=0.5
@ Notes :
10 [0] 0.2 1. Z θ JC (t)=3.91 o C/W Max.
2. Duty Factor, D=t1 /t2
0.1 3. TJM -TC =PDM *Z θ JC (t)
0.05 P.DM
0.02
10 [-1] 0.01 t1.t2.
single pulse
10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1]
t1 , Square Wave Pulse Duration [sec]
, Drain Current [A]-ID
, Drain Current [A]-ID
(t) , Thermal Response
Z JC θ
**----- End of picture text -----**
**SFR/U9024** ## **P-CHANNEL POWER MOSFET** **Fig 12. Gate Charge Test Circuit & Waveform** **==> picture [385 x 177] intentionally omitted <==** **----- Start of picture text -----**
“ Current Regulator ”
Same Type VGS
50K Ω as DUT
Qg
12V 200nF
300nF -10V
VDS
VGS Qgs Qgd
DUT
-3mA
R1 R2
Charge
Current Sampling (IG) Current Sampling (ID)
Resistor Resistor
**----- End of picture text -----**
**Fig 13. Resistive Switching Test Circuit & Waveforms** **==> picture [439 x 290] intentionally omitted <==** **----- Start of picture text -----**
RL
Vout td(on) t on tr td(off) t off tf
Vin VDD
( 0.5 rated VDS ) Vin
RG 10%
DUT
-10V
90%
Vout
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
VDS LL EAS = ----12 LL IAS2 --------------------BVBVDSS -- VDSS DD
Vary tp to obtain ID t p Time
required peak ID
VDD VDS (t)
RG C VDD ID (t)
DUT
-10V IAS
t p BVDSS
**----- End of picture text -----**
**P-CHANNEL POWER MOSFET** ## **SFR/U9024** ## **Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms** **==> picture [310 x 465] intentionally omitted <==** **----- Start of picture text -----**
+
VDS
DUT
--
I S
L
Driver
VGS
RG Compliment of DUT(N-Channel) VDD
VGS • dv/dt controlled by “RG”
• IS controlled by Duty Factor “D”
Gate Pulse Width
VGS D = --------------------------Gate Pulse Period 10V
( Driver )
Body Diode Reverse Current
I S IRM
( DUT )
di/dt
IFM , Body Diode Forward Current
Vf
VDS
( DUT )
Body Diode VDD
Forward Voltage Drop
Body Diode Recovery dv/dt
**----- End of picture text -----**
**==> picture [64 x 7] intentionally omitted <==** **----- Start of picture text -----**
TRADEMARKS
**----- End of picture text -----**
**==> picture [439 x 623] intentionally omitted <==** **----- Start of picture text -----**
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
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the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life
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with instructions for use provided in the labeling, can be effectiveness.
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.
Preliminary First Production This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete Not In Production This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I1
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