# Dual MOSFET, N Channel, 60 V, 17 A, 0.039 ohm

![Product image](https://novapart.co/image/farnell:3616951/)

**URL**: https://novapart.co/products/NVMFD5877NLT3G/dual-mosfet-n-channel-60-v-17-a-0039-ohm
**SKU**: NVMFD5877NLT3G
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Dual MOSFETs
**Price**: €0.3310
**Stock**: 10+

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (15-Jan-2018) |
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Transistor Case Style | DFN |
| Operating Temperature Max | 175°C |
| Power Dissipation N Channel | 23W |
| Power Dissipation P Channel | - |
| Drain Source Voltage Vds N Channel | 60V |
| Drain Source Voltage Vds P Channel | - |
| Continuous Drain Current Id N Channel | 17A |
| Continuous Drain Current Id P Channel | - |
| Drain Source On State Resistance N Channel | 0.039ohm |
| Drain Source On State Resistance P Channel | - |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3616951/)

**Share Feedback DATA SHEET** Your Opinion Matters **www.onsemi.com** ~~ee~~ 

## MOSFET ~~—_~~ - Power, Dual **-** N Channel, Logic Level, Dual SO8FL 60 V, 39 m ; 17 A 

**V(BR)DSS RDS(on) MAX ID MAX** 39 m @ 10 V 60 V 17 A 60 m @ 4.5 V ~~eee~~ 

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**----- Start of picture text -----**<br>
Dual N-Channel<br>D1 D2<br>G1 G2<br>S1 S2<br>MARKING DIAGRAM<br>D1 D1<br>S1 D1<br>1 G1 5877xx D1<br>DFN8 5x6 S2 AYWZZ D2<br>(SO8FL) G2 D2<br>CASE 506BT(SO8FL)<br>D2 D2<br>**----- End of picture text -----**<br>


## NVMFD5877NL 

## **Features** 

- Low R to Minimize Conduction Losses DS(on) 

- Low Capacitance to Minimize Driver Losses 

- NVMFD5877NLWF − Wettable Flanks Option for Enhanced Optical Inspection 

- AEC-Q101 Qualified and PPAP Capable 

## **MARKING DIAGRAM** 

- These Devices are Pb-Free, Halogen Free and are RoHS Compliant 

## **MAXIMUM RATINGS** (TJ = 25 C unless otherwise noted) 

~~es~~ **Parameter Symbol** ~~ee ee~~ **Value Unit CASE 506BT(SO8FL)** G2 D2 D2 D2 Drain-to-Source Voltage VDSS 60 V ~~eeee ee~~ Gate-to-Source Voltage VGS 20 V 5877NL = Specific Device Code ~~ee~~ Continuous Drain Tmb = 25 C ~~ee~~ ID ~~ee~~ 17 ~~ee~~ A 5877LW = Specific Device Codefor NVMFD5877NL Current R(Notes 1, 2, 3, 4)J−mb Tmb = 100 C 12 for NVMFD5877NLWF Steady ~~—~~ A = Assembly Location Power Dissipation State Tmb = 25 C PD 23 W Y = Year 2, 3)R J−mb[ (Notes 1,] ~~[=—~~ Tmb = 100 C ~~—~~ 12 WZZ = Lot Traceability= Work Week Continuous Drain TA = 25 C ID 6 A Current R(Notes 1 & 3, 4)JA Steady TA = 100 C 5 Power DissipationR JA (Notes 1, 3) State TTAA = 100 = 25 CC PD 3.21.6 W See detailed ordering, marking and shipping information onpage 6 of this data sheet. **ORDERING INFORMATION** ~~rna ee oe~~ Pulsed Drain TA = 25 C, tp = 10 s IDM 74 A NOTE: Some of the devices on this data sheet have been **DISCONTINUED** . Please refer to the table on page 6. Current ~~Pf~~ Operating Junction and Storage Temperature TJ, Tstg −55 to C +175 ~~Pe~~ Source Current (Body Diode) IS 19 A ~~es~~ Single Pulse (IL(pk) = 14.5 A, EAS 10.5 mJ Drain-to-Source L = 0.1 mH) Avalanche Energy (TVDD = 24 V, VJ = 25GS =C, (IL = 2 mH)L(pk) = 6.3 A, 40 10 V, RG = 25 ) ~~ee~~ _ ee ~~|~~ Lead Temperature for Soldering Purposes ~~ee~~ TL ~~ee~~ 260 C (1/8 from case for 10 s) ~~ee ee~~ Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

Publication Order Number: **NVMFD5877NL/D** 

**1** 

 Semiconductor Components Industries, LLC, 2014 **May, 2025 − Rev. 11** 

**NVMFD5877NL** 

**THERMAL RESISTANCE MAXIMUM RATINGS** (Note 1) 

~~a~~ **Parameter Symbol Value Unit** Junction-to-Mounting Board (top) − Steady State (Note 2, 3) R J−mb 6.5 C/W ~~Be a~~ Junction-to-Ambient − Steady State (Note 3) R JA 47 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 

|2. Psi (<br>) is used as required per JESD51-12 for packages in which substantially less than 100% of the heat flows to single case surface.<br>3. Surface-mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.<br>4. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle.<br>**ELECTRICAL CHARACTERISTICS**(TJ= 25C unless otherwise specified)<br>**Parameter**<br>**Symbol**<br>**Test Condition**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>Ww~~Po~~|
|---|
|**OFF CHARACTERISTICS**|
|Drain-to-Source Breakdown Voltage<br>V(BR)DSS<br>VGS= 0 V, ID= 250 A<br>60<br>V<br>Drain-to-Source Breakdown Voltage<br>Temperature Coefficient<br>V(BR)DSS/TJ<br>53<br>mV/C<br>Zero Gate Voltage Drain Current<br>IDSS<br>VGS= 0 V,<br>VDS= 60 V<br>TJ= 25C<br>1.0<br>A<br>TJ= 125C<br>10<br>Gate-to-Source Leakage Current<br>IGSS<br>VDS= 0 V, VGS=20 V<br>100<br>nA<br>**ON CHARACTERISTICS**(Note 5)<br>Gate Threshold Voltage<br>VGS(TH)<br>VGS= VDS, ID= 250 A<br>1.0<br>3.0<br>V<br>Negative Threshold Temperature<br>Coefficient<br>VGS(TH)/TJ<br>3.5<br>mV/C<br>~~Oa~~<br>~~ee~~<br>~~ee rs~~<br>~~ee ee ee~~<br>~~pOa~~|
|Drain-to-Source On Resistance<br>RDS(on)<br>VGS= 10 V<br>ID= 7.5 A<br>31<br>39<br>m<br>VGS= 4.5 V<br>ID= 7.5 A<br>42<br>60<br>Forward Transconductance<br>gFS<br>VDS = 15 V, ID = 5.0 A<br>7.0<br>S<br>~~a~~<br>~~es~~<br>~~ee ee ee~~<br>~~GG~~|
|**CHARGES AND CAPACITANCES**|
|Input Capacitance<br>Ciss<br>VGS = 0 V, f = 1.0 MHz, VDS = 25 V<br>540<br>pF<br>Output Capacitance<br>Coss<br>55<br>Reverse Transfer Capacitance<br>Crss<br>36<br>Total Gate Charge<br>QG(TOT)<br>VGS = 4.5 V, VDS = 48 V,<br>ID = 5.0 A<br>5.9<br>nC<br>Threshold Gate Charge<br>QG(TH)<br>0.62<br>Gate-to-Source Charge<br>QGS<br>1.64<br>Gate-to-Drain Charge<br>QGD<br>2.80<br>Total Gate Charge<br>QG(TOT)<br>VGS = 10 V, VDS = 48V, ID = 5.0A<br>11<br>20<br>nC<br>**SWITCHING CHARACTERISTICS**(Note 6)<br>~~po~~<br>~~a~~<br>~~a~~<br>~~po~~<br>~~|~~<br>~~po~~<br>~~ee~~<br>~~po~~<br>~~ee~~<br>~~po~~<br>~~ee~~<br>~~po~~<br>~~ee~~<br>~~ee ee~~<br>~~ee~~<br>~~po~~|
|Turn-On Delay Time<br>td(on)<br>VGS= 4.5 V, VDS= 48 V,<br>ID= 5.0 A, RG= 2.5<br>8.1<br>ns<br>Rise Time<br>tr<br>15.8<br>Turn-Off Delay Time<br>td(off)<br>11.8<br>Fall Time<br>tf<br>3.9<br>Turn-On Delay Time<br>td(on)<br>VGS= 10 V, VDS= 48 V,<br>ID= 5.0 A, RG= 2.5<br>4.9<br>ns<br>Rise Time<br>tr<br>6.4<br>Turn-Off Delay Time<br>td(off)<br>14.5<br>Fall Time<br>tf<br>2.4<br>5. Pulse Test: pulse width = 300 s, duty cycle2%.<br>~~po~~<br>~~a~~<br>~~po~~<br>,<br>~~~-}~~<br>~~|~~<br>~~po~~<br>~~a~~<br>~~po~~<br>~~a~~<br>~~po~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>,<br>~~~-)~~<br>~~| oo~~<br>~~po~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~a~~<br>u|



6. Switching characteristics are independent of operating junction temperatures. 

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## **NVMFD5877NL** 

**ELECTRICAL CHARACTERISTICS** (TJ = 25 C unless otherwise specified)  (continued) 

|**Parameter**<br>**Unit**<br>**Max**<br>**Typ**<br>**Min**<br>**Test Condition**<br>**Symbol**<br>**DRAIN-SOURCE DIODE CHARACTERISTICS**<br>~~Po~~|
|---|
|Forward Diode Voltage<br>VSD<br>VGS= 0 V,<br>IS= 5.0 A<br>TJ= 25C<br>0.8<br>1.2<br>V<br>TJ= 125C<br>0.7<br>Reverse Recovery Time<br>tRR<br>VGS= 0 V, dIS/dt= 100 A/ s,<br>IS= 5.0 A<br>14.5<br>ns<br>Charge Time<br>ta<br>11.5<br>Discharge Time<br>tb<br>3.1<br>Reverse Recovery Charge<br>QRR<br>11<br>nC<br>**PACKAGE PARASITIC VALUES**<br>~~rs~~<br>~~rs~~<br>~~ee ee~~<br>~~po~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>ee<br>~~ee ee~~<br>~~po~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~a a~~<br>~~ee~~|
|Source Inductance<br>LS<br>TA= 25C<br>0.93<br>nH<br>Drain Inductance<br>LD<br>0.005<br>Gate Inductance<br>LG<br>1.84<br>Gate Resistance<br>RG<br>1.5<br>5. Pulse Test: pulse width = 300 s, duty cycle2%.<br>~~ee~~<br>~~ee~~<br>~~a a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~po~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~es ee ee~~|



6. Switching characteristics are independent of operating junction temperatures. 

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

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## **TYPICAL CHARACTERISTICS** 

**==> picture [493 x 627] intentionally omitted <==**

**----- Start of picture text -----**<br>
40 30<br>36 ey VGS = 10 V 5 V TJ = 25C VDS  10 V<br>4 ee ee ee e/a<br>32 4.5 V<br>28 ey Cr Lt |<br>se 20 ee<br>24<br>Ah<br>20 |(UY—— 4.0 V fF<br>16 TJ = 25C<br>s/s 10  a<br>12<br>pj} | ft ‘ff<br>8 3.5 V<br>40 Ea——————— 3.0 V 0 |eeFe TJ = 125C TJ = −55C<br>0 1 2 3 4 5 1 2 3 4 5<br>VDS, DRAIN-TO-SOURCE VOLTAGE (V) VGS, GATE-TO-SOURCE VOLTAGE (V)<br>Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics<br>0.065 0.065<br>0.0600.055 PEee T IDJ  = 25  = 10 A C 0.0550.060 aa TJ = 25C<br>0.050 PY 0.050<br>VGS = 4.5 V<br>0.045 0.045<br>TA E e e<br>0.040 TINE 0.040 Ge eT<br>0.035 0.035<br>VGS = 10 V<br>ee<br>0.030 ge 0.030<br>0.025 Peer 0.025 C O E<br>3 4 5 6 7 8 9 10 5 8 10 13 15 18 20 23 25<br>VGS, GATE-TO-SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 3. On-Resistance vs. Gate-to-Source Figure 4. On-Resistance vs. Drain Current and<br>Voltage Gate Voltage<br>2.1 1E−04<br>ID = 7.5 A VGS = 0 V<br>1.9 1E−05<br>V GS  = 10 V TJ = 150C<br>1.7 Po | | yy | | 1E−06  — Y  _— E S S<br>1.5 ttt} 1E−07 TJ = 125C<br>1.3 ee an| 1E−08 eBea = ]<br>1.1 BD 1E−09<br>46 ee e SS Sa<br>0.9 [ett| | | | 1E−10 lhB e TJ = 25C<br>0.7 Peet 1E−11<br>0.5 7r_ | |tT |tlt lt ct 1E−12 EESSS SS S SSS S SSSS<br>−50 −25 0 25 50 75 100 125 150 175 5 10 15 20 25 30 35 40 45 50 55 60<br>TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (V)<br>Figure 5. On-Resistance Variation with Figure 6. Drain-to-Source Leakage Current vs.<br>Temperature Voltage<br>, DRAIN CURRENT (A) , DRAIN CURRENT (A)<br>ID ID<br>) )<br>, DRAIN-TO-SOURCE RESISTANCE ( , DRAIN-TO-SOURCE RESISTANCE (<br>DS(on) DS(on)<br>R R<br>, LEAKAGE (A)<br>IDSS<br>, DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


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## **TYPICAL CHARACTERISTICS** 

**==> picture [491 x 181] intentionally omitted <==**

**----- Start of picture text -----**<br>
800 10<br>VGS = 0 V 9 Q T<br>700 ee Ciss TJ = 25C 8 Sa eeee<br>600<br>500 a S E 7 SEE EEE<br>6<br>400 re ee e e 5 PET Ar<br>300 OE 4 Qgs Qgd<br>200 Oe 3 T J  = 25  C<br>HT Coss 2 VDD = 48 V<br>100 a ee Oe 1 ID = 5 A<br>0 e Crss e 0 Ae<br>0 5 10 15 20 25 30 0 1 2 3 4 5 6 7 8 9 10 11<br>DRAIN-TO-SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)<br>C, CAPACITANCE (pF)<br>, GATE-TO-SOURCE VOLTAGE (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


**Figure 7. Capacitance Variation** 

**Figure 8. Gate-to-Source vs. Gate Charge** 

**==> picture [492 x 393] intentionally omitted <==**

**----- Start of picture text -----**<br>
1000 40<br>VDD = 48 V VGS = 0 V<br>VIDGS = 5 A = 10 V a a ee ee TJ = 25C<br>30<br>100<br>td(off)<br>tf<br>a e 20 eee<br>a eeeoe tr LT<br>10 td(on)<br>ate r 10 TTT yy<br>1 a ee ee ee el 0 WA<br>1 10 100 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0<br>RG, GATE RESISTANCE ( Q ) VSD, SOURCE-TO-DRAIN VOLTAGE (V)<br>Figure 9. Resistive Switching Time Variation Figure 10. Diode Forward Voltage<br>vs. Gate Resistance<br>100<br>10 s<br>a<br>100 s<br>10<br>pA UUTNINNE ET<br>1  m s<br>| 4 VGS = 20 V MEE, Sa 10 ms m r<br>1 Single Pulse<br>TC = 25C<br>RDS(on) Limit dc<br>Thermal Limit PTTET TTT<br>0.1 Package Limit nv<br>0.1 1 10 100<br>VDS, DRAIN VOLTAGE (V)<br>t, TIME (ns)<br>, SOURCE CURRENT (A)<br>IS<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Rated Forward Biased Safe Operating Area** 

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**NVMFD5877NL** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [492 x 179] intentionally omitted <==**

**----- Start of picture text -----**<br>
100<br>ee——== =. ——eee=). ee== 2 ee==. eee= =. eee== ==. ==. a<br>ER Duty Cycle = 0.5 Aeeeeee eeei ee ees<br>0.2<br>10 eee| TimiLd =Rmim=...— anei",ttlla a<br>FE 0.1 aeeS==.... SS = = ESre____—_. oeeenn — | ||<br>i 0.05 =---- a=!8AO 0 A OO 0 0<br>0.02<br>1 hhLrpTrHIUI TT| TTTTTTTTETTEET tTEETTT<br>© ai— 0.01 aceeHaOB2OOOs ee<br>EttLL Lert, TT TT TT Device Mounted on 650 mm [2] LTT<br>0.1 Single Pulse 2 oz Cu PCB<br>peer—<—=SS TTFpTE TT pp milEE<br>SSa  RSAA EE SBSH GNOOeH SH OOOBeeOO SH Oe OO 2<br>0.01<br>0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000<br>PULSE TIME (sec)<br>C/W)<br><br> (<br>JA(t)<br>R<br>**----- End of picture text -----**<br>


**Figure 12. Thermal Response** 

## **DEVICE ORDERING INFORMATION** 

|**Device**|**Marking**|**Package**|**Shipping**†|
|---|---|---|---|
|NVMFD5877NLWFT1G-UM|5877LW|DFN8|1500 / Tape & Reel|
|||(Pb-Free)||
|**DISCONTINUED**(Note 7)||||
|NVMFD5877NLT1G|5877NL|DFN8|1500 / Tape & Reel|
|||(Pb-Free)||
|NVMFD5877NLWFT1G|5877LW|DFN8|1500 / Tape & Reel|
|||(Pb-Free)||
|NVMFD5877NLT3G|5877NL|DFN8|5000 / Tape & Reel|
|||(Pb-Free)||
|NVMFD5877NLWFT3G|5877LW|DFN8|5000 / Tape & Reel|
|||(Pb-Free)||



† For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

7. **DISCONTINUED:** These devices are not recommended for new design. Please contact your **onsemi** representative for information. The most current information on these devices may be available on www.onsemi.com. 

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**6** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**==> picture [51 x 34] intentionally omitted <==**

**DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)** CASE 506BT ISSUE F 

DATE 23 NOV 2021 

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**----- Start of picture text -----**<br>
1 DATE 23 NOV 2021<br>SCALE 2:1 2X NOTES:<br>0.20 C 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.<br>2. CONTROLLING DIMENSION: MILLIMETERS.<br>D A 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED<br>BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.<br>8 7 D16 5 B 2X 0.20 C 4.5. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELLAS THE TERMINALS.DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,PROTRUSIONS, OR GATE BURRS.<br>6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED<br>AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST<br>POINT ON THE PACKAGE BODY.<br>7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.<br>PIN ONE E1 E MILLIMETERS<br>IDENTIFIER<br>ÉÉ DIM MIN NOM MAX<br>NOTE 7 A 0.90 −−− 1.10<br>ÉÉ 4Xh A1b 0.33−−− 0.42−−− 0.050.51<br>1 2 3 4 b1 0.33 0.42 0.51<br>ÉÉ c 0.20 −−− 0.33<br>TOP VIEW c A1 D 5.15 BSC<br>D1 4.70 4.90 5.10<br>0.10 C D2 3.90 4.10 4.30<br>A D3 1.50 1.70 1.90<br>DETAIL B E 6.15 BSC<br>0.10 C ALTERNATE E1 5.70 5.90 6.10<br>NOTE 4 SIDE VIEW C [SEATING] PLANE DETAIL A CONSTRUCTION E2e 3.90 1.27 BSC4.15 4.40<br>DETAIL A NOTE 6 G 0.45 0.55 0.65<br>h −−− −−− 12    �<br>D2 K 0.51 −−− −−−<br>D3 K1 0.56 −−− −−−<br>L 0.48 0.61 0.71<br>e 4X L M 3.25 3.50 3.75<br>1 4 K N 1.80 2.00 2.20<br>DETAIL B SOLDERING FOOTPRINT*<br>4.56<br>M N 4Xb1 E2 0.758X 2.082X 0.562X<br>8 5<br>4X G 8X b<br>K1 0.10 C A B 4X<br>4.84 1.40 6.59<br>BOTTOM VIEW 0.05 C NOTE 3 2.30<br>3.70<br>GENERIC<br>MARKING DIAGRAM*<br>0.70<br>1<br>XXXXXX<br>AYWZZ 4X 1.00 1.27<br>PITCH<br>XXXXXX = Specific Device Code 5.55<br>A = Assembly Location DIMENSION: MILLIMETERS<br>Y = Year<br>*For additional information on our Pb−Free strategy and soldering<br>W = Work Week details, please download the  onsemi  Soldering and Mounting<br>ZZ = Lot Traceability Techniques Reference Manual, SOLDERRM/D.<br>**----- End of picture text -----**<br>


7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA. 

**==> picture [207 x 186] intentionally omitted <==**

**----- Start of picture text -----**<br>
4.56<br>2X 2X<br>8X 2.082X 0.562X<br>0.758X<br>4X<br>4.84 1.40 6.59<br>2.30<br>3.70<br>0.70<br>4X 1.00 1.27<br>PITCH<br>5.55<br>DIMENSION: MILLIMETERS<br>**----- End of picture text -----**<br>


   - *For additional information on our Pb−Free strategy and soldering details, please download the **onsemi** Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

- *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ � ”, may or may not be present. Some products may not follow the Generic Marking. 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

## **DOCUMENT NUMBER: 98AON50417E** 

**DESCRIPTION: DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL)** 

**PAGE 1 OF 1** 

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**onsemi** , , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of **onsemi** ’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. **onsemi** reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and **onsemi** makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using **onsemi** products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by **onsemi** . “Typical” parameters which may be provided in **onsemi** data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. **onsemi** does not convey any license under any of its intellectual property rights nor the rights of others. **onsemi** products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use **onsemi** products for any such unintended or unauthorized application, Buyer shall indemnify and hold **onsemi** and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that **onsemi** was negligent regarding the design or manufacture of the part. **onsemi** is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **ADDITIONAL INFORMATION** 

**TECHNICAL PUBLICATIONS** : **ONLINE SUPPORT** : www.onsemi.com/support **Technical Library:** www.onsemi.com/design/resources/technical−documentation **For additional information, please contact your local Sales Representative at onsemi Website:** www.onsemi.com www.onsemi.com/support/sales 

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## Links

- [View this product on Novapart](https://novapart.co/products/NVMFD5877NLT3G/dual-mosfet-n-channel-60-v-17-a-0039-ohm)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/on-semiconductor/nvmfd5877nlt3g/dual-mosfet/dp/3616951)
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