# Power MOSFET, N Channel, 60 V, 89 A, 0.0041 ohm, TO-252 (DPAK), Surface Mount ![Product image](https://novapart.co/image/farnell:3368858/) **URL**: https://novapart.co/products/NVD5C648NLT4G/power-mosfet-n-channel-60-v-89-a-00041-ohm-to-252 **SKU**: NVD5C648NLT4G **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €1.0700 **Stock**: 1000+ **Lead Time**: 141 days (indicative) ## Specifications | Parameter | Value | |---|---| | Svhc | Lead (25-Jun-2025) | | No. Of Pins | 3Pins | | Channel Type | N Channel | | Product Range | - | | Qualification | AEC-Q101 | | Power Dissipation | 72W | | Transistor Mounting | Surface Mount | | Rds(On) Test Voltage | 10V | | Transistor Case Style | TO-252 (DPAK) | | Drain Source Voltage Vds | 60V | | Operating Temperature Max | 175°C | | Continuous Drain Current Id | 89A | | Drain Source On State Resistance | 0.0041ohm | | Gate Source Threshold Voltage Max | 2.1V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:3368858/) ## NVD5C648NL MOSFET – Power, Single N-Channel ~~——~~ 60 V, 4.1 m 89 A ## **Features** - Low R to Minimize Conduction Losses DS(on) - Low QG and Capacitance to Minimize Driver Losses - AEC−Q101 Qualified and PPAP Capable - These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant **www.onsemi.com** **==> picture [190 x 33] intentionally omitted <==** **----- Start of picture text -----**
ee V(BR)DSS RDS(on) ee ee ID
4.1 m @ 10 V
60 V 89 A
**----- End of picture text -----**
60 V 5.7 m @ 4.5 V |**MAXIMUM RATINGS**(TJ= 25°C unless otherwise noted)
**Parameter**
**Symbol**
**Value**
**Unit**
Drain−to−Source Voltage
VDSS
60
V
Gate−to−Source Voltage
VGS
20
V
Continuous Drain Cur-
rent R JC(Notes 1 & 3)
Steady
State
TC= 25°C
ID
89
A
TC= 100°C
63
Power Dissipation R JC
(Note 1)
TC= 25°C
PD
72
W
TC= 100°C
36
Continuous Drain Cur-
rent R JA(Notes 1, 2 &
3)
Steady
State
TA= 25°C
ID
18
A
TA= 100°C
13
Power Dissipation R JA
(Notes 1 & 2)
TA= 25°C
PD
3.1
W
TA= 100°C
1.5
Pulsed Drain Current
TA= 25°C, tp= 10 s
IDM
510
A
Operating Junction and Storage Temperature
TJ, Tstg
−55 to
175
°C
~~ee~~
~~es ee~~
~~a~~
~~SSS ~~
~~——o—e~~
~~TSS~~
~~a~~
~~ee~~|**DPAK**
**CASE 369C**
**STYLE 2**
1 2
3
4
G
S
**N−CHANNEL MOSFET**
D
~~&~~
ef|**DPAK**
**CASE 369C**
**STYLE 2**
1 2
3
4
G
S
**N−CHANNEL MOSFET**
D
~~&~~
ef| |---|---|---| |Source Current (Body Diode)
IS
85
A
Single Pulse Drain−to−Source Avalanche
Energy (TJ= 25°C, IL(pk)= 7.0 A)
EAS
223
mJ
Lead Temperature for Soldering Purposes
(1/8″from case for 10 s)
TL
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
**THERMAL RESISTANCE MAXIMUM RATINGS**
~~ee~~
~~ee~~|**MARKING DIAGRAM**
**& PIN ASSIGNMENT**
2
4
Drain
AYWW
5C
648LG
~~—~~|| |**Parameter**
**Symbol**
**Value**
**Unit**
~~es~~
~~ee~~|1
Gate
Drain 3
Source|| |Junction−to−Case (Drain) (Note 1)
R JC
2.07
°C/W|A
= Assembly Location|= Assembly Location| |Junction−to−Ambient − SteadyState(Note 2)
R JA
48.1|Y
= Year|| |1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.|WW
= Work Week
5C648L = Device Code
G
= Pb−Free Package|| 2. Surface−mounted on FR4 board using a 650 mm[2] , 2 oz. Cu pad. 3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. ## **ORDERING INFORMATION** See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Publication Order Number: **NVD5C648NL/D** **1** © Semiconductor Components Industries, LLC, 2017 **June, 2019 − Rev. 0** ## **NVD5C648NL** ## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) |**ELECTRICAL CHARACTERISTICS **(TJ|= 25°C unless|otherwise noted)|otherwise noted)||||| |---|---|---|---|---|---|---|---| |**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**| |**OFF CHARACTERISTICS**|||||||| |Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID=|250�A|60|||V| |Drain−to−Source Breakdown Voltage
Temperature Coefficient|V(BR)DSS/TJ||||24||mV/°C| |Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,
VDS= 60 V|TJ= 25°C|||10|�A| ||||TJ= 125°C|||250|| |Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS= 20 V||||100|nA| |**ON CHARACTERISTICS**(Note 4)|||||||| |Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 250�A||1.2||2.1|V| |Negative Threshold Temperature Coefficient|VGS(TH)/TJ||||5.2||mV/°C| |Drain−to−Source On Resistance|RDS(on)|VGS= 10 V, ID= 45 A|||3.4|4.1|m�| |||VGS= 4.5 V, ID= 45 A|||4.6|5.7|| |Forward Transconductance|gFS|VDS= 5.0 V, ID= 45 A|||120||S| |**CHARGES, CAPACITANCES AND GATE RESISTANCES**|||||||| |Input Capacitance|Ciss|VGS= 0 V, f = 1.0 MHz,
VDS= 25 V|||2900||pF| |Output Capacitance|Coss||||1300||| |Reverse Transfer Capacitance|Crss||||28||| |Total Gate Charge|QG(TOT)|VDS= 48 V,
ID= 45 A|VGS= 4.5 V||17||nC| ||||VGS= 10 V||39||| |Threshold Gate Charge|QG(TH)|VGS= 4.5 V, VDS= 48 V,
ID= 45 A|||4.8||nC| |Gate−to−Source Charge|QGS||||8.8||| |Gate−to−Drain Charge|QGD||||3.5||| |Plateau Voltage|VGP||||3.2||V| |**SWITCHING CHARACTERISTICS**(Note 5)|||||||| |Turn−On Delay Time|td(on)|VGS= 4.5 V, VDS= 48 V,
ID= 45 A, RG= 2.5�|||21||ns| |Rise Time|tr||||91||| |Turn−Off Delay Time|td(off)||||47||| |Fall Time|tf||||68||| |**DRAIN−SOURCE DIODE CHARACTERISTICS**|||||||| |Forward Diode Voltage|VSD|VGS= 0 V,
IS= 45 A|TJ= 25°C||0.9|1.2|V| ||||TJ= 125°C||0.8||| |Reverse Recovery Time|tRR|VGS= 0 V, dIs/dt
IS= 45|= 100 A/�s,
A||47||ns| |Charge Time|ta||||23||| |Discharge Time|tb||||24||| |Reverse Recovery Charge|QRR||||30||nC| 4. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%. 5. Switching characteristics are independent of operating junction temperatures. **www.onsemi.com** **2** **NVD5C648NL** ## **TYPICAL CHARACTERISTICS** **==> picture [491 x 591] intentionally omitted <==** **----- Start of picture text -----**
180 180
VGS = 10 V to 4.5 V VDS = 5 V
3.6 V
150 150
3.4 V
120 120
90 3.2 V 90
60 3.0 V 60 TJ = 25 ° C
2.8 V
30 30
2.6 V
0 2.4 V 0 TJ = 125 ° C TJ = −55 ° C
0 0.5 1.0 1.5 2.0 2.5 0 1 2 3 4 5
VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
45 8
40 ITDJ = 45 A = 25 ° C 7 TJ = 25 ° C
35
6
30 5 VGS = 4.5 V
25
4
20
15 3 V GS = 10 V
2
10
5 1
0 0
3 4 5 6 7 8 9 10 10 30 50 70 90 110 130 150 170
VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and
Voltage Gate Voltage
2.0 100K
VGS = 10 V TJ = 150 ° C
1.8 ID = 45 A 10K
1.6 1K TJ = 125 ° C
1.4 100 TJ = 85 ° C
1.2 10
1.0 1
0.8 0.1 TJ = 25 ° C
0.6 0.01
−50 −25 0 25 50 75 100 125 150 175 5 10 15 20 25 30 35 40 45 50 55
TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)
, DRAIN CURRENT (A) , DRAIN CURRENT (A)
ID ID
) � ) �
, DRAIN−TO−SOURCE RESISTANCE (m , DRAIN−TO−SOURCE RESISTANCE (m
DS(on) DS(on)
R R
, LEAKAGE (nA)
, NORMALIZED DRAIN−TO− IDSS
SOURCE RESISTANCE
DS(on)
R
**----- End of picture text -----**
**Figure 5. On−Resistance Variation with Temperature** **Figure 6. Drain−to−Source Leakage Current vs. Voltage** **www.onsemi.com** **3** **NVD5C648NL** ## **TYPICAL CHARACTERISTICS** **==> picture [242 x 382] intentionally omitted <==** **----- Start of picture text -----**
10K
CISS
1K
COSS
100
10 CRSS
VGS = 0 V
TJ = 25 ° C
f = 1 MHz
1
0 10 20 30 40 50 60
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
1000
100 tr
tf
td(off)
td(on)
10
VGS = 4.5 V
VDS = 48 V
ID = 45 A
1
1 10 100
RG, GATE RESISTANCE ( � )
C, CAPACITANCE (pF)
t, TIME (ns)
**----- End of picture text -----**
**Figure 9. Resistive Switching Time Variation vs. Gate Resistance** **==> picture [241 x 382] intentionally omitted <==** **----- Start of picture text -----**
10
9 V DS = 48 V
ID = 45 A
8 T J = 25 ° C
7
6
5
4 QGS QGD
3
2
1
0
0 5 10 15 20 25 30 35 40
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source vs. Total Charge
100
VGS = 0 V
10
1
T J = 125 ° C T J = 25 ° C T J = −55 ° C
0.1
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
, GATE−TO−SOURCE VOLTAGE (V)
GS
V
, SOURCE CURRENT (A)
IS
**----- End of picture text -----**
**Figure 10. Diode Forward Voltage vs. Current** **==> picture [492 x 173] intentionally omitted <==** **----- Start of picture text -----**
1000 100
100
TJ(initial) = 25 ° C
10 10
VSingle PulseGS ≤ 10 V 10 � s TJ(initial) = 100 ° C
1 TC = 25 ° C 0.5 ms
RDS(on) Limit 1 ms
Thermal Limit 10 ms
Package Limit
0.1 1
0.1 1 10 100 1000 0.00001 0.0001 0.001 0.01
VDS, DRAIN−TO−SOURCE VOLTAGE (V) TIME IN AVALANCHE (s)
, (A)
IPEAK
, DRAIN CURRENT (A)
ID
**----- End of picture text -----**
**Figure 11. Maximum Rated Forward Biased Safe Operating Area** **Figure 12. Maximum Drain Current vs. Time in Avalanche** **www.onsemi.com** **4** **NVD5C648NL** ## **TYPICAL CHARACTERISTICS** **==> picture [491 x 173] intentionally omitted <==** **----- Start of picture text -----**
10
Duty Cycle = 50%
1
20%
10%
5%
0.1
2%
1%
0.01 Single Pulse
0.001
1E−06 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
PULSE TIME (sec)
C/W)
°
R(t) (
**----- End of picture text -----**
**Figure 13. Thermal Response** ## **ORDERING INFORMATION** |**ORDERING INFORMATION**||| |---|---|---| |**Order Number**|**Package**|**Shipping**†| |NVD5C648NLT4G|DPAK
(Pb−Free)|2500 / Tape & Reel| †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. **www.onsemi.com** **5** **NVD5C648NL** ## **PACKAGE DIMENSIONS** **==> picture [481 x 449] intentionally omitted <==** **----- Start of picture text -----**
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
NOTES:
A 1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
E C 2. CONTROLLING DIMENSION: INCHES.
A 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
b3 B c2 4. DIMENSIONS D AND E DO NOT INCLUDE MOLDMENSIONS b3, L3 and Z.
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
4 NOT EXCEED 0.006 INCHES PER SIDE.
L3 bly oy Z 5. DIMENSIONS D AND E ARE DETERMINED AT THE
D DETAIL A H OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
1 2 3 PLANE H.
7. OPTIONAL MOLD FEATURE.
L4 NOTE 7 DIM MININCHESMAX MILLIMETERSMIN MAX
b2 c BOTTOM VIEW A 0.086 0.094 2.18 2.38
e SIDE VIEW A1 0.000 0.005 0.00 0.13
b b 0.025 0.035 0.63 0.89
TOP VIEW 0.005 (0.13) M C b2b3 0.0280.180 0.0450.215 0.724.57 1.145.46
c 0.018 0.024 0.46 0.61
c2 0.018 0.024 0.46 0.61
H Z Z D 0.235 0.245 5.97 6.22
E 0.250 0.265 6.35 6.73
e 0.090 BSC 2.29 BSC
L2 [GAUGE] PLANE C SEATINGPLANE H 0.370 0.410 9.40 10.41
L 0.055 0.070 1.40 1.78
L1 0.114 REF 2.90 REF
L2 0.020 BSC 0.51 BSC
L L3 0.035 0.050 0.89 1.27
A1 BOTTOM VIEW L4 −−− 0.040 −−− 1.01
chy L1 ? a CONSTRUCTIONSALTERNATE A. Z 0.155 −−− 3.93 −−−
DETAIL A
ROTATED 9 CW SOLDERING FOOTPRINT* STYLE 2:
PIN 1. GATE
6.20 3.00 2.3. DRAINSOURCE
0.244 0.118 4. DRAIN
2.58
PET
0.102
5.80
1.60 6.17
0.228
0.063 0.243
Ls"
SCALE 3:1 mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
**----- End of picture text -----**
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