# Power MOSFET, P Channel, 20 V, 8.8 A, 0.014 ohm, SOIC, Surface Mount
**URL**: https://novapart.co/products/NTMS10P02R2G/power-mosfet-p-channel-20-v-88-a-0014-ohm-soic
**SKU**: NTMS10P02R2G
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.5670
**Stock**: 1000+
**Lead Time**: 134 days (indicative)
## Description
Transistor Polarity:P Channel; Continuous Drain Current Id:-8.8A; Drain Source Voltage Vds:-20V; On Resistance Rds(on):0.012ohm; Rds(on) Test Voltage Vgs:-4.5V; Threshold Voltage Vgs:-8
## Specifications
| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 8Pins |
| Channel Type | P Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 1.6W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 4.5V |
| Transistor Case Style | SOIC |
| Drain Source Voltage Vds | 20V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 8.8A |
| Drain Source On State Resistance | 0.014ohm |
| Gate Source Threshold Voltage Max | 880mV |
## Datasheet
📄 [Download PDF](https://novapart.co/datasheet/farnell:2533197/)
## NTMS10P02R2
## MOSFET – Power, Single, P-Channel, Enhancement Mode, SOIC-8 -10 Amps, -20 Volts
## **Features**
- Ultra Low RDS(on)
- Higher Efficiency Extending Battery Life
- Logic Level Gate Drive
- Miniature SOIC−8 Surface Mount Package
- Diode Exhibits High Speed, Soft Recovery
- Avalanche Energy Specified
- SOIC−8 Mounting Information Provided
- Pb−Free Package is Available
## **Applications**
- Power Management in Portable and Battery−Powered Products, i.e.: Cellular and Cordless Telephones and PCMCIA Cards
## **http://onsemi.com**
## **−10 AMPERES**
## **−20 VOLTS**
**14 m** Q **@ VGS = −4.5 V**
**==> picture [65 x 91] intentionally omitted <==**
**----- Start of picture text -----**
P−Channel
D
G
S
**----- End of picture text -----**
## **MAXIMUM RATINGS**
|**MAXIMUM RATINGS**|~~ee~~|~~ee~~||
|---|---|---|---|
|**Rating**
~~ee~~
~~ee~~|**Symbol**
~~ee~~
~~ee~~
~~ee~~|**Value**
~~ee~~
~~ee~~
~~ee~~|**Unit**
~~ee~~|
|Drain−to−Source Voltage
~~ee~~
~~ee~~|VDSS
~~ee~~
~~ee~~
~~ee~~
ee|−20
~~ee~~
~~ee~~
~~ee~~|Vdc
~~ee~~|
|Gate−to−Source Voltage − Continuous
~~ee~~|VGS
~~ee~~
ee|12
~~ee~~|Vdc|
|Thermal Resistance −
Junction−to−Ambient (Note 1)
Total Power Dissipation @ TA= 25°C
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Maximum Operating Power Dissipation
Maximum Operating Drain Current
Pulsed Drain Current (Note 3)
~~ee~~|R JA
PD
ID
ID
PD
ID
IDM
~~ee ~~
ee|50
2.5
−10
−8.0
0.6
−5.5
−50
~~ee~~|°C/W
W
A
A
W
A
A|
|Thermal Resistance −
Junction−to−Ambient (Note 2)
Total Power Dissipation @ TA= 25°C
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Maximum Operating Power Dissipation
Maximum Operating Drain Current
Pulsed Drain Current (Note 3)|R JA
PD
ID
ID
PD
ID
IDM|80
1.6
−8.8
−6.4
0.4
−4.5
−44|°C/W
W
A
A
W
A
A|
|Operating and Storage Temperature Range|TJ, Tstg|−55 to
+150|°C|
|Single Pulse Drain−to−Source Avalanche En-
ergy − Starting TJ= 25°C
(VDD= −20 Vdc, VGS= −4.5 Vdc,
Peak IL= 5.0 Apk, L = 40 mH, RG= 25 )|EAS|500|mJ|
|Maximum Lead Temperature for Soldering
Purposes, 1/8″from case for 10 seconds|TL|260|°C|
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
**==> picture [158 x 169] intentionally omitted <==**
**----- Start of picture text -----**
MARKING DIAGRAM &
PIN ASSIGNMENT
D D D D
8 8
1
E10P02
SOIC−8 AYWW
CASE 751
STYLE 12
1 |
S S S G
E10P02 = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
= Pb−Free Package
**----- End of picture text -----**
(Note: Microdot may be in either location)
## **ORDERING INFORMATION**
|**Device**|**Package**|**Shipping**†|
|---|---|---|
|NTMS10P02R2|SOIC−8|2500/Tape & Reel|
|NTMS10P02R2G|SOIC−8
(Pb−Free)|2500/Tape & Reel|
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
1. Mounted onto a 2 ″ square FR−4 Board
- (1 in sq, Cu 0.06 ″ thick single sided), t = 10 seconds.
2. Mounted onto a 2 ″ square FR−4 Board
- (1 in sq, Cu 0.06 ″ thick single sided), t = steady state.
Publication Order Number:
**1**
© Semiconductor Components Industries, LLC, 2006 **June, 2019 − Rev. 3**
**NTMS10P02R2/D**
**NTMS10P02R2**
3. Pulse Test: Pulse Width < 300 � s, Duty Cycle < 2%.
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**2**
## **NTMS10P02R2**
## **ELECTRICAL CHARACTERISTICS** (TC = 25 ° C unless otherwise noted) (Note 4)
|**ELECTRICAL CHARACTERISTICS**(TC= 25°C unless otherwise noted) (N|**ELECTRICAL CHARACTERISTICS**(TC= 25°C unless otherwise noted) (N|ote 4)|||||
|---|---|---|---|---|---|---|
|**Characteristic**||**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**|||||||
|Drain−to−Source Breakdown Voltage
(VGS= 0 Vdc, ID= −250�Adc)
Temperature Coefficient (Positive)||V(BR)DSS|−20
−|−
−12.1|−
−|Vdc
mV/°C|
|Zero Gate Voltage Drain Current
(VDS= −20 Vdc, VGS= 0 Vdc, TJ= 25°C)
(VDS= −20 Vdc, VGS= 0 Vdc, TJ= 70°C)||IDSS|−
−|−
−|−1.0
−5.0|�Adc|
|Gate−Body Leakage Current
(VGS= −12 Vdc, VDS= 0 Vdc)||IGSS|−|−|−100|nAdc|
|Gate−Body Leakage Current
(VGS= +12 Vdc, VDS= 0 Vdc)||IGSS|−|−|100|nAdc|
|**ON CHARACTERISTICS**|||||||
|Gate Threshold Voltage
(VDS= VGS, ID= −250�Adc)
Temperature Coefficient (Negative)||VGS(th)|−0.6
−|−0.88
2.8|−1.20
−|Vdc
mV/°C|
|Static Drain−to−Source On−State Resistance
(VGS= −4.5 Vdc, ID= −10 Adc)
(VGS= −2.5 Vdc, ID= −8.8 Adc)||RDS(on)|−
−|0.012
0.017|0.014
0.020|�|
|Forward Transconductance (VDS=|−10 Vdc, ID= −10 Adc)|gFS|−|30|−|Mhos|
|**DYNAMIC CHARACTERISTICS**|||||||
|Input Capacitance|(VDS= −16 Vdc, VGS= 0 Vdc,
f = 1.0 MHz)|Ciss|−|3100|3640|pF|
|Output Capacitance||Coss|−|1100|1670||
|Reverse Transfer Capacitance||Crss|−|475|1010||
|**SWITCHING CHARACTERISTICS**(Notes 5 & 6)|||||||
|Turn−On Delay Time|(VDD= −10 Vdc, ID= −1.0 Adc,
VGS= −4.5 Vdc,
RG= 6.0�)|td(on)|−|25|35|ns|
|Rise Time||tr|−|40|65||
|Turn−Off Delay Time||td(off)|−|110|190||
|Fall Time||tf|−|110|190||
|Turn−On Delay Time|(VDD= −10 Vdc, ID= −10 Adc,
VGS= −4.5 Vdc,
RG= 6.0�)|td(on)|−|25|−|ns|
|Rise Time||tr|−|100|−||
|Turn−Off Delay Time||td(off)|−|100|−||
|Fall Time||tf|−|125|−||
|Total Gate Charge|(VDS= −10 Vdc,
VGS= −4.5 Vdc,
ID= −10 Adc)|Qtot|−|48|70|nC|
|Gate−Source Charge||Qgs|−|6.5|−||
|Gate−Drain Charge||Qgd|−|17|−||
|**BODY−DRAIN DIODE RATINGS**(Note 5)|||||||
|Diode Forward On−Voltage|(IS= −2.1 Adc, VGS= 0 Vdc)
(IS= −2.1 Adc, VGS= 0 Vdc, TJ= 125°C)|VSD|−
−|−0.72
−0.60|−1.2
−|Vdc|
|Diode Forward On−Voltage|(IS= −10 Adc, VGS= 0 Vdc)
(IS= −10 Adc, VGS= 0 Vdc, TJ= 125°C)|VSD|−
−|−0.90
−0.75|−
−|Vdc|
|Reverse Recovery Time|(IS= −2.1 Adc, VGS= 0 Vdc,
dIS/dt = 100 A/�s)|trr|−|65|100|ns|
|||ta|−|25|−||
|||tb|−|40|−||
|Reverse Recovery Stored Charge||QRR|−|0.075|−|�C|
4. Handling precautions to protect against electrostatic discharge is mandatory.
5. Indicates Pulse Test: Pulse Width = 300 � s max, Duty Cycle = 2%.
6. Switching characteristics are independent of operating junction temperature.
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**3**
**NTMS10P02R2**
**==> picture [243 x 168] intentionally omitted <==**
**----- Start of picture text -----**
20
−2.3 V −2.1 V
15 TJ = 25 ° C
−10 V
−3.1 V −1.9 V
10
5.0 V GS = −1.7 V
0
0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
-ID, DRAIN CURRENT (AMPS)
**----- End of picture text -----**
**Figure 1. On−Region Characteristics**
**==> picture [236 x 168] intentionally omitted <==**
**----- Start of picture text -----**
10
VDS ≥ −10 V
8.0
6.0
25 ° C
4.0
2.0 100 ° C T J = −55 ° C
0
0 0.5 1.0 1.5 2.0 2.5
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
-ID, DRAIN CURRENT (AMPS)
**----- End of picture text -----**
**Figure 2. Transfer Characteristics**
**==> picture [488 x 390] intentionally omitted <==**
**----- Start of picture text -----**
0.100 0.020
ID = −10 A TJ = 25 ° C VGS = −2.5 V
TJ = 25 ° C
0.075
0.016
0.050
VGS = −4.5 V
0.012
0.025
0 0.008
0 2.0 4.0 6.0 8.0 10 6.0 10 14 18
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) −ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Figure 4. On-Resistance versus Drain Current
Gate−To−Source Voltage and Gate Voltage
1.6 10,000
VGS = 0 V
ID = −10 A
1.4 VGS = −4.5 V
1000 TJ = 125 ° C
1.2
1.0 TJ = 100 ° C
100
0.8
0.6 10
−50 −25 0 25 50 75 100 125 150 2.0 6.0 10 14 18
TJ, JUNCTION TEMPERATURE ( ° C) −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
RDS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS)
-IDSS, LEAKAGE (nA)
RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
**----- End of picture text -----**
**Figure 5. On−Resistance Variation with Temperature**
**Figure 6. Drain−To−Source Leakage Current versus Voltage**
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**4**
**NTMS10P02R2**
**==> picture [244 x 178] intentionally omitted <==**
**----- Start of picture text -----**
10,000
VGS = 0 V VDS = 0 V TJ = 25 ° C
8000 Ciss
6000
Crss
4000
Ciss
2000
Crss Coss
0
10 5.0 0 5.0 10 15 20
−VGS −VDS
C, CAPACITANCE (pF)
**----- End of picture text -----**
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
**Figure 7. Capacitance Variation**
**==> picture [258 x 198] intentionally omitted <==**
**----- Start of picture text -----**
5.0 10
QT
4.0 VGS 8.0
VDS
3.0 6.0
Q1 Q2
2.0 4.0
ID = −10 A
1.0 TJ = 25 ° C 2.0
Q3
0 0
0 10 20 30 40 50
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
**----- End of picture text -----**
**==> picture [488 x 170] intentionally omitted <==**
**----- Start of picture text -----**
1000 1000
VDD = −10 V td(off) VDD = −10 V
ID = −1.0 A tf ID = −10 A td(off)
VGS = −4.5 V VGS = −4.5 V
tr
tr tf
100 100
td(on) td(on)
10 10
1.0 10 100 1.0 10 100
RG, GATE RESISTANCE (OHMS) RG, GATE RESISTANCE (OHMS)
t, TIME (ns) t, TIME (ns)
**----- End of picture text -----**
**Figure 9. Resistive Switching Time Variation versus Gate Resistance**
**Figure 10. Resistive Switching Time Variation versus Gate Resistance**
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**5**
**NTMS10P02R2**
## **DRAIN−TO−SOURCE DIODE CHARACTERISTICS**
**==> picture [489 x 171] intentionally omitted <==**
**----- Start of picture text -----**
100
2.0 V GS = 0 V
TJ = 25 ° C 100 � s
1.6
10 1.0 ms
1.2
VGS = 2.5 V 10 ms
SINGLE PULSE
0.8 1.0 TC = 25 ° C
0.4 RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT dc
0 0.1
0.50 0.55 0.60 0.65 0.70 0.1 1.0 10 100
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
−IS, SOURCE CURRENT (AMPS) −ID, DRAIN CURRENT (AMPS)
**----- End of picture text -----**
**Figure 11. Diode Forward Voltage versus Current**
**Figure 12. Maximum Rated Forward Biased Safe Operating Area**
**==> picture [207 x 100] intentionally omitted <==**
**----- Start of picture text -----**
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS
**----- End of picture text -----**
**Figure 13. Diode Reverse Recovery Waveform**
## **TYPICAL ELECTRICAL CHARACTERISTICS**
**==> picture [484 x 170] intentionally omitted <==**
**----- Start of picture text -----**
10
1.0
D = 0.5
0.2
0.1
0.1
0.05 Normalized to � ja at 10s.
0.02 Chip 0.0163 � 0.0652 � 0.1988 � 0.6411 � 0.9502 �
0.01
0.01
0.0307 F 0.1668 F 0.5541 F 1.9437 F 72.416 F
Ambient
SINGLE PULSE
0.001
1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
THERMAL RESISTANCE
Rthja(t), EFFECTIVE TRANSIENT
**----- End of picture text -----**
**Figure 14. Thermal Response**
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**6**
MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS**
**==> picture [42 x 32] intentionally omitted <==**
**----- Start of picture text -----**
8
1
SCALE 1:1
**----- End of picture text -----**
**SOIC−8 NB** CASE 751−07 ISSUE AK DATE 16 FEB 2011
**==> picture [468 x 427] intentionally omitted <==**
**----- Start of picture text -----**
NOTES:
−X− 1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
py 5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
Th STANDARD IS 751−07.
G MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
C N X 45 B 3.80 4.00 0.150 0.157
| a SEATING “ C 1.35 1.75 0.053 0.069
PLANE D 0.33 0.51 0.013 0.020
−Z− G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
0.10 (0.004) J 0.19 0.25 0.007 0.010
H D M J K 0.40 1.27 0.016 0.050
M 0 8 0 8
N 0.25 0.50 0.010 0.020
0.25 (0.010) M Z Y S X S S 5.80 6.20 0.228 0.244
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8 8 8 8
XXXXX XXXXX XXXXXX XXXXXX
1.52 ALYWX ALYWX AYWW AYWW
0.060
1 1 1 1
IC IC Discrete Discrete
r oogO: bd (Pb−Free) bed be (Pb−Free)
7.0 4.0
XXXXX = Specific Device Code XXXXXX = Specific Device Code
0.275 0.155
A = Assembly Location A = Assembly Location
L = Wafer Lot Y = Year
yt Y = Year WW = Work Week
W = Work Week = Pb−Free Package
= Pb−Free Package
0.6 1.270 *This information is generic. Please refer to
0.024 oon 0.050 device data sheet for actual part marking. |
Pb−Free indicator, “G” or microdot “ ”, may
mm or may not be present. Some products may
SCALE 6:1
inches not follow the Generic Marking.
**----- End of picture text -----**
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
**STYLES ON PAGE 2**
Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ASB42564B** Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **DESCRIPTION: SOIC−8 NB PAGE 1 OF 2** ~~a~~ ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.
www.onsemi.com
© Semiconductor Components Industries, LLC, 2019
**SOIC−8 NB** CASE 751−07 ISSUE AK
## DATE 16 FEB 2011
|STYLE 1:|STYLE 1:|STYLE 2:||STYLE 3:|STYLE 3:||STYLE 4:|STYLE 4:|
|---|---|---|---|---|---|---|---|---|
|PIN 1.|EMITTER|PIN 1.|COLLECTOR, DIE, #1|PIN 1.||DRAIN, DIE #1|PIN 1.|ANODE|
|2.|COLLECTOR|2.|COLLECTOR, #1|2.||DRAIN, #1|2.|ANODE|
|3.|COLLECTOR|3.|COLLECTOR, #2|3.||DRAIN, #2|3.|ANODE|
|4.|EMITTER|4.|COLLECTOR, #2|4.||DRAIN, #2|4.|ANODE|
|5.|EMITTER|5.|BASE, #2|5.||GATE, #2|5.|ANODE|
|6.|BASE|6.|EMITTER, #2|6.||SOURCE, #2|6.|ANODE|
|7.|BASE|7.|BASE, #1|7.||GATE, #1|7.|ANODE|
|8.|EMITTER|8.|EMITTER, #1|8.||SOURCE, #1|8.|COMMON CATHODE|
|STYLE 5:||STYLE 6:||STYLE 7:|||STYLE 8:||
|PIN 1.|DRAIN|PIN 1.|SOURCE|PIN 1.||INPUT|PIN 1.|COLLECTOR, DIE #1|
|2.|DRAIN|2.|DRAIN|2.||EXTERNAL BYPASS|2.|BASE, #1|
|3.|DRAIN|3.|DRAIN|3.||THIRD STAGE SOURCE|3.|BASE, #2|
|4.|DRAIN|4.|SOURCE|4.||GROUND|4.|COLLECTOR, #2|
|5.|GATE|5.|SOURCE|5.||DRAIN|5.|COLLECTOR, #2|
|6.|GATE|6.|GATE|6.||GATE 3|6.|EMITTER, #2|
|7.|SOURCE|7.|GATE|7.||SECOND STAGE Vd|7.|EMITTER, #1|
|8.|SOURCE|8.|SOURCE|8.||FIRST STAGE Vd|8.|COLLECTOR, #1|
|STYLE 9:||STYLE 10:||STYLE 11:|||STYLE 12:||
|PIN 1.|EMITTER, COMMON|PIN 1.|GROUND|PIN 1.||SOURCE 1|PIN 1.|SOURCE|
|2.|COLLECTOR, DIE #1|2.|BIAS 1|2.||GATE 1|2.|SOURCE|
|3.|COLLECTOR, DIE #2|3.|OUTPUT|3.||SOURCE 2|3.|SOURCE|
|4.|EMITTER, COMMON|4.|GROUND|4.||GATE 2|4.|GATE|
|5.|EMITTER, COMMON|5.|GROUND|5.||DRAIN 2|5.|DRAIN|
|6.|BASE, DIE #2|6.|BIAS 2|6.||DRAIN 2|6.|DRAIN|
|7.|BASE, DIE #1|7.|INPUT|7.||DRAIN 1|7.|DRAIN|
|8.|EMITTER, COMMON|8.|GROUND|8.||DRAIN 1|8.|DRAIN|
|STYLE 13:||STYLE 14:||STYLE 15:|||STYLE 16:||
|PIN 1.|N.C.|PIN 1.|N−SOURCE|PIN 1.|ANODE 1||PIN 1.|EMITTER, DIE #1|
|2.|SOURCE|2.|N−GATE|2.|ANODE 1||2.|BASE, DIE #1|
|3.|SOURCE|3.|P−SOURCE|3.|ANODE 1||3.|EMITTER, DIE #2|
|4.|GATE|4.|P−GATE|4.|ANODE 1||4.|BASE, DIE #2|
|5.|DRAIN|5.|P−DRAIN|5.|CATHODE, COMMON||5.|COLLECTOR, DIE #2|
|6.|DRAIN|6.|P−DRAIN|6.|CATHODE, COMMON||6.|COLLECTOR, DIE #2|
|7.|DRAIN|7.|N−DRAIN|7.|CATHODE, COMMON||7.|COLLECTOR, DIE #1|
|8.|DRAIN|8.|N−DRAIN|8.|CATHODE, COMMON||8.|COLLECTOR, DIE #1|
|STYLE 17:||STYLE 18:||STYLE 19:|||STYLE 20:||
|PIN 1.|VCC|PIN 1.|ANODE|PIN 1.||SOURCE 1|PIN 1.|SOURCE (N)|
|2.|V2OUT|2.|ANODE|2.||GATE 1|2.|GATE (N)|
|3.|V1OUT|3.|SOURCE|3.||SOURCE 2|3.|SOURCE (P)|
|4.|TXE|4.|GATE|4.||GATE 2|4.|GATE (P)|
|5.|RXE|5.|DRAIN|5.||DRAIN 2|5.|DRAIN|
|6.|VEE|6.|DRAIN|6.||MIRROR 2|6.|DRAIN|
|7.|GND|7.|CATHODE|7.||DRAIN 1|7.|DRAIN|
|8.|ACC|8.|CATHODE|8.||MIRROR 1|8.|DRAIN|
|STYLE 21:||STYLE 22:||STYLE 23:|||STYLE 24:||
|PIN 1.|CATHODE 1|PIN 1.|I/O LINE 1|PIN 1.||LINE 1 IN|PIN 1.|BASE|
|2.|CATHODE 2|2.|COMMON CATHODE/VCC|2.||COMMON ANODE/GND|2.|EMITTER|
|3.|CATHODE 3|3.|COMMON CATHODE/VCC|3.||COMMON ANODE/GND|3.|COLLECTOR/ANODE|
|4.|CATHODE 4|4.|I/O LINE 3|4.||LINE 2 IN|4.|COLLECTOR/ANODE|
|5.|CATHODE 5|5.|COMMON ANODE/GND|5.||LINE 2 OUT|5.|CATHODE|
|6.|COMMON ANODE|6.|I/O LINE 4|6.||COMMON ANODE/GND|6.|CATHODE|
|7.|COMMON ANODE|7.|I/O LINE 5|7.||COMMON ANODE/GND|7.|COLLECTOR/ANODE|
|8.|CATHODE 6|8.|COMMON ANODE/GND|8.||LINE 1 OUT|8.|COLLECTOR/ANODE|
|STYLE 25:||STYLE 26:||STYLE 27:|STYLE 27:||STYLE 28:||
|PIN 1.|VIN|PIN 1.|GND|PIN 1.||ILIMIT|PIN 1.|SW_TO_GND|
|2.|N/C|2.|dv/dt|2.||OVLO|2.|DASIC_OFF|
|3.|REXT|3.|ENABLE|3.||UVLO|3.|DASIC_SW_DET|
|4.|GND|4.|ILIMIT|4.||INPUT+|4.|GND|
|5.|IOUT|5.|SOURCE|5.||SOURCE|5.|V_MON|
|6.|IOUT|6.|SOURCE|6.||SOURCE|6.|VBULK|
|7.|IOUT|7.|SOURCE|7.||SOURCE|7.|VBULK|
|8.|IOUT|8.|VCC|8.||DRAIN|8.|VIN|
|STYLE 29:||STYLE 30:|||||||
|PIN 1.|BASE, DIE #1|PIN 1.|DRAIN 1||||||
|2.|EMITTER, #1|2.|DRAIN 1||||||
|3.|BASE, #2|3.|GATE 2||||||
|4.|EMITTER, #2|4.|SOURCE 2||||||
|5.|COLLECTOR, #2|5.|SOURCE 1/DRAIN 2||||||
|6.|COLLECTOR, #2|6.|SOURCE 1/DRAIN 2||||||
|7.|COLLECTOR, #1|7.|SOURCE 1/DRAIN 2||||||
|8.|COLLECTOR, #1|8.|GATE 1||||||
Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ASB42564B** Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. **DESCRIPTION: SOIC−8 NB PAGE 2 OF 2**
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**==> picture [232 x 43] intentionally omitted <==**
## Links
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---
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