# Power MOSFET, N Channel, 30 V, 115 A, 0.0022 ohm, DFN, Surface Mount

![Product image](https://novapart.co/image/farnell:2774825/)

**URL**: https://novapart.co/products/NTMFS4845NT1G/power-mosfet-n-channel-30-v-115-a-00022-ohm-dfn
**SKU**: NTMFS4845NT1G
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.5320
**Stock**: 10+

## Specifications

| Parameter | Value |
|---|---|
| No. Of Pins | 5Pins |
| Channel Type | N Channel |
| Power Dissipation | 62.5W |
| Transistor Mounting | Surface Mount |
| Transistor Polarity | N Channel |
| Power Dissipation Pd | 62.5W |
| Rds(On) Test Voltage | 11.5V |
| On Resistance Rds(On) | 0.0022ohm |
| Transistor Case Style | DFN |
| Drain Source Voltage Vds | 30V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 115A |
| Drain Source On State Resistance | 0.0022ohm |
| Gate Source Threshold Voltage Max | 1.8V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2774825/)

## NTMFS4845N 

## Power MOSFET 

## **30 V, 115 A, Single N−Channel, SO−8FL** 

## **Features** 

- Low R to Minimize Conduction Losses DS(on) 

- Low Capacitance to Minimize Driver Losses 

- Optimized Gate Charge to Minimize Switching Losses 

**http://onsemi.com** 

- Thermally Enhanced SO−8 Package 

- These are Pb−Free Devices 

**V(BR)DSS RDS(ON) MAX ID MAX Applications** • Refer to Application Note AND8195/D 30 V 2.9 m @ 10 V 115 A • CPU Power Delivery ~~ESa ee~~ 4.4 m @ 4.5 V ee • DC−DC Converters • Low Side Switching D (5,6) **MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise stated) ~~ee~~ **Parameter Symbol** ~~es~~ **Value** ~~ee~~ **Unit** ~~es~~ Drain−to−Source Voltage ~~ee~~ VDSS 30 ~~es~~ V Gate−to−Source Voltage VGS ± 16 V G (4) Continuous Drain TA = 25 ° C ID 22 A ~~ef~~ Current R(Note 1) JA ~~eG~~ TA = 85 ° C 15.8 S (1,2,3) Power Dissipation TA = 25 ° C PD 2.27 W **N−CHANNEL MOSFET** R JA (Note 1) Continuous Drain TA = 25 ° C ID 35.5 A **MARKING** Current R10 sec JA TA = 85 ° C 25.6 **DIAGRAM** ~~J~~ Power Dissipation TA = 25 ° C PD 5.95 W D RContinuous DrainCurrent R(Note 2)JA, t 10 secJA SteadyState ~~ee~~ TTAA = 25 = 85 °° CC ID 13.79.9 A **SO−8 FLAT LEAD** 2 **CASE 488AA** 1 GSSS AYWZZ4845N DD Power Dissipation TA = 25 ° C PD 0.89 W **STYLE 1** D R JA (Note 2) ~~eees~~ Continuous DrainCurrent R(Note 1)Power DissipationJC ~~| ES~~ TTTCCC = 25 = 85 = 25 °°° CCC PIDD 62.511583 WA AYWZZ = Lot Traceability= Year= Assembly Location= Work Week ~~|~~ R JC (Note 1) Pulsed Drain tp=10 s TA = 25 ° C IDM 230 A Current ~~a~~ **ORDERING INFORMATION** ~~ee~~ Current limited by packageOperating Junction and Storage TA = 25 ~~es~~ ° C IDmaxTJ,pkg −55 to100 ° AC **Device Package Shipping**[†] Temperature TSTG +150 NTMFS4845NT1G SO−8FL 1500 / Source Current (Body Diode) IS 62 A (Pb−Free) Tape & Reel ~~a~~ Drain to Source dV/dt dV/dt 6 V/ns NTMFS4845NT3G SO−8FL 5000 / Single Pulse Drain−to−Source Avalanche EAS 228 mJ (Pb−Free) Tape & Reel ~~ee T+ ee~~ Energy (VLead Temperature for Soldering PurposesIL = 39 ApkDD, L = 0.3 mH, R = 50 V, VGS = 10 V,G = 25 TL 260 ~~ee~~ ° C †For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging Specifications ~~ee~~ (1/8” from case for 10 s) Brochure, BRD8011/D. 

## **Applications** 

- Refer to Application Note AND8195/D 

- CPU Power Delivery 

- DC−DC Converters 

- Low Side Switching 

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 

Publication Order Number: 

**1** 

© Semiconductor Components Industries, LLC, 2012 **May, 2012 − Rev. 3** 

**NTMFS4845N/D** 

**NTMFS4845N** 

## **THERMAL RESISTANCE MAXIMUM RATINGS** 

|**THERMAL RESISTANCE MAXIMUM RATINGS**||||
|---|---|---|---|
|**Parameter**|**Symbol**|**Value**|**Unit**|
|Junction−to−Case (Drain)|R�JC|2.0|°C/W|
|Junction−to−Ambient – Steady State (Note 1)|R�JA|55.1||
|Junction−to−Ambient – Steady State (Note 2)|R�JA|140.1||
|Junction−to−Ambient − t�10 sec|R�JA|21||



1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu. 

2. Surface−mounted on FR4 board using the minimum recommended pad size. 

**ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise specified) 

|**Parameter**|**Symbol**|**Test Condition**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID=|250�A|30|||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(BR)DSS/<br>TJ||||25||mV/°C|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,<br>VDS= 24 V|TJ= 25°C|||1|�A|
||||TJ= 125°C|||10||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS|=±16 V|||±100|nA|
|**ON CHARACTERISTICS**(Note 3)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID=|250�A|1.45|1.8|2.5|V|
|Negative Threshold Temperature Coefficient|VGS(TH)/TJ||||5.2||mV/°C|
|Drain−to−Source On Resistance|RDS(on)|VGS= 10 V to<br>11.5 V|ID= 30 A||2.2|2.9|m�|
||||ID= 15 A||2.2|||
|||VGS= 4.5 V|ID= 30 A||3.4|4.4||
||||ID= 15 A||3.4|||
|Forward Transconductance|gFS|VDS= 1.5 V, ID= 30 A|||87||S|
|**CHARGES AND CAPACITANCES**||||||||
|Input Capacitance|CISS|VGS= 0 V, f = 1 MHz, VDS= 12 V|||3720||pF|
|Output Capacitance|COSS||||650|||
|Reverse Transfer Capacitance|CRSS||||335|||
|Total Gate Charge|QG(TOT)|VGS= 4.5 V, VDS= 15 V; ID= 30 A|||25.6|39|nC|
|Threshold Gate Charge|QG(TH)||||3.2|||
|Gate−to−Source Charge|QGS||||9.4|||
|Gate−to−Drain Charge|QGD||||8.6|||
|Total Gate Charge|QG(TOT)|VGS= 11.5 V, VDS= 15 V,<br>ID= 30 A|||62||nC|
|**SWITCHING CHARACTERISTICS**(Note 4)||||||||
|Turn−On Delay Time|td(ON)|VGS= 4.5 V, VDS= 15 V, ID= 15 A,<br>RG= 3.0�|||20.5||ns|
|Rise Time|tr||||48.4|||
|Turn−Off Delay Time|td(OFF)||||28.9|||
|Fall Time|tf||||12.2|||



3. Pulse Test: pulse width � 300 � s, duty cycle � 2%. 

4. Switching characteristics are independent of operating junction temperatures. 

**http://onsemi.com** 

**2** 

**NTMFS4845N** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise specified) 

|**ELECTRICAL CHARACTERISTICS**(TJ=|25°C unless|otherwise specified)|otherwise specified)|||||
|---|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**SWITCHING CHARACTERISTICS**(Note 4)||||||||
|Turn−On Delay Time|td(ON)|VGS= 11.5 V, VDS= 15 V,<br>ID= 15 A, RG= 3.0�|||12.5||ns|
|Rise Time|tr||||27.1|||
|Turn−Off Delay Time|td(OFF)||||37.7|||
|Fall Time|tf||||9.7|||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= 30 A|TJ= 25°C||0.8|1.0|V|
||||TJ= 125°C||0.7|||
|Reverse Recovery Time|tRR|VGS= 0 V, dIS/dt = 100 A/�s,<br>IS= 30 A|||20.8||ns|
|Charge Time|ta||||12.6|||
|Discharge Time|tb||||8.2|||
|Reverse Recovery Charge|QRR||||9.0||nC|
|**PACKAGE PARASITIC VALUES**||||||||
|Source Inductance|LS|TA= 25°C|||0.65||nH|
|Drain Inductance|LD||||0.005|||
|Gate Inductance|LG||||1.84|||
|Gate Resistance|RG||||1.3|2.5|�|



3. Pulse Test: pulse width � 300 � s, duty cycle � 2%. 

4. Switching characteristics are independent of operating junction temperatures. 

## **TYPICAL CHARACTERISTICS** 

**==> picture [487 x 174] intentionally omitted <==**

**----- Start of picture text -----**<br>
200 150<br>180 10 V VGS = 4.2 V TJ = 25 ° C 4.0 V 140<br>130 VDS ≥  10 V<br>160 5.0 V 3.8 V 120<br>110<br>140 100<br>4.5 V 3.6 V<br>120 90<br>80<br>100 3.4 V<br>70<br>80 60<br>3.2 V 50<br>60 40 TJ = 125 ° C<br>3.0 V<br>40 2.8 V 3020 TJ = 25 ° C<br>20<br>0 2.6 V 100 T J  = −55 ° C<br>0 1 2 3 4 5 6 1 2 3 4<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)<br>, DRAIN CURRENT (A) , DRAIN CURRENT (A)<br>ID ID<br>**----- End of picture text -----**<br>


**Figure 1. On−Region Characteristics** 

**==> picture [143 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 2. Transfer Characteristics<br>**----- End of picture text -----**<br>


**http://onsemi.com** 

**3** 

**NTMFS4845N** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [491 x 630] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.016 0.006<br>0.014 ID = 30 ATJ = 25 ° C 0.005 TJ = 25 ° C<br>0.012<br>0.010 0.004 VGS = 4.5 V<br>0.008<br>0.006 0.003 V GS  = 11.5 V<br>0.004<br>0.002<br>0.002<br>0 0.001<br>2 3 4 5 6 7 8 9 10 11 10 15 20 25 30 35 40 45 50 55 60<br>VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and<br>Voltage Gate Voltage<br>1.7 10,000<br>1.6 ID = 30 A VGS = 0 V<br>1.5 VGS = 10 V<br>1.4 TJ = 150 ° C<br>1.3<br>1.2<br>1000<br>1.1<br>1.0<br>0.9<br>0.8 TJ = 125 ° C<br>0.7<br>0.6 100<br>−50 −25 0 25 50 75 100 125 150 2 4 6 8 10 12 14 16 18 20<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current<br>Temperature vs. Voltage<br>4500 12 16<br>4000 Ciss TJ = 25 ° C QT 14<br>10<br>3500 VDS VGS 12<br>3000 8<br>10<br>2500<br>6 8<br>2000<br>1500 4 Qgs Qgd 6<br>Coss 4<br>1000<br>500 Crss 2 TIDJ = 30 A = 25 ° C 2<br>0 0 0<br>0 4 8 12 16 20 24 28 32 0 5 10 15 20 25 30 35 40 45 50 55 60 65<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)<br>Figure 7. Capacitance Variation Figure 8. Gate−to−Source and<br>Drain−to−Source Voltage vs. Total Charge<br>) � ) �<br>, DRAIN−TO−SOURCE RESISTANCE ( , DRAIN−TO−SOURCE RESISTANCE (<br>DS(on) DS(on)<br>R R<br>, LEAKAGE (nA)<br>, DRAIN−TO−SOURCE<br>IDSS<br>DS(on)<br>R RESISTANCE (NORMALIZED)<br>V<br>DS<br>C, CAPACITANCE (pF)<br>, GATE−TO−SOURCE VOLTAGE (V)<br>GS<br>V , DRAIN−TO−SOURCE VOLTAGE (V)<br>**----- End of picture text -----**<br>


**http://onsemi.com** 

**4** 

**NTMFS4845N** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [243 x 156] intentionally omitted <==**

**----- Start of picture text -----**<br>
1000<br>VDS = 15 V<br>ID = 15 A<br>VGS = 11.5 V tf<br>100<br>td(off)<br>tr td(on)<br>10<br>1<br>1 10 100<br>t, TIME (ns)<br>**----- End of picture text -----**<br>


**==> picture [104 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
RG, GATE RESISTANCE ( � )<br>**----- End of picture text -----**<br>


**Figure 9. Resistive Switching Time Variation vs. Gate Resistance** 

**==> picture [239 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
30<br>VGS = 0 V<br>25 TJ = 25 ° C<br>20<br>15<br>10<br>5<br>0<br>0.4 0.5 0.6 0.7 0.8 0.9<br>VSD, SOURCE−TO−DRAIN VOLTAGE (V)<br>, SOURCE CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 10. Diode Forward Voltage vs. Current** 

**==> picture [491 x 384] intentionally omitted <==**

**----- Start of picture text -----**<br>
1000 240<br>220 ID = 39 A<br>200<br>10  � s<br>100 180<br>160<br>100  � s 140<br>10 1 ms 120<br>VGS = 20 V 100<br>10 ms<br>Single Pulse 80<br>1 TC = 25 ° C dc 60<br>RDS(on) Limit 40<br>Thermal Limit<br>20<br>Package Limit<br>0.1 0<br>0.1 1 10 100 25 50 75 100 125 150<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) TJ, STARTING JUNCTION TEMPERATURE( ° C)<br>Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy vs.<br>Safe Operating Area Starting Junction Temperature<br>160 1000<br>140<br>120<br>100<br>100<br>80<br>60 125 ° C 100 ° C 25 ° C<br>10<br>40<br>20<br>VDS = 1.5 V<br>0 1<br>0 15 30 45 60 75 90 105 120 1 10 100 1000 10,000<br>DRAIN CURRENT (A) PULSE WIDTH ( � s)<br>, DRAIN CURRENT (A)<br>ID , SINGLE PULSE DRAIN−TO−<br>AS<br>E<br>SOURCE AVALANCHE ENERGY (mJ)<br> (S)<br> (A)<br>gFS Id<br>**----- End of picture text -----**<br>


**Figure 13. gFS vs. Drain Current** 

**Figure 14. Id vs. Pulse Width** 

**http://onsemi.com** 

**5** 

**NTMFS4845N** 

## **PACKAGE DIMENSIONS** 

**==> picture [475 x 582] intentionally omitted <==**

**----- Start of picture text -----**<br>
DFN5 5x6, 1.27P<br>(SO−8FL)<br>CASE 488AA<br>ISSUE G<br>2 X NOTES:<br>1. DIMENSIONING AND TOLERANCING PER<br>0.20 C ASME Y14.5M, 1994.<br>2. CONTROLLING DIMENSION: MILLIMETER.<br>a D A 3. DIMENSION D1 AND E1 DO NOT INCLUDE<br>MOLD FLASH PROTRUSIONS OR GATE<br>2 B 2 X BURRS.<br>D1 MILLIMETERS<br>0.20 C<br>4 DIM MIN NOM MAX<br>A 0.90 1.00 1.10<br>A1 0.00 −−− 0.05<br>E1 4 X b 0.33 0.41 0.51<br>c 0.23 0.28 0.33<br>E D 5.15 BSC<br>2 D1 4.50 4.90 5.10<br>c D2 3.50 −−− 4.22<br>a A1 E 6.15 BSC<br>HH f ec t —= E1 5.50 5.80 6.10<br>P 1 2 3 T 4 ify EEE E2 3.45 −−− 4.30<br>e 1.27 BSC<br>TOP VIEW G 0.51 0.61 0.71<br>3 X C K 1.20 1.35 1.50<br>0.10 C S e h SEATINGPLANE = L1L 0.510.05 0.610.17 0.710.20<br>M 3.00 3.40 3.80<br>A DETAIL A 0  −−− 12<br>a ae<br>0.10 C STYLE 1:<br>PIN 1. SOURCE<br>SF SIDE VIEW DETAIL A SOLDERING FOOTPRINT*  2. 3. SOURCESOURCE<br> 4. GATE<br>3X 4X  5. DRAIN<br>8X b 1.270 0.750<br>4X<br>0.10 C A B 1.000<br>0.05 c L e/2<br>1 fe 4 0.965 b oo ts<br>K<br>1.330 2X<br>ft an a 0.905<br>E2 2X<br>PIN 5 M 0.495 4.530<br>(EXPOSED PAD) L1<br>3.200<br>0.475<br>G ac D2 and<br>2X<br>BOTTOM VIEW 1.530<br>rah Lo 4.560  eS<br>*For additional information on our Pb−Free strategy and soldering<br>details, please download the ON Semiconductor Soldering and<br>Mounting Techniques Reference Manual, SOLDERRM/D.<br>ON Semiconductor  and          are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).  SCILLC reserves the right to make changes without further notice<br>to any products herein.  SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability<br>arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.<br>“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.  All<br>operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.  SCILLC does not convey any license under its patent rights<br>nor the rights of others.  SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications<br>intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.  Should<br>Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,<br>and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death<br>associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.  SCILLC is an Equal<br>Opportunity/Affirmative Action Employer.  This literature is subject to all applicable copyright laws and is not for resale in any manner.<br>**----- End of picture text -----**<br>


## **PUBLICATION ORDERING INFORMATION** 

## **LITERATURE FULFILLMENT** : 

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**NTMFS4845N/D** 

**6** 



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