# Power MOSFET, N Channel, 30 V, 57 A, 0.0047 ohm, SO-8 FL, Surface Mount ![Product image](https://novapart.co/image/farnell:2317601/) **URL**: https://novapart.co/products/NTMFS4841NT1G/power-mosfet-n-channel-30-v-57-a-00047-ohm-so-8-fl **SKU**: NTMFS4841NT1G **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.4590 **Stock**: 10+ ## Specifications | Parameter | Value | |---|---| | No. Of Pins | 8Pins | | Channel Type | N Channel | | Power Dissipation | 41.7W | | Transistor Mounting | Surface Mount | | Transistor Polarity | N Channel | | Power Dissipation Pd | 41.7W | | Rds(On) Test Voltage | 11.5V | | On Resistance Rds(On) | 0.0047ohm | | Transistor Case Style | SO-8 FL | | Drain Source Voltage Vds | 30V | | Operating Temperature Max | 150°C | | Continuous Drain Current Id | 57A | | Drain Source On State Resistance | 0.0047ohm | | Gate Source Threshold Voltage Max | 2.5V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2317601/) NTMFS4841N ## Power MOSFET ## **30 V, 57 A, Single N−Channel, SO−8FL** ## **Features** - Low R to Minimize Conduction Losses DS(on) - Low Capacitance to Minimize Driver Losses - Optimized Gate Charge to Minimize Switching Losses ## **http://onsemi.com** - These are Pb−Free Devices **==> picture [492 x 510] intentionally omitted <==** **----- Start of picture text -----**
V(BR)DSS RDS(ON) MAX ID MAX
Applications
• Refer to Application Note AND8195/D 30 V 7.0 m @ 10 V 57 A
• CPU Power Delivery a eee 11.4 m @ 4.5 V
• DC−DC Converters
MAXIMUM RATINGS (TJ = 25 ° C unless otherwise stated)
D (5,6)
es Parameter Symbol Value Unit
Drain−to−Source Voltage VDSS 30 V
Gate−to−Source Voltage VGS ± 20 V
Continuous Drain TA = 25 ° C ID 13.1 A G (4)
Current R JA
(Note 1) Steady TA = 85 ° C 9.5
State
eo] —— Power Dissipation SR. TA = 25 ° C PD 2.17 W a) S (1,2,3)
R JA (Note 1) TA = 85 ° C 1.13 N−CHANNEL MOSFET
Continuous Drain TA = 25 ° C ID 19.9 A
co Current Rt = 10 sec JA − eee TA = 85 ° C 14.4 MARKING
DIAGRAM
Power Dissipation TA = 25 ° C PD 5 W D
a RContinuous DrainJA, t 10 sec SteadyState eee TTAA = 25 = 85 °° CC ID ee 2.68.3 A ~ 1 SS 4841N D
rc Current R(Note 2) JA ———ae TA = 85 ° C 6 SO−8 FLAT LEADCASE 488AA GS ee AYWZZ D
Power Dissipation | Ef TA = 25 ° C PD 0.87 W STYLE 1 D
R JA (Note 2) TA = 85 ° C 0.45
Continuous Drain TC = 25 ° C ID 57 A A = Assembly Location
a Current R(Note 1) JC TC = 85 ° C 41 YW = Year= Work Week
a Power Dissipation ee TC = 25 ° C ee PD 41.7 W ZZ = Lot Traceability
{| R JC (Note 1) TC = 85 ° C 21.7
Pulsed Drain tp=10 s TA = 25 ° C IDM 171 A
PE Current ORDERING INFORMATION
Operating Junction and Storage TJ, −55 to ° C
Temperature TSTG +150 Device Package Shipping [†]
Pe
Source Current (Body Diode) IS 35 A NTMFS4841NT1G SO−8FL 1500 /
Drain to Source dV/dt dV/dt 6 V/ns (Pb−Free) Tape & Reel
Single Pulse Drain−to−Source Avalanche EAS 180 mJ NTMFS4841NT3G SO−8FL 5000 /
Energy (VDD = 24 V, VGS = 10 V, (Pb−Free) Tape & Reel
—— IL = 19 Apk, L = 1.0 mH, RG = 25 T+
Pw Lead Temperature for Soldering Purposes | TL 260 ° C †For information on tape and reel specifications,
including part orientation and tape sizes, please
(1/8” from case for 10 s)
eeee eee refer to our Tape and Reel Packaging Specifications
Stresses exceeding Maximum Ratings may damage the device. Maximum Brochure, BRD8011/D.
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
**----- End of picture text -----**
Publication Order Number: **1** © Semiconductor Components Industries, LLC, 2012 **May, 2012 − Rev. 8** **NTMFS4841N/D** **NTMFS4841N** ## **THERMAL RESISTANCE MAXIMUM RATINGS** |**THERMAL RESISTANCE MAXIMUM RATINGS**|||| |---|---|---|---| |**Parameter**|**Symbol**|**Value**|**Unit**| |Junction−to−Case (Drain)|R�JC|3|°C/W| |Junction−to−Ambient – Steady State (Note 1)|R�JA|57.7|| |Junction−to−Ambient – Steady State (Note 2)|R�JA|143.4|| |Junction−to−Ambient − t = 10 sec|R�JA|25|| 1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise specified) |**Parameter**|**Symbol**|**Test Condition**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---|---| |**OFF CHARACTERISTICS**|||||||| |Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID=|250�A|30|||V| |Drain−to−Source Breakdown Voltage
Temperature Coefficient|V(BR)DSS/
TJ||||25||mV/°C| |Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,
VDS= 24 V|TJ= 25°C|||1|�A| ||||TJ= 125°C|||10|| |Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS|=±20 V|||±100|nA| |**ON CHARACTERISTICS**(Note 3)|||||||| |Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID=|250�A|1.5||2.5|V| |Negative Threshold Temperature Coefficient|VGS(TH)/TJ||||5.6||mV/°C| |Drain−to−Source On Resistance|RDS(on)|VGS= 10 V to
11.5 V|ID= 30 A||4.7|7.0|m�| ||||ID= 15 A||4.6||| |||VGS= 4.5 V|ID= 30 A||9.2|11.4|| ||||ID= 15 A||8.5||| |Forward Transconductance|gFS|VDS= 15 V, ID= 15 A|||16||S| |**CHARGES AND CAPACITANCES**|||||||| |Input Capacitance|CISS|VGS= 0 V, f = 1 MHz, VDS= 12 V|||1436||pF| |Output Capacitance|COSS||||348||| |Reverse Transfer Capacitance|CRSS||||177||| |Total Gate Charge|QG(TOT)|VGS= 4.5 V, VDS= 15 V; ID= 30 A|||11.5|17|nC| |Threshold Gate Charge|QG(TH)||||2.0||| |Gate−to−Source Charge|QGS||||5.0||| |Gate−to−Drain Charge|QGD||||5.1||| |Total Gate Charge|QG(TOT)|VGS= 11.5 V, VDS= 15 V,
ID= 30 A|||25.4||nC| |**SWITCHING CHARACTERISTICS**(Note 4)|||||||| |Turn−On Delay Time|td(ON)|VGS= 4.5 V, VDS= 15 V, ID= 15 A,
RG= 3.0�|||13.5||ns| |Rise Time|tr||||66.5||| |Turn−Off Delay Time|td(OFF)||||15.5||| |Fall Time|tf||||7.5||| 3. Pulse Test: pulse width � 300 � s, duty cycle � 2%. 4. Switching characteristics are independent of operating junction temperatures. **http://onsemi.com** **2** ## **NTMFS4841N** ## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise specified) |**ELECTRICAL CHARACTERISTICS**(TJ=|25°C unless|otherwise specified)|otherwise specified)||||| |---|---|---|---|---|---|---|---| |**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**| |**SWITCHING CHARACTERISTICS**(Note 4)|||||||| |Turn−On Delay Time|td(ON)|VGS= 11.5 V, VDS= 15 V,
ID= 15 A, RG= 3.0�|||8.1||ns| |Rise Time|tr||||24.2||| |Turn−Off Delay Time|td(OFF)||||22.8||| |Fall Time|tf||||5.7||| |**DRAIN−SOURCE DIODE CHARACTERISTICS**|||||||| |Forward Diode Voltage|VSD|VGS= 0 V,
IS= 30 A|TJ= 25°C||0.9|1.2|V| ||||TJ= 125°C||0.8||| |Reverse Recovery Time|tRR|VGS= 0 V, dIS/dt = 100 A/�s,
IS= 30 A|||20.5||ns| |Charge Time|ta||||11.6||| |Discharge Time|tb||||8.9||| |Reverse Recovery Charge|QRR||||10.7||nC| |**PACKAGE PARASITIC VALUES**|||||||| |Source Inductance|LS|TA= 25°C|||0.93||nH| |Drain Inductance|LD||||0.005||| |Gate Inductance|LG||||1.84||| |Gate Resistance|RG||||3.2||�| 3. Pulse Test: pulse width � 300 � s, duty cycle � 2%. 4. Switching characteristics are independent of operating junction temperatures. **http://onsemi.com** **3** **NTMFS4841N** ## **TYPICAL PERFORMANCE CURVES** **==> picture [237 x 174] intentionally omitted <==** **----- Start of picture text -----**
140
130 TJ = 25 ° C
5.5 V to 10 V
120
110 VGS = 5 V
100
90
80 4.5 V
70
60
50 4 V
40 3.8 V
30
3.6 V
20
3.4 V
10
0
0 1 2 3 4 5
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
, DRAIN CURRENT (AMPS)
ID
**----- End of picture text -----**
**Figure 1. On−Region Characteristics** **==> picture [234 x 174] intentionally omitted <==** **----- Start of picture text -----**
140
130 VDS = 10 V
120
110
100
90
80
70
60
50
40 T J = 125 ° C
30
20 TJ = 25 ° C
10 T J = −55 ° C
0
1 2 3 4 5 6 7 8
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
, DRAIN CURRENT (AMPS)
ID
**----- End of picture text -----**
**Figure 2. Transfer Characteristics** **==> picture [487 x 435] intentionally omitted <==** **----- Start of picture text -----**
0.017
0.018 ID = 30 A TJ = 25 ° C
0.017 TJ = 25 ° C
0.016 0.014
0.015
VGS = 4.5 V
0.014
0.013 0.011
0.012
0.011
0.008
0.010
0.009 VGS = 11.5 V
0.008
0.005
0.007
0.006
0.005 0.002
3 4 5 6 7 8 9 10 11 10 15 20 25 30 35 40 45 50 55 60
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and
Voltage Gate Voltage
1.8 10000
1.7 ID = 30 A VGS = 0 V
1.6 VGS = 10 V 1000 TJ = 150 ° C
1.5
1.4 TJ = 125 ° C
100
1.3
1.2
1.1 10
1.0
0.9 1 TJ = 25 ° C
0.8
0.7
0.6 0.1
−55 −35 −15 5 25 45 65 85 105 125 145 5 10 15 20 25 30
TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current
Temperature vs. Voltage
) � ) �
, DRAIN−TO−SOURCE RESISTANCE ( , DRAIN−TO−SOURCE RESISTANCE (
DS(on) DS(on)
R R
, LEAKAGE (nA)
(NORMALIZED) IDSS
, DRAIN−TO−SOURCE RESISTANCE
DS(on)
R
**----- End of picture text -----**
**http://onsemi.com** **4** **NTMFS4841N** ## **TYPICAL PERFORMANCE CURVES** **==> picture [240 x 170] intentionally omitted <==** **----- Start of picture text -----**
2200
2000 TJ = 25 ° C
Ciss
1800
1600
Ciss
1400
1200
1000
800 C rss
600
400 Coss
200
0 Crss
10 5 0 5 10 15 20 25 30
VGS VDS
C, CAPACITANCE (pF)
**----- End of picture text -----**
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) **Figure 7. Capacitance Variation** **==> picture [236 x 171] intentionally omitted <==** **----- Start of picture text -----**
12
11 Q T
10
9
8
7
6
5
4 QGS QGD
3 VDD = 15 V
2 V GS = 11.5 V
1 TIDJ = 30 A = 25 ° C
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26
QG, TOTAL GATE CHARGE (nC)
, GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
V
**----- End of picture text -----**
**Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge** **==> picture [241 x 386] intentionally omitted <==** **----- Start of picture text -----**
1000
VDD = 15 V
ID = 15 A
VGS = 11.5 V
100
tr
td(off)
10 td(on)
tf
1
1 10 100
RG, GATE RESISTANCE ( � )
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
1000
100 10 � s
VGS = 20 V 100 � s
SINGLE PULSE 1 ms
10 TC = 25 ° C
RDS(on) LIMIT 10 ms
THERMAL LIMIT
PACKAGE LIMIT dc
1
0.1 1 10 100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
t, TIME (ns)
ID, DRAIN CURRENT (AMPS)
**----- End of picture text -----**
**Figure 11. Maximum Rated Forward Biased Safe Operating Area** **==> picture [235 x 171] intentionally omitted <==** **----- Start of picture text -----**
30
VGS = 0 V
25 TJ = 25 ° C
20
15
10
5
0
0.5 0.6 0.7 0.8 0.9 1.0
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
IS, SOURCE CURRENT (AMPS)
**----- End of picture text -----**
**Figure 10. Diode Forward Voltage vs. Current** **==> picture [242 x 170] intentionally omitted <==** **----- Start of picture text -----**
180
ID = 19 A
160
140
120
100
80
60
40
20
0
25 50 75 100 125 150
TJ, STARTING JUNCTION TEMPERATURE ( ° C)
AVALANCHE ENERGY (mJ)
, SINGLE PULSE DRAIN−TO−SOURCE
AS
E
**----- End of picture text -----**
**Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature** **http://onsemi.com** **5** **NTMFS4841N** ## **TYPICAL PERFORMANCE CURVES** **==> picture [491 x 389] intentionally omitted <==** **----- Start of picture text -----**
100
25 ° C
100 ° C
125 ° C
10
1
1 10 100 1000
PULSE WIDTH ( � s)
Figure 13. EAS vs. Pulse Width
1.0
0.1
Normalized to R � JA at Steady State (1 inch)
0.01
0.0086 � 0.026 � 0.078 � 0.748 � 4.92 � 7.46 � 15.76 � 23 � 51 �
0.00004 0.0002 0.0006 0.004 0.033 0.139 1.03 2.4 57
Single Pulse Ambient
0.001
1E−04 1E−03 1E−02 1E−01 1E+00 1E+01 1E+02 1E+03
t, time (s)
ID, DRAIN CURRENT (AMPS)
, EFFECTIVE TRANSIENT THERMAL RESPONSE
JA
�
R
**----- End of picture text -----**
**Figure 14. FET Thermal Response** **http://onsemi.com** **6** **NTMFS4841N** ## **PACKAGE DIMENSIONS** **==> picture [475 x 582] intentionally omitted <==** **----- Start of picture text -----**
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE G
2 X NOTES:
1. DIMENSIONING AND TOLERANCING PER
0.20 C ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
a D A 3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
2 B 2 X BURRS.
D1 MILLIMETERS
0.20 C
4 DIM MIN NOM MAX
A 0.90 1.00 1.10
A1 0.00 −−− 0.05
E1 4 X b 0.33 0.41 0.51
c 0.23 0.28 0.33
E D 5.15 BSC
2 D1 4.50 4.90 5.10
c D2 3.50 −−− 4.22
a A1 E 6.15 BSC
HH f ec t —= E1 5.50 5.80 6.10
P 1 2 3 T 4 ify EEE E2 3.45 −−− 4.30
e 1.27 BSC
TOP VIEW G 0.51 0.61 0.71
3 X C K 1.20 1.35 1.50
0.10 C S e h SEATINGPLANE = L1L 0.510.05 0.610.17 0.710.20
M 3.00 3.40 3.80
A DETAIL A 0 −−− 12
a ae
0.10 C STYLE 1:
PIN 1. SOURCE
SF SIDE VIEW DETAIL A SOLDERING FOOTPRINT* 2. 3. SOURCESOURCE
4. GATE
3X 4X 5. DRAIN
8X b 1.270 0.750
4X
0.10 C A B 1.000
0.05 c L e/2
1 fe 4 0.965 b oo ts
K
1.330 2X
ft an a 0.905
E2 2X
PIN 5 M 0.495 4.530
(EXPOSED PAD) L1
3.200
0.475
G ac D2 and
2X
BOTTOM VIEW 1.530
rah Lo 4.560 eS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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**----- End of picture text -----**
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